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  • Committer: Mathieu Desnoyers
  • Author(s): Wang Jing
  • Date: 2023-09-06 13:20:24 UTC
  • Revision ID: git-v1:dc46a9c324ae94d89da41ea9a3f97503115df88e
Add LoongArch support

This commit completes LoongArch support.

LoongArch supports byte and short atomic operations,
and defines UATOMIC_HAS_ATOMIC_BYTE and UATOMIC_HAS_ATOMIC_SHORT.

Signed-off-by: Wang Jing <wangjing@loongson.cn>
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I335e654939bfc90994275f2a4fad550c95f3eba4

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// SPDX-License-Identifier: MIT
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/*
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 * Atomic exchange operations for the RISC-V architecture.
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 *
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 * Let the compiler do it.
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 */
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/*
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 * See <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104831> for details.
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 *
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 * Until the following patches are backported, Userspace RCU is broken for the
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 * RISC-V architecture when compiled with GCC.
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 *
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 *  - <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4990cf84c460f064d6281d0813f20b0ef20c7448>
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 *  - <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4990cf84c460f064d6281d0813f20b0ef20c7448>
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 *  - <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=d199d2e56da2379004e7e0457150409c0c99d3e6>
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 */
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#if defined(__GNUC__)
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#  error "Implementations of some atomic operations of GCC for RISC-V \
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          are insufficient for sequential consistency. For this reason \
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          Userspace RCU is currently marked as 'broken' for RISC-V with \
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          GCC. However, it is still possible to use other toolchains."
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#endif
 
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 * Atomic exchange operations for the RISC-V architecture. Let GCC do it.
 
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 */
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#ifndef _URCU_ARCH_UATOMIC_RISCV_H
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#define _URCU_ARCH_UATOMIC_RISCV_H