1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
|
/* -*- mesa-c++ -*-
*
* Copyright (c) 2019 Collabora LTD
*
* Author: Gert Wollny <gert.wollny@collabora.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* on the rights to use, copy, modify, merge, publish, distribute, sub
* license, and/or sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "sfn_emitinstruction.h"
#include "sfn_shader_base.h"
namespace r600 {
EmitInstruction::EmitInstruction(ShaderFromNirProcessor& processor):
m_proc(processor)
{
}
EmitInstruction::~EmitInstruction()
{
}
bool EmitInstruction::emit(nir_instr* instr)
{
return do_emit(instr);
}
PValue EmitInstruction::from_nir(const nir_src& v, unsigned component, unsigned swizzled)
{
return m_proc.from_nir(v, component, swizzled);
}
PValue EmitInstruction::from_nir(const nir_alu_src& v, unsigned component)
{
return m_proc.from_nir(v, component);
}
PValue EmitInstruction::from_nir(const nir_tex_src& v, unsigned component)
{
return m_proc.from_nir(v, component);
}
PValue EmitInstruction::from_nir(const nir_alu_dest& v, unsigned component)
{
return m_proc.from_nir(v, component);
}
PValue EmitInstruction::from_nir(const nir_dest& v, unsigned component)
{
return m_proc.from_nir(v, component);
}
PValue EmitInstruction::from_nir(const nir_src& v, unsigned component)
{
return m_proc.from_nir(v, component);
}
void EmitInstruction::emit_instruction(Instruction *ir)
{
return m_proc.emit_instruction(ir);
}
void EmitInstruction::emit_instruction(AluInstruction *ir)
{
return m_proc.emit_instruction(ir);
}
bool EmitInstruction::emit_instruction(EAluOp opcode, PValue dest,
std::vector<PValue> src0,
const std::set<AluModifiers>& m_flags)
{
return m_proc.emit_instruction(opcode, dest,src0, m_flags);
}
const nir_variable *
EmitInstruction::get_deref_location(const nir_src& v) const
{
return m_proc.get_deref_location(v);
}
PValue EmitInstruction::from_nir_with_fetch_constant(const nir_src& src, unsigned component, int channel)
{
return m_proc.from_nir_with_fetch_constant(src, component, channel);
}
GPRVector EmitInstruction::vec_from_nir_with_fetch_constant(const nir_src& src, unsigned mask,
const GPRVector::Swizzle& swizzle, bool match)
{
return m_proc.vec_from_nir_with_fetch_constant(src, mask, swizzle, match);
}
PGPRValue EmitInstruction::get_temp_register(int channel)
{
return m_proc.get_temp_register(channel);
}
GPRVector EmitInstruction::get_temp_vec4(const GPRVector::Swizzle& swizzle)
{
return m_proc.get_temp_vec4(swizzle);
}
PValue EmitInstruction::create_register_from_nir_src(const nir_src& src, unsigned swizzle)
{
return m_proc.create_register_from_nir_src(src, swizzle);
}
enum chip_class EmitInstruction::get_chip_class(void) const
{
return m_proc.get_chip_class();
}
PValue EmitInstruction::literal(uint32_t value)
{
return m_proc.literal(value);
}
GPRVector EmitInstruction::vec_from_nir(const nir_dest& dst, int num_components)
{
return m_proc.vec_from_nir(dst, num_components);
}
bool EmitInstruction::inject_register(unsigned sel, unsigned swizzle,
const PValue& reg, bool map)
{
return m_proc.inject_register(sel, swizzle, reg, map);
}
int EmitInstruction::remap_atomic_base(int base)
{
return m_proc.remap_atomic_base(base);
}
void EmitInstruction::set_has_txs_cube_array_comp()
{
m_proc.sh_info().has_txq_cube_array_z_comp = 1;
}
const std::set<AluModifiers> EmitInstruction::empty = {};
const std::set<AluModifiers> EmitInstruction::write = {alu_write};
const std::set<AluModifiers> EmitInstruction::last_write = {alu_write, alu_last_instr};
const std::set<AluModifiers> EmitInstruction::last = {alu_last_instr};
}
|