1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
|
#ifndef HWDEF_BLF_GT_H
#define HWDEF_BLF_GT_H
/* BLF GT driver layout
* ----
* Reset -|1 8|- VCC (unused)
* eswitch -|2 7|- Voltage divider
* AUX LED -|3 6|- Current control (buck level)
* GND -|4 5|- PWM (buck output on/off)
* ----
*/
#define PWM_CHANNELS 2
#ifndef AUXLED_PIN
#define AUXLED_PIN PB4 // pin 3
#endif
#ifndef SWITCH_PIN
#define SWITCH_PIN PB3 // pin 2
#define SWITCH_PCINT PCINT3 // pin 2 pin change interrupt
#endif
#ifndef PWM1_PIN
#define PWM1_PIN PB0 // pin 5, 1x7135 PWM
#define PWM1_LVL OCR0A // OCR0A is the output compare register for PB0
#endif
#ifndef PWM2_PIN
#define PWM2_PIN PB1 // pin 6, FET PWM
#define PWM2_LVL OCR0B // OCR0B is the output compare register for PB1
#endif
#define USE_VOLTAGE_DIVIDER // use a voltage divider on pin 7, not VCC
#ifndef VOLTAGE_PIN
#define VOLTAGE_PIN PB2 // pin 7, voltage ADC
#define VOLTAGE_CHANNEL 0x01 // MUX 01 corresponds with PB2
#define VOLTAGE_ADC ADC1D // Digital input disable bit corresponding with PB2
// inherited from tk-attiny.h
//#define VOLTAGE_ADC_DIDR DIDR0 // DIDR for ADC1
// 1.1V reference, left-adjust, ADC1/PB2
//#define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | (1 << ADLAR) | VOLTAGE_CHANNEL)
// 1.1V reference, no left-adjust, ADC1/PB2
#define ADMUX_VOLTAGE_DIVIDER ((1 << V_REF) | VOLTAGE_CHANNEL)
#endif
#define ADC_PRSCL 0x07 // clk/128
// Raw ADC readings at 4.4V and 2.2V (in-between, we assume values form a straight line)
#ifndef ADC_44
#define ADC_44 (184*4)
#endif
#ifndef ADC_22
#define ADC_22 (92*4)
#endif
#define FAST 0xA3 // fast PWM both channels
#define PHASE 0xA1 // phase-correct PWM both channels
#define LAYOUT_DEFINED
#endif
|