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  • Committer: Jens Kuske
  • Date: 2016-03-09 20:01:56 UTC
  • Revision ID: git-v1:c2fb6939920c1354271fac40c290ccf403c698fd
Fix some H.265 parameters

Now all H.265 test bitstreams (except PICSIZE_[ABD], which
might be too wide for the hardware) are decoded correctly.

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added added

removed removed

Lines of Context:
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                p->slice.num_ref_idx_l0_active_minus1 = p->info->num_ref_idx_l0_default_active_minus1;
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                p->slice.num_ref_idx_l1_active_minus1 = p->info->num_ref_idx_l1_default_active_minus1;
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                p->slice.collocated_from_l0_flag = 1;
 
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                p->slice.collocated_ref_idx = 0;
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                p->slice.slice_deblocking_filter_disabled_flag = p->info->pps_deblocking_filter_disabled_flag;
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                p->slice.slice_beta_offset_div2 = p->info->pps_beta_offset_div2;
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                p->slice.slice_tc_offset_div2 = p->info->pps_tc_offset_div2;
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                        for (i = 0; i < p->info->NumPocStCurrAfter && rIdx < NumRpsCurrTempList0; rIdx++, i++)
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                                RefPicListTemp0[rIdx] = p->info->RefPicSetStCurrAfter[i];
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                        for (i = 0; i < p->info->NumPocLtCurr && rIdx < NumRpsCurrTempList0; rIdx++, i++)
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                                RefPicListTemp0[rIdx] = p->info->RefPicSetLtCurr[i];
 
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                                RefPicListTemp0[rIdx] = p->info->RefPicSetLtCurr[i] | (1 << 7);
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                }
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                writel(VE_SRAM_HEVC_REF_PIC_LIST0, p->regs + VE_HEVC_SRAM_ADDR);
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                        for (i = 0; i < p->info->NumPocStCurrBefore && rIdx < NumRpsCurrTempList1; rIdx++, i++)
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                                RefPicListTemp1[rIdx] = p->info->RefPicSetStCurrBefore[i];
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                        for (i = 0; i < p->info->NumPocLtCurr && rIdx < NumRpsCurrTempList1; rIdx++, i++)
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                                RefPicListTemp1[rIdx] = p->info->RefPicSetLtCurr[i];
 
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                                RefPicListTemp1[rIdx] = p->info->RefPicSetLtCurr[i] | (1 << 7);
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                }
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                writel(VE_SRAM_HEVC_REF_PIC_LIST1, p->regs + VE_HEVC_SRAM_ADDR);
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                writel(0x40 | p->nal_unit_type, p->regs + VE_HEVC_NAL_HDR);
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                writel(0x00018001 |
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                        ((p->info->strong_intra_smoothing_enabled_flag & 0x1) << 26) |
 
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                writel(((p->info->strong_intra_smoothing_enabled_flag & 0x1) << 26) |
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                        ((p->info->sps_temporal_mvp_enabled_flag & 0x1) << 25) |
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                        ((p->info->sample_adaptive_offset_enabled_flag & 0x1) << 24) |
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                        ((p->info->amp_enabled_flag & 0x1) << 23) |
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                        ((p->info->max_transform_hierarchy_depth_intra & 0x7) << 20) |
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                        ((p->info->max_transform_hierarchy_depth_inter & 0x7) << 17) |
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                        ((p->info->log2_diff_max_min_luma_coding_block_size & 0x3) << 11), p->regs + VE_HEVC_SPS);
 
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                        ((p->info->log2_diff_max_min_transform_block_size & 0x3) << 15) |
 
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                        ((p->info->log2_min_transform_block_size_minus2 & 0x3) << 13) |
 
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                        ((p->info->log2_diff_max_min_luma_coding_block_size & 0x3) << 11) |
 
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                        ((p->info->log2_min_luma_coding_block_size_minus3 & 0x3) << 9) |
 
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                        ((p->info->chroma_format_idc & 0x3) << 0), p->regs + VE_HEVC_SPS);
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                writel((decoder->height << 16) | decoder->width, p->regs + VE_HEVC_PIC_SIZE);
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                        ((p->info->diff_cu_qp_delta_depth & 0xf) << 4) |
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                        ((p->info->cu_qp_delta_enabled_flag & 0x1) << 3) |
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                        ((p->info->transform_skip_enabled_flag & 0x1) << 2) |
 
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                        ((p->info->constrained_intra_pred_flag & 0x1) << 1) |
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                        ((p->info->sign_data_hiding_enabled_flag & 0x1) << 0), p->regs + VE_HEVC_PPS0);
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                writel(((p->info->pps_loop_filter_across_slices_enabled_flag & 0x1) << 6) |
 
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                writel(((p->info->log2_parallel_merge_level_minus2 & 0x7) << 8) |
 
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                        ((p->info->pps_loop_filter_across_slices_enabled_flag & 0x1) << 6) |
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                        ((p->info->loop_filter_across_tiles_enabled_flag & 0x1) << 5) |
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                        ((p->info->entropy_coding_sync_enabled_flag & 0x1) << 4) |
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                        ((p->info->tiles_enabled_flag & 0x1) << 3) |
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                writel(0xc0000000, p->regs + VE_EXTRA_OUT_FMT_OFFSET);
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                writel((0x2 << 4), p->regs + 0x0ec);
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                writel(output->chroma_size / 2, p->regs + 0x0c4);
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                writel(((decoder->width / 2) << 16) | decoder->width, p->regs + 0x0c8);
 
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                writel((ALIGN(decoder->width / 2, 16) << 16) | ALIGN(decoder->width, 32), p->regs + 0x0c8);
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                writel(0x00000000, p->regs + 0x0cc);
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                writel(0x00000000, p->regs + 0x550);
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                writel(0x00000000, p->regs + 0x554);