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186.1.1
by Selene Scriven
Imported Emisar D4 RampingIOS code from Tom E. |
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#ifndef TK_ATTINY_H
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#define TK_ATTINY_H
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/*
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* Attiny portability header.
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* This helps abstract away the differences between various attiny MCUs.
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*
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* Copyright (C) 2015 Selene Scriven
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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// Choose your MCU here, or in the main .c file, or in the build script
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//#define ATTINY 13
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//#define ATTINY 25
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/******************** hardware-specific values **************************/
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#if (ATTINY == 13)
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#define F_CPU 4800000UL
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#define EEPSIZE 64
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#define V_REF REFS0
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#define BOGOMIPS 950
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#elif (ATTINY == 25)
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// TODO: Use 6.4 MHz instead of 8 MHz?
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#define F_CPU 8000000UL
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#define EEPSIZE 128
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#define V_REF REFS1
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#define BOGOMIPS 2000
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#elif (ATTINY == 85)
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// TODO: Use 6.4 MHz instead of 8 MHz?
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#define F_CPU 8000000UL
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#define EEPSIZE 512
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#define V_REF REFS1
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#define BOGOMIPS 2000
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#else
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Hey, you need to define ATTINY. |
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#endif
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/******************** I/O pin and register layout ************************/
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/*
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* ----
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* Reset -|1 8|- VCC
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* OTC -|2 7|- Voltage ADC
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* Star 3 -|3 6|- PWM (FET)
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* GND -|4 5|- PWM (1x7135)
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* ----
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*/
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#define STAR2_PIN PB0 // If this pin isn't used for ALT_PWM |
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#define STAR3_PIN PB4 // pin 3 |
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#define CAP_PIN PB3 // pin 2, OTC |
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#define CAP_CHANNEL 0x03 // MUX 03 corresponds with PB3 (Star 4) |
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#define CAP_DIDR ADC3D // Digital input disable bit corresponding with PB3 |
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#define PWM_PIN PB1 // pin 6, FET PWM |
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#define PWM_LVL OCR0B // OCR0B is the output compare register for PB1 |
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#define ALT_PWM_PIN PB0 // pin 5, 1x7135 PWM |
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#define ALT_PWM_LVL OCR0A // OCR0A is the output compare register for PB0 |
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#define VOLTAGE_PIN PB2 // pin 7, voltage ADC |
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#define ADC_CHANNEL 0x01 // MUX 01 corresponds with PB2 |
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#define ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2 |
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#define ADC_PRSCL 0x06 // clk/64 |
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//#define TEMP_DIDR ADC4D
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#define TEMP_CHANNEL 0b00001111
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#endif // TK_ATTINY_H |