188.33.14
by Selene ToyKeeper
switched the rest of FSM + Anduril to use SPDX license headers |
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// MF01-Mini driver layout
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// Copyright (C) 2019-2023 Selene ToyKeeper
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// SPDX-License-Identifier: GPL-3.0-or-later
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#pragma once
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188.11.7
by Selene Scriven
added support for Mateminco MF01-Mini |
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188.33.14
by Selene ToyKeeper
switched the rest of FSM + Anduril to use SPDX license headers |
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/*
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188.11.7
by Selene Scriven
added support for Mateminco MF01-Mini |
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* ----
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* Reset -|1 8|- VCC
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* eswitch -|2 7|- aux LEDs
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* FET PWM -|3 6|- PWM (7x7135)
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* GND -|4 5|- PWM (1x7135)
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* ----
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*/
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#define PWM_CHANNELS 3
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#ifndef AUXLED_PIN
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#define AUXLED_PIN PB2 // pin 7 |
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#endif
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#ifndef SWITCH_PIN
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#define SWITCH_PIN PB3 // pin 2 |
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#define SWITCH_PCINT PCINT3 // pin 2 pin change interrupt |
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#endif
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#ifndef PWM1_PIN
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#define PWM1_PIN PB0 // pin 5, 1x7135 PWM |
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#define PWM1_LVL OCR0A // OCR0A is the output compare register for PB0 |
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#endif
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#ifndef PWM2_PIN
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188.11.10
by Selene Scriven
just cleaning up some comments |
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#define PWM2_PIN PB1 // pin 6, 7x7135 PWM |
188.11.7
by Selene Scriven
added support for Mateminco MF01-Mini |
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#define PWM2_LVL OCR0B // OCR0B is the output compare register for PB1 |
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#endif
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#ifndef PWM3_PIN
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#define PWM3_PIN PB4 // pin 3, FET PWM |
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#define PWM3_LVL OCR1B // OCR1B is the output compare register for PB4 |
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#endif
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188.15.11
by Selene Scriven
went back to slower clk/128 ADC timing |
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#define ADC_PRSCL 0x07 // clk/128 |
188.11.7
by Selene Scriven
added support for Mateminco MF01-Mini |
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// average drop across diode on this hardware
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#ifndef VOLTAGE_FUDGE_FACTOR
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#define VOLTAGE_FUDGE_FACTOR 5 // add 0.25V |
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#endif
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#define FAST 0xA3 // fast PWM both channels |
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#define PHASE 0xA1 // phase-correct PWM both channels |
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#define LAYOUT_DEFINED
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