1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
|
#ifndef HWDEF_NANJG_H
#define HWDEF_NANJG_H
/* NANJG driver layout
*/
#define STAR2_PIN PB0
#define STAR3_PIN PB4
#define STAR4_PIN PB3
#define PWM_PIN PB1
#define VOLTAGE_PIN PB2
#define ADC_CHANNEL 0x01 // MUX 01 corresponds with PB2
#define ADC_DIDR ADC1D // Digital input disable bit corresponding with PB2
#define ADC_PRSCL 0x06 // clk/64
#define PWM_LVL OCR0B // OCR0B is the output compare register for PB1
#define FAST 0x23 // fast PWM channel 1 only
#define PHASE 0x21 // phase-correct PWM channel 1 only
#define LAYOUT_DEFINED
#endif
|