298
301
/* Calculate the min / max delta */
299
302
hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
300
303
&hpet_clockevent);
301
/* 5 usec minimum reprogramming delta. */
302
hpet_clockevent.min_delta_ns = 5000;
304
/* Setup minimum reprogramming delta. */
305
hpet_clockevent.min_delta_ns = clockevent_delta2ns(HPET_MIN_PROG_DELTA,
305
309
* Start hpet with the boot cpu mask and make it
379
383
struct clock_event_device *evt, int timer)
383
388
cnt = hpet_readl(HPET_COUNTER);
384
389
cnt += (u32) delta;
385
390
hpet_writel(cnt, HPET_Tn_CMP(timer));
388
* We need to read back the CMP register on certain HPET
389
* implementations (ATI chipsets) which seem to delay the
390
* transfer of the compare register into the internal compare
391
* logic. With small deltas this might actually be too late as
392
* the counter could already be higher than the compare value
393
* at that point and we would wait for the next hpet interrupt
394
* forever. We found out that reading the CMP register back
395
* forces the transfer so we can rely on the comparison with
396
* the counter register below. If the read back from the
397
* compare register does not match the value we programmed
398
* then we might have a real hardware problem. We can not do
399
* much about it here, but at least alert the user/admin with
400
* a prominent warning.
401
* An erratum on some chipsets (ICH9,..), results in comparator read
402
* immediately following a write returning old value. Workaround
403
* for this is to read this value second time, when first
404
* read returns old value.
393
* HPETs are a complete disaster. The compare register is
394
* based on a equal comparison and neither provides a less
395
* than or equal functionality (which would require to take
396
* the wraparound into account) nor a simple count down event
397
* mode. Further the write to the comparator register is
398
* delayed internally up to two HPET clock cycles in certain
399
* chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
400
* longer delays. We worked around that by reading back the
401
* compare register, but that required another workaround for
402
* ICH9,10 chips where the first readout after write can
403
* return the old stale value. We already had a minimum
404
* programming delta of 5us enforced, but a NMI or SMI hitting
405
* between the counter readout and the comparator write can
406
* move us behind that point easily. Now instead of reading
407
* the compare register back several times, we make the ETIME
408
* decision based on the following: Return ETIME if the
409
* counter value after the write is less than HPET_MIN_CYCLES
410
* away from the event or if the counter is already ahead of
411
* the event. The minimum programming delta for the generic
412
* clockevents code is set to 1.5 * HPET_MIN_CYCLES.
406
if (unlikely((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt)) {
407
WARN_ONCE((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt,
408
KERN_WARNING "hpet: compare register read back failed.\n");
414
res = (s32)(cnt - (u32)hpet_readl(HPET_COUNTER));
411
return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
416
return res < HPET_MIN_CYCLES ? -ETIME : 0;
414
419
static void hpet_legacy_set_mode(enum clock_event_mode mode,