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7
by Herton Ronaldo Krzesinski, Herton Ronaldo Krzesinski, Tim Gardner
[ Herton Ronaldo Krzesinski ] |
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/*
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* Copyright (c) 2010 Broadcom Corporation
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _HNDSOC_H
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#define _HNDSOC_H
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/* Include the soci specific files */
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#include <sbconfig.h> |
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#include <aidmp.h> |
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/*
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* SOC Interconnect Address Map.
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* All regions may not exist on all chips.
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*/
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#define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */ |
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#define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */ |
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#define SI_PCI_MEM_SZ (64 * 1024 * 1024)
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#define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */ |
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#define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ |
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#define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */ |
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#ifdef SI_ENUM_BASE_VARIABLE
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#define SI_ENUM_BASE (sii->pub.si_enum_base)
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#else
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#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */ |
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#endif /* SI_ENUM_BASE_VARIABLE */ |
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#define SI_WRAP_BASE 0x18100000 /* Wrapper space base */ |
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#define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ |
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#define SI_MAXCORES 16 /* Max cores (this is arbitrary, for software |
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* convenience and could be changed if we
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* make any larger chips
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*/
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#define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */ |
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#define SI_FASTRAM_SWAPPED 0x19800000
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#define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ |
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#define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ |
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#define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */ |
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#define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ |
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#define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ |
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#define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */ |
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#define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */ |
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#define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */ |
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#define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */ |
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#define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */ |
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#define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */ |
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#define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */ |
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#define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */ |
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#define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 |
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* (2 ZettaBytes), low 32 bits
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*/
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#define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 |
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* (2 ZettaBytes), high 32 bits
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*/
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/* core codes */
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#define NODEV_CORE_ID 0x700 /* Invalid coreid */ |
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#define CC_CORE_ID 0x800 /* chipcommon core */ |
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#define ILINE20_CORE_ID 0x801 /* iline20 core */ |
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#define SRAM_CORE_ID 0x802 /* sram core */ |
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#define SDRAM_CORE_ID 0x803 /* sdram core */ |
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#define PCI_CORE_ID 0x804 /* pci core */ |
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#define MIPS_CORE_ID 0x805 /* mips core */ |
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#define ENET_CORE_ID 0x806 /* enet mac core */ |
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#define CODEC_CORE_ID 0x807 /* v90 codec core */ |
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#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */ |
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#define ADSL_CORE_ID 0x809 /* ADSL core */ |
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#define ILINE100_CORE_ID 0x80a /* iline100 core */ |
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#define IPSEC_CORE_ID 0x80b /* ipsec core */ |
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#define UTOPIA_CORE_ID 0x80c /* utopia core */ |
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#define PCMCIA_CORE_ID 0x80d /* pcmcia core */ |
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#define SOCRAM_CORE_ID 0x80e /* internal memory core */ |
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#define MEMC_CORE_ID 0x80f /* memc sdram core */ |
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#define OFDM_CORE_ID 0x810 /* OFDM phy core */ |
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#define EXTIF_CORE_ID 0x811 /* external interface core */ |
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#define D11_CORE_ID 0x812 /* 802.11 MAC core */ |
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#define APHY_CORE_ID 0x813 /* 802.11a phy core */ |
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#define BPHY_CORE_ID 0x814 /* 802.11b phy core */ |
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#define GPHY_CORE_ID 0x815 /* 802.11g phy core */ |
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#define MIPS33_CORE_ID 0x816 /* mips3302 core */ |
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#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */ |
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#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */ |
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#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */ |
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#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */ |
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#define SDIOH_CORE_ID 0x81b /* sdio host core */ |
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#define ROBO_CORE_ID 0x81c /* roboswitch core */ |
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#define ATA100_CORE_ID 0x81d /* parallel ATA core */ |
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#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */ |
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#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */ |
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#define PCIE_CORE_ID 0x820 /* pci express core */ |
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#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */ |
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#define SRAMC_CORE_ID 0x822 /* SRAM controller core */ |
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#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */ |
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#define ARM11_CORE_ID 0x824 /* ARM 1176 core */ |
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#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */ |
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#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */ |
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#define PMU_CORE_ID 0x827 /* PMU core */ |
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#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */ |
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#define SDIOD_CORE_ID 0x829 /* SDIO device core */ |
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#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */ |
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#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */ |
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#define MIPS74K_CORE_ID 0x82c /* mips 74k core */ |
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#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */ |
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#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */ |
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#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */ |
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#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */ |
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#define SC_CORE_ID 0x831 /* shared common core */ |
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#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */ |
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#define SPIH_CORE_ID 0x833 /* SPI host core */ |
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#define I2S_CORE_ID 0x834 /* I2S core */ |
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#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */ |
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#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */ |
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#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */ |
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#define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all |
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* unused address ranges
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*/
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/* There are TWO constants on all HND chips: SI_ENUM_BASE above,
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* and chipcommon being the first core:
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*/
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#define SI_CC_IDX 0
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/* SOC Interconnect types (aka chip types) */
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#define SOCI_AI 1
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/* Common core control flags */
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#define SICF_BIST_EN 0x8000
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#define SICF_PME_EN 0x4000
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#define SICF_CORE_BITS 0x3ffc
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#define SICF_FGC 0x0002
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#define SICF_CLOCK_EN 0x0001
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/* Common core status flags */
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#define SISF_BIST_DONE 0x8000
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#define SISF_BIST_ERROR 0x4000
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#define SISF_GATED_CLK 0x2000
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#define SISF_DMA64 0x1000
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#define SISF_CORE_BITS 0x0fff
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/* A register that is common to all cores to
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* communicate w/PMU regarding clock control.
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*/
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#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */ |
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/* clk_ctl_st register */
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#define CCS_FORCEALP 0x00000001 /* force ALP request */ |
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#define CCS_FORCEHT 0x00000002 /* force HT request */ |
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#define CCS_FORCEILP 0x00000004 /* force ILP request */ |
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#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */ |
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#define CCS_HTAREQ 0x00000010 /* HT Avail Request */ |
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#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */ |
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#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */ |
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#define CCS_ERSRC_REQ_SHIFT 8
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#define CCS_ALPAVAIL 0x00010000 /* ALP is available */ |
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#define CCS_HTAVAIL 0x00020000 /* HT is available */ |
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#define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */ |
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#define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */ |
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#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */ |
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#define CCS_ERSRC_STS_SHIFT 24
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#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */ |
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#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */ |
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/* Not really related to SOC Interconnect, but a couple of software
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* conventions for the use the flash space:
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*/
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/* Minimum amount of flash we support */
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#define FLASH_MIN 0x00020000 /* Minimum flash size */ |
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/* A boot/binary may have an embedded block that describes its size */
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#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */ |
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#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */ |
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#define BISZ_MAGIC_IDX 0 /* Word 0: magic */ |
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#define BISZ_TXTST_IDX 1 /* 1: text start */ |
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#define BISZ_TXTEND_IDX 2 /* 2: text end */ |
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#define BISZ_DATAST_IDX 3 /* 3: data start */ |
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#define BISZ_DATAEND_IDX 4 /* 4: data end */ |
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#define BISZ_BSSST_IDX 5 /* 5: bss start */ |
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#define BISZ_BSSEND_IDX 6 /* 6: bss end */ |
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#define BISZ_SIZE 7 /* descriptor size in 32-bit integers */ |
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#endif /* _HNDSOC_H */ |