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  • Committer: Package Import Robot
  • Author(s): Maarten Lankhorst
  • Date: 2013-06-19 10:24:58 UTC
  • Revision ID: package-import@ubuntu.com-20130619102458-mgo60tk6i26cctj0
Tags: 2.4.43-0ubuntu0.0.2
* Added patches to add/fix Haswell pci-id's (LP: #1175533)
  - fix-hsw-crw-ids.diff
  - fix-hsw-gt3-names.diff
  - add-more-reserved-hsw-ids.diff

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commit 1669a67d063e82a58dae4d906015172d471e9a2a
 
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Author: Rodrigo Vivi <rodrigo.vivi@gmail.com>
 
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Date:   Mon May 13 17:48:40 2013 -0300
 
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    intel: Adding more reserved PCI IDs for Haswell.
 
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    At DDX commit Chris mentioned the tendency we have of finding out more
 
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    PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
 
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    Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701
 
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    Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
 
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    Acked-by: Kenneth Graunke <kenneth@whitecape.org>
 
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diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
 
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index 3350def..aeb439e 100644
 
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--- a/intel/intel_chipset.h
 
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+++ b/intel/intel_chipset.h
 
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@@ -97,6 +97,12 @@
 
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 #define PCI_CHIP_HASWELL_S_GT1         0x040A /* Server */
 
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 #define PCI_CHIP_HASWELL_S_GT2         0x041A
 
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 #define PCI_CHIP_HASWELL_S_GT3         0x042A
 
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+#define PCI_CHIP_HASWELL_B_GT1         0x040B /* Reserved */
 
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+#define PCI_CHIP_HASWELL_B_GT2         0x041B
 
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+#define PCI_CHIP_HASWELL_B_GT3         0x042B
 
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+#define PCI_CHIP_HASWELL_E_GT1         0x040E /* Reserved */
 
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+#define PCI_CHIP_HASWELL_E_GT2         0x041E
 
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+#define PCI_CHIP_HASWELL_E_GT3         0x042E
 
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 #define PCI_CHIP_HASWELL_SDV_GT1       0x0C02 /* Desktop */
 
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 #define PCI_CHIP_HASWELL_SDV_GT2       0x0C12
 
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 #define PCI_CHIP_HASWELL_SDV_GT3       0x0C22
 
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@@ -106,6 +112,12 @@
 
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 #define PCI_CHIP_HASWELL_SDV_S_GT1     0x0C0A /* Server */
 
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 #define PCI_CHIP_HASWELL_SDV_S_GT2     0x0C1A
 
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 #define PCI_CHIP_HASWELL_SDV_S_GT3     0x0C2A
 
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+#define PCI_CHIP_HASWELL_SDV_B_GT1     0x0C0B /* Reserved */
 
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+#define PCI_CHIP_HASWELL_SDV_B_GT2     0x0C1B
 
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+#define PCI_CHIP_HASWELL_SDV_B_GT3     0x0C2B
 
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+#define PCI_CHIP_HASWELL_SDV_E_GT1     0x0C0E /* Reserved */
 
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+#define PCI_CHIP_HASWELL_SDV_E_GT2     0x0C1E
 
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+#define PCI_CHIP_HASWELL_SDV_E_GT3     0x0C2E
 
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 #define PCI_CHIP_HASWELL_ULT_GT1       0x0A02 /* Desktop */
 
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 #define PCI_CHIP_HASWELL_ULT_GT2       0x0A12
 
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 #define PCI_CHIP_HASWELL_ULT_GT3       0x0A22
 
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@@ -115,6 +127,12 @@
 
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 #define PCI_CHIP_HASWELL_ULT_S_GT1     0x0A0A /* Server */
 
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 #define PCI_CHIP_HASWELL_ULT_S_GT2     0x0A1A
 
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 #define PCI_CHIP_HASWELL_ULT_S_GT3     0x0A2A
 
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+#define PCI_CHIP_HASWELL_ULT_B_GT1     0x0A0B /* Reserved */
 
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+#define PCI_CHIP_HASWELL_ULT_B_GT2     0x0A1B
 
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+#define PCI_CHIP_HASWELL_ULT_B_GT3     0x0A2B
 
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+#define PCI_CHIP_HASWELL_ULT_E_GT1     0x0A0E /* Reserved */
 
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+#define PCI_CHIP_HASWELL_ULT_E_GT2     0x0A1E
 
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+#define PCI_CHIP_HASWELL_ULT_E_GT3     0x0A2E
 
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 #define PCI_CHIP_HASWELL_CRW_GT1       0x0D02 /* Desktop */
 
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 #define PCI_CHIP_HASWELL_CRW_GT2       0x0D12
 
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 #define PCI_CHIP_HASWELL_CRW_GT3       0x0D22
 
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@@ -124,6 +142,12 @@
 
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 #define PCI_CHIP_HASWELL_CRW_S_GT1     0x0D0A /* Server */
 
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 #define PCI_CHIP_HASWELL_CRW_S_GT2     0x0D1A
 
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 #define PCI_CHIP_HASWELL_CRW_S_GT3     0x0D2A
 
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+#define PCI_CHIP_HASWELL_CRW_B_GT1     0x0D0B /* Reserved */
 
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+#define PCI_CHIP_HASWELL_CRW_B_GT2     0x0D1B
 
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+#define PCI_CHIP_HASWELL_CRW_B_GT3     0x0D2B
 
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+#define PCI_CHIP_HASWELL_CRW_E_GT1     0x0D0E /* Reserved */
 
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+#define PCI_CHIP_HASWELL_CRW_E_GT2     0x0D1E
 
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+#define PCI_CHIP_HASWELL_CRW_E_GT3     0x0D2E
 
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 #define PCI_CHIP_VALLEYVIEW_PO         0x0f30 /* VLV PO board */
 
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 #define PCI_CHIP_VALLEYVIEW_1          0x0f31
 
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@@ -210,39 +234,63 @@
 
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 #define IS_HSW_GT1(devid)      ((devid) == PCI_CHIP_HASWELL_GT1 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_B_GT1 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_E_GT1 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
 
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-                                (devid) == PCI_CHIP_HASWELL_CRW_S_GT1)
 
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+                                (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
 
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 #define IS_HSW_GT2(devid)      ((devid) == PCI_CHIP_HASWELL_GT2 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_B_GT2 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_E_GT2 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
 
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-                                (devid) == PCI_CHIP_HASWELL_CRW_S_GT2)
 
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+                                (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
 
113
 #define IS_HSW_GT3(devid)      ((devid) == PCI_CHIP_HASWELL_GT3 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_B_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_E_GT3 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
 
119
                                 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
 
124
                                 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
 
126
+                                (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
 
127
+                                (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
 
128
                                 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
 
129
                                 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
 
130
-                                (devid) == PCI_CHIP_HASWELL_CRW_S_GT3)
 
131
+                                (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
 
132
+                                (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
 
134
 
 
135
 #define IS_HASWELL(devid)      (IS_HSW_GT1(devid) || \
 
136
                                 IS_HSW_GT2(devid) || \