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Viewing changes to debian/patches/fix-hsw-crw-ids.diff

  • Committer: Package Import Robot
  • Author(s): Maarten Lankhorst
  • Date: 2013-06-19 10:24:58 UTC
  • Revision ID: package-import@ubuntu.com-20130619102458-mgo60tk6i26cctj0
Tags: 2.4.43-0ubuntu0.0.2
* Added patches to add/fix Haswell pci-id's (LP: #1175533)
  - fix-hsw-crw-ids.diff
  - fix-hsw-gt3-names.diff
  - add-more-reserved-hsw-ids.diff

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commit ca678bc073462623cfc89dea80271bc361f1655f
 
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Author: Kenneth Graunke <kenneth@whitecape.org>
 
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Date:   Fri Mar 1 15:37:01 2013 -0800
 
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    intel: Fix Haswell CRW PCI IDs.
 
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    The second digit was off by one, which meant we accidentally treated
 
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    GT(n) as GT(n-1).  This also meant no support for GT1 at all.
 
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    Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
 
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diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
 
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index 2760dc8..5aea3f2 100644
 
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--- a/intel/intel_chipset.h
 
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+++ b/intel/intel_chipset.h
 
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@@ -115,15 +115,15 @@
 
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 #define PCI_CHIP_HASWELL_ULT_S_GT1     0x0A0A /* Server */
 
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 #define PCI_CHIP_HASWELL_ULT_S_GT2     0x0A1A
 
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 #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS        0x0A2A
 
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-#define PCI_CHIP_HASWELL_CRW_GT1       0x0D12 /* Desktop */
 
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-#define PCI_CHIP_HASWELL_CRW_GT2       0x0D22
 
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-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS  0x0D32
 
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-#define PCI_CHIP_HASWELL_CRW_M_GT1     0x0D16 /* Mobile */
 
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-#define PCI_CHIP_HASWELL_CRW_M_GT2     0x0D26
 
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-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS        0x0D36
 
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-#define PCI_CHIP_HASWELL_CRW_S_GT1     0x0D1A /* Server */
 
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-#define PCI_CHIP_HASWELL_CRW_S_GT2     0x0D2A
 
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-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS        0x0D3A
 
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+#define PCI_CHIP_HASWELL_CRW_GT1       0x0D02 /* Desktop */
 
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+#define PCI_CHIP_HASWELL_CRW_GT2       0x0D12
 
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+#define PCI_CHIP_HASWELL_CRW_GT2_PLUS  0x0D22
 
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+#define PCI_CHIP_HASWELL_CRW_M_GT1     0x0D06 /* Mobile */
 
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+#define PCI_CHIP_HASWELL_CRW_M_GT2     0x0D16
 
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+#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS        0x0D26
 
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+#define PCI_CHIP_HASWELL_CRW_S_GT1     0x0D0A /* Server */
 
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+#define PCI_CHIP_HASWELL_CRW_S_GT2     0x0D1A
 
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+#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS        0x0D2A
 
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 #define PCI_CHIP_VALLEYVIEW_PO         0x0f30 /* VLV PO board */
 
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 #define PCI_CHIP_VALLEYVIEW_1          0x0f31