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Viewing changes to debian/patches/fix-hsw-gt3-names.diff

  • Committer: Package Import Robot
  • Author(s): Maarten Lankhorst
  • Date: 2013-06-19 10:24:58 UTC
  • Revision ID: package-import@ubuntu.com-20130619102458-mgo60tk6i26cctj0
Tags: 2.4.43-0ubuntu0.0.2
https://launchpad.net/bugs/1175533
* Added patches to add/fix Haswell pci-id's (LP: #1175533)
  - fix-hsw-crw-ids.diff
  - fix-hsw-gt3-names.diff
  - add-more-reserved-hsw-ids.diff

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debian/patches/fix-hsw-gt3-names.diff
 
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commit 150c3555e7ba53f6ad2d3970cca8e4d5970410aa
 
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Author: Rodrigo Vivi <rodrigo.vivi@gmail.com>
 
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Date:   Mon May 13 17:48:39 2013 -0300
 
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    intel: Fix Haswell GT3 names.
 
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    When publishing first HSW ids we weren't allowed to use "GT3" codname.
 
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    But this is the correct codname and Mesa is using it already.
 
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    So to avoid people getting confused why in Mesa it is called GT3 and here
 
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    it is called GT2_PLUS let's fix this name in a standard and correct way.
 
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    Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
 
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    Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
 
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    Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 
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diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
 
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index 5aea3f2..3350def 100644
 
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--- a/intel/intel_chipset.h
 
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+++ b/intel/intel_chipset.h
 
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@@ -90,40 +90,40 @@
 
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 #define PCI_CHIP_HASWELL_GT1           0x0402 /* Desktop */
 
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 #define PCI_CHIP_HASWELL_GT2           0x0412
 
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-#define PCI_CHIP_HASWELL_GT2_PLUS      0x0422
 
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+#define PCI_CHIP_HASWELL_GT3           0x0422
 
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 #define PCI_CHIP_HASWELL_M_GT1         0x0406 /* Mobile */
 
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 #define PCI_CHIP_HASWELL_M_GT2         0x0416
 
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-#define PCI_CHIP_HASWELL_M_GT2_PLUS    0x0426
 
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+#define PCI_CHIP_HASWELL_M_GT3         0x0426
 
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 #define PCI_CHIP_HASWELL_S_GT1         0x040A /* Server */
 
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 #define PCI_CHIP_HASWELL_S_GT2         0x041A
 
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-#define PCI_CHIP_HASWELL_S_GT2_PLUS    0x042A
 
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+#define PCI_CHIP_HASWELL_S_GT3         0x042A
 
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 #define PCI_CHIP_HASWELL_SDV_GT1       0x0C02 /* Desktop */
 
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 #define PCI_CHIP_HASWELL_SDV_GT2       0x0C12
 
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-#define PCI_CHIP_HASWELL_SDV_GT2_PLUS  0x0C22
 
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+#define PCI_CHIP_HASWELL_SDV_GT3       0x0C22
 
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 #define PCI_CHIP_HASWELL_SDV_M_GT1     0x0C06 /* Mobile */
 
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 #define PCI_CHIP_HASWELL_SDV_M_GT2     0x0C16
 
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-#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS        0x0C26
 
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+#define PCI_CHIP_HASWELL_SDV_M_GT3     0x0C26
 
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 #define PCI_CHIP_HASWELL_SDV_S_GT1     0x0C0A /* Server */
 
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 #define PCI_CHIP_HASWELL_SDV_S_GT2     0x0C1A
 
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-#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS        0x0C2A
 
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+#define PCI_CHIP_HASWELL_SDV_S_GT3     0x0C2A
 
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 #define PCI_CHIP_HASWELL_ULT_GT1       0x0A02 /* Desktop */
 
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 #define PCI_CHIP_HASWELL_ULT_GT2       0x0A12
 
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-#define PCI_CHIP_HASWELL_ULT_GT2_PLUS  0x0A22
 
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+#define PCI_CHIP_HASWELL_ULT_GT3       0x0A22
 
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 #define PCI_CHIP_HASWELL_ULT_M_GT1     0x0A06 /* Mobile */
 
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 #define PCI_CHIP_HASWELL_ULT_M_GT2     0x0A16
 
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-#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS        0x0A26
 
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+#define PCI_CHIP_HASWELL_ULT_M_GT3     0x0A26
 
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 #define PCI_CHIP_HASWELL_ULT_S_GT1     0x0A0A /* Server */
 
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 #define PCI_CHIP_HASWELL_ULT_S_GT2     0x0A1A
 
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-#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS        0x0A2A
 
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+#define PCI_CHIP_HASWELL_ULT_S_GT3     0x0A2A
 
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 #define PCI_CHIP_HASWELL_CRW_GT1       0x0D02 /* Desktop */
 
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 #define PCI_CHIP_HASWELL_CRW_GT2       0x0D12
 
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-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS  0x0D22
 
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+#define PCI_CHIP_HASWELL_CRW_GT3       0x0D22
 
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 #define PCI_CHIP_HASWELL_CRW_M_GT1     0x0D06 /* Mobile */
 
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 #define PCI_CHIP_HASWELL_CRW_M_GT2     0x0D16
 
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-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS        0x0D26
 
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+#define PCI_CHIP_HASWELL_CRW_M_GT3     0x0D26
 
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 #define PCI_CHIP_HASWELL_CRW_S_GT1     0x0D0A /* Server */
 
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 #define PCI_CHIP_HASWELL_CRW_S_GT2     0x0D1A
 
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-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS        0x0D2A
 
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+#define PCI_CHIP_HASWELL_CRW_S_GT3     0x0D2A
 
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 #define PCI_CHIP_VALLEYVIEW_PO         0x0f30 /* VLV PO board */
 
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 #define PCI_CHIP_VALLEYVIEW_1          0x0f31
 
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@@ -230,22 +230,23 @@
 
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                                 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
 
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                                 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
 
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-                                (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
 
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-                                (devid) == PCI_CHIP_HASWELL_GT2_PLUS || \
 
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-                                (devid) == PCI_CHIP_HASWELL_M_GT2_PLUS || \
 
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-                                (devid) == PCI_CHIP_HASWELL_S_GT2_PLUS || \
 
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-                                (devid) == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
 
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-                                (devid) == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
 
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-                                (devid) == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
 
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-                                (devid) == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
 
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-                                (devid) == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
 
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-                                (devid) == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
 
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-                                (devid) == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
 
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-                                (devid) == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
 
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-                                (devid) == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
 
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+                                (devid) == PCI_CHIP_HASWELL_CRW_S_GT2)
 
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+#define IS_HSW_GT3(devid)      ((devid) == PCI_CHIP_HASWELL_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_M_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_S_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
 
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+                                (devid) == PCI_CHIP_HASWELL_CRW_S_GT3)
 
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 #define IS_HASWELL(devid)      (IS_HSW_GT1(devid) || \
 
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-                                IS_HSW_GT2(devid))
 
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+                                IS_HSW_GT2(devid) || \
 
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+                                IS_HSW_GT3(devid))
 
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 #define IS_9XX(dev)            (IS_GEN3(dev) || \
 
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                                 IS_GEN4(dev) || \