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Viewing changes to debian/patches/fix-hsw-crw-ids.diff

  • Committer: Package Import Robot
  • Author(s): Maarten Lankhorst
  • Date: 2013-06-19 12:00:59 UTC
  • Revision ID: package-import@ubuntu.com-20130619120059-jlt0e9ghrs6pkcfs
Tags: 2:2.20.9-0ubuntu2.2~precise1
https://launchpad.net/bugs/1175533
Added patches to add/fix Haswell pci-id's (LP: #1175533)

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debian/patches/fix-hsw-crw-ids.diff
 
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commit ae3531c3a1d72a73b25c5563b4db029f051262cb
 
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Author: Chris Wilson <chris@chris-wilson.co.uk>
 
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Date:   Fri Mar 1 23:46:07 2013 +0000
 
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    Fix Haswell CRW PCI-IDs
 
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    As we missed the PCI-ID for the CRW GT1 variant, we would not have enabled
 
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    render support for those particular Haswell machines.
 
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    Reported-by: Kenneth Graunke <kenneth@whitecape.org>
 
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diff --git a/src/intel_driver.h b/src/intel_driver.h
 
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index c98025b..0dda5b1 100644
 
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--- a/src/intel_driver.h
 
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+++ b/src/intel_driver.h
 
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@@ -219,15 +219,15 @@
 
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 #define PCI_CHIP_HASWELL_ULT_S_GT1     0x0A0A
 
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 #define PCI_CHIP_HASWELL_ULT_S_GT2     0x0A1A
 
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 #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS        0x0A2A
 
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-#define PCI_CHIP_HASWELL_CRW_D_GT1     0x0D12
 
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-#define PCI_CHIP_HASWELL_CRW_D_GT2     0x0D22
 
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-#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS        0x0D32
 
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-#define PCI_CHIP_HASWELL_CRW_M_GT1     0x0D16
 
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-#define PCI_CHIP_HASWELL_CRW_M_GT2     0x0D26
 
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-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS        0x0D36
 
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-#define PCI_CHIP_HASWELL_CRW_S_GT1     0x0D1A
 
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-#define PCI_CHIP_HASWELL_CRW_S_GT2     0x0D2A
 
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-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS        0x0D3A
 
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+#define PCI_CHIP_HASWELL_CRW_D_GT1     0x0D02
 
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+#define PCI_CHIP_HASWELL_CRW_D_GT2     0x0D12
 
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+#define PCI_CHIP_HASWELL_CRW_D_GT2_PLUS        0x0D22
 
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+#define PCI_CHIP_HASWELL_CRW_M_GT1     0x0D06
 
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+#define PCI_CHIP_HASWELL_CRW_M_GT2     0x0D16
 
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+#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS        0x0D26
 
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+#define PCI_CHIP_HASWELL_CRW_S_GT1     0x0D0A
 
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+#define PCI_CHIP_HASWELL_CRW_S_GT2     0x0D1A
 
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+#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS        0x0D2A
 
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 #define PCI_CHIP_VALLEYVIEW_PO         0x0f30
 
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 #define PCI_CHIP_VALLEYVIEW_1          0x0f31