782
782
/* Interrupt Vectors */
783
783
/* Interrupt Vector 0 is the reset vector. */
785
#define INT0_vect_num 1
784
786
#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
788
#define INT1_vect_num 2
785
789
#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
791
#define PCINT0_vect_num 3
786
792
#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */
794
#define PCINT1_vect_num 4
787
795
#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */
797
#define PCINT2_vect_num 5
788
798
#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */
800
#define WDT_vect_num 6
789
801
#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */
803
#define TIMER2_COMPA_vect_num 7
790
804
#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */
806
#define TIMER2_COMPB_vect_num 8
791
807
#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */
809
#define TIMER2_OVF_vect_num 9
792
810
#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */
812
#define TIMER1_CAPT_vect_num 10
793
813
#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */
815
#define TIMER1_COMPA_vect_num 11
794
816
#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */
818
#define TIMER1_COMPB_vect_num 12
795
819
#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
821
#define TIMER1_OVF_vect_num 13
796
822
#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */
824
#define TIMER0_COMPA_vect_num 14
797
825
#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */
827
#define TIMER0_COMPB_vect_num 15
798
828
#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */
830
#define TIMER0_OVF_vect_num 16
799
831
#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */
833
#define SPI_STC_vect_num 17
800
834
#define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */
836
#define USART_RX_vect_num 18
801
837
#define USART_RX_vect _VECTOR(18) /* USART Rx Complete */
839
#define USART_UDRE_vect_num 19
802
840
#define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */
842
#define USART_TX_vect_num 20
803
843
#define USART_TX_vect _VECTOR(20) /* USART Tx Complete */
845
#define ADC_vect_num 21
804
846
#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */
848
#define EE_READY_vect_num 22
805
849
#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */
851
#define ANALOG_COMP_vect_num 23
806
852
#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */
854
#define TWI_vect_num 24
807
855
#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */
857
#define SPM_READY_vect_num 25
808
858
#define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */
810
860
#define _VECTORS_SIZE (26 * 2)