2
Virtual Combat hardware games.
4
Driver by Jason Eckhardt, Andrew Gardner and Phil Bennett.
8
There are two known games on this hardware. Both are developed by
11
Virtual Combat (c) VR8 Inc. 1993
12
http://arcade.sonzogni.com/VRCombat/
14
Shadow Fighters (German) (c) Dutech 1993
18
There are two boards to this hardware. The upper, which contains the
19
graphics ROMs and the i860, and the lower which contains the main
20
and sound CPUs. Virtual Combat sports two upper boards which
21
output a different rasterization of the scene for each stereo eye.
23
UPPER: (Virtual Combat has an identical MIDDLE board also).
24
Intel I860 XR processor
25
MB8298-25P-SK RAMS x12 (silkscreen said 62256)
26
Analog device ADV476KN50E (silkscreen said BT476)
30
PAL palce24v10 x2 (next to the i860)
34
Motorola MC68000P12 x2
37
4 MB8298-25P-SK RAMS (in groups of 2 off by themselves)
38
1 CXK58257SP-10L at each end of the SNDCPU ROMS and the CPU ROMS (4 chips total)
39
Motorola MC6845P CRT controller
40
2x 27C010A containing sound code
41
Xx 27C040 containing sound data (VOC files)
42
Dallas DS1220Y - closest to pin 64 of CPU - read as a 2716 - (silkscreened "6116")
43
Xx 27c040 containing program code, etc.
47
NOTES : Shadow Fighters appears to have been dumped from an earlier
48
revision of the hardware. There are no IC labels, and
49
lots of factory rework has been done to the bottom board.
50
Because the board was so early for Shadow Fighters, there were
51
no IC locations silkscreened on the PCB. The locations
52
from Virtual Combat have been used.
53
The Shadow Fighters bottom board has an extra 20 mhz xtal on it.
54
The data stored in "samples" is simply a series of
55
Creative Media VOC files concatenated to eachother.
56
The sound program ("sound") is about 640 bytes long.
57
The hardware is said to run at medium resolution.
58
The SRAM module dump can likely be thrown away for both games.
59
The PAL that's dumped for Shadow Fighters looks pretty bad.
61
TODO : This is a partially working driver. Most of the memory maps for
62
all four CPUs are complete. An Intel i860XR CPU core has now
63
been incorporated into MAME.
65
-------- Notes/questions ----------
66
- Most of the memory maps and input ports are complete now.
67
For "main", the only I/O locations that seem to be left
69
0x60001C: Only read; might be a latch of some sort. It is
70
read each time M0's interrupt service routine syncs
71
with the i860's to have them update the frame buffer.
72
Might this be a HW blank bit so things look clean when
73
the i860's do their updates?
74
The two other times I see it read are just before
75
and after one of the pallette setups is done.
76
0x600018: ? No info yet.
77
0x704000: (VC only) Likely analog axis for VR headset
78
0x703000: (VC only) Likely analog axis for VR headset
80
----------------------------------------------
85
#include "cpu/m68000/m68000.h"
86
#include "cpu/i860/i860.h"
87
#include "video/tlc34076.h"
88
#include "video/mc6845.h"
89
#include "sound/dac.h"
90
#include "machine/nvram.h"
93
class vcombat_state : public driver_device
96
vcombat_state(const machine_config &mconfig, device_type type, const char *tag)
97
: driver_device(mconfig, type, tag) { }
99
UINT16* m_m68k_framebuffer[2];
100
UINT16* m_i860_framebuffer[2][2];
101
UINT16* m_framebuffer_ctrl;
102
UINT16* m_vid_0_shared_RAM;
103
UINT16* m_vid_1_shared_RAM;
108
static SCREEN_UPDATE( vcombat )
110
vcombat_state *state = screen->machine().driver_data<vcombat_state>();
112
const rgb_t *const pens = tlc34076_get_pens(screen->machine().device("tlc34076"));
113
device_t *aux = screen->machine().device("aux");
115
UINT16 *m68k_buf = state->m_m68k_framebuffer[(*state->m_framebuffer_ctrl & 0x20) ? 1 : 0];
116
UINT16 *i860_buf = state->m_i860_framebuffer[(screen == aux) ? 1 : 0][0];
118
/* TODO: It looks like the leftmost chunk of the ground should really be on the right side? */
119
/* But the i860 draws the background correctly, so it may be an original game issue. */
120
/* There's also some garbage in the upper-left corner. Might be related to this 'wraparound'. */
121
/* Or maybe it's related to the 68k's alpha? It might come from the 68k side of the house. */
123
for (y = cliprect->min_y; y <= cliprect->max_y; ++y)
126
int src_addr = 256/2 * y;
127
const UINT16 *m68k_src = &m68k_buf[src_addr];
128
const UINT16 *i860_src = &i860_buf[src_addr];
129
UINT32 *dst = BITMAP_ADDR32(bitmap, y, cliprect->min_x);
131
for (x = cliprect->min_x; x <= cliprect->max_x; x += 2)
134
UINT16 m68k_pix = *m68k_src++;
135
UINT16 i860_pix = *i860_src++;
137
/* Draw two pixels */
138
for (i = 0; i < 2; ++i)
140
/* Vcombat's screen renders 'flopped' - very likely because VR headset displays may reflect off mirrors.
141
Shadfgtr isn't flopped, so it's not a constant feature of the hardware. */
143
/* Combine the two layers */
144
if ((m68k_pix & 0xff) == 0)
145
*dst++ = pens[i860_pix & 0xff];
147
*dst++ = pens[m68k_pix & 0xff];
159
static WRITE16_HANDLER( main_video_write )
161
vcombat_state *state = space->machine().driver_data<vcombat_state>();
162
int fb = (*state->m_framebuffer_ctrl & 0x20) ? 0 : 1;
163
UINT16 old_data = state->m_m68k_framebuffer[fb][offset];
165
/* Transparency mode? */
166
if (*state->m_framebuffer_ctrl & 0x40)
171
if ((data & 0x00ff) == 0)
172
data = (data & 0xff00) | (old_data & 0x00ff);
173
if ((data & 0xff00) == 0)
174
data = (data & 0x00ff) | (old_data & 0xff00);
176
COMBINE_DATA(&state->m_m68k_framebuffer[fb][offset]);
180
COMBINE_DATA(&state->m_m68k_framebuffer[fb][offset]);
184
static READ16_HANDLER( control_1_r )
186
return (input_port_read(space->machine(), "IN0") << 8);
189
static READ16_HANDLER( control_2_r )
191
return (input_port_read(space->machine(), "IN1") << 8);
194
static READ16_HANDLER( control_3_r )
196
return (input_port_read(space->machine(), "IN2") << 8);
199
static void wiggle_i860_common(device_t *device, UINT16 data)
201
int bus_hold = (data & 0x03) == 0x03;
202
int reset = data & 0x10;
208
fprintf(stderr, "M0 asserting bus HOLD to i860 %s\n", device->tag());
209
i860_set_pin(device, DEC_PIN_BUS_HOLD, 1);
213
fprintf(stderr, "M0 clearing bus HOLD to i860 %s\n", device->tag());
214
i860_set_pin(device, DEC_PIN_BUS_HOLD, 0);
219
fprintf(stderr, "M0 asserting RESET to i860 %s\n", device->tag());
220
i860_set_pin(device, DEC_PIN_RESET, 1);
223
i860_set_pin(device, DEC_PIN_RESET, 0);
226
static WRITE16_HANDLER( wiggle_i860p0_pins_w )
228
wiggle_i860_common(space->machine().device("vid_0"), data);
231
static WRITE16_HANDLER( wiggle_i860p1_pins_w )
233
wiggle_i860_common(space->machine().device("vid_1"), data);
236
static READ16_HANDLER( main_irqiack_r )
238
//fprintf(stderr, "M0: irq iack\n");
239
device_set_input_line(space->machine().device("maincpu"), M68K_IRQ_1, CLEAR_LINE);
240
//device_set_input_line(space->machine().device("maincpu"), INPUT_LINE_RESET, CLEAR_LINE);
244
static READ16_HANDLER( sound_resetmain_r )
246
//fprintf(stderr, "M1: reset line to M0\n");
247
//device_set_input_line(space->machine().device("maincpu"), INPUT_LINE_RESET, PULSE_LINE);
251
static WRITE64_HANDLER( v0_fb_w )
253
vcombat_state *state = space->machine().driver_data<vcombat_state>();
254
/* The frame buffer seems to sit on a 32-bit data bus, while the
255
i860 uses a 64-bit data bus. Adjust accordingly. */
256
char *p = (char *)(state->m_i860_framebuffer[0][0]);
258
int o = (offset << 2);
259
if (m & 0xff000000) {
260
p[o+3] = (data >> 24) & 0xff;
262
if (m & 0x00ff0000) {
263
p[o+2] = (data >> 16) & 0xff;
265
if (m & 0x0000ff00) {
266
p[o+1] = (data >> 8) & 0xff;
268
if (m & 0x000000ff) {
269
p[o+0] = (data >> 0) & 0xff;
273
/* This is just temporary so we can see what each i860 is doing to the
275
static WRITE64_HANDLER( v1_fb_w )
277
vcombat_state *state = space->machine().driver_data<vcombat_state>();
278
/* The frame buffer seems to sit on a 32-bit data bus, while the
279
i860 uses a 64-bit data bus. Adjust accordingly. */
280
char *p = (char *)(state->m_i860_framebuffer[1][0]);
282
int o = (offset << 2);
283
if (m & 0xff000000) {
284
p[o+3] = (data >> 24) & 0xff;
286
if (m & 0x00ff0000) {
287
p[o+2] = (data >> 16) & 0xff;
289
if (m & 0x0000ff00) {
290
p[o+1] = (data >> 8) & 0xff;
292
if (m & 0x000000ff) {
293
p[o+0] = (data >> 0) & 0xff;
297
static WRITE16_HANDLER( crtc_w )
299
vcombat_state *state = space->machine().driver_data<vcombat_state>();
300
mc6845_device *crtc = space->machine().device<mc6845_device>("crtc");
305
if (state->m_crtc_select == 0)
306
crtc->address_w(*space, 0, data >> 8);
308
crtc->register_w(*space, 0, data >> 8);
310
state->m_crtc_select ^= 1;
313
static WRITE16_DEVICE_HANDLER( vcombat_dac_w )
315
INT16 newval = ((INT16)data - 0x6000) << 2;
316
dac_signed_data_16_w(device, newval + 0x8000);
319
static ADDRESS_MAP_START( main_map, AS_PROGRAM, 16 )
320
AM_RANGE(0x000000, 0x0fffff) AM_ROM
321
AM_RANGE(0x200000, 0x20ffff) AM_RAM
322
AM_RANGE(0x300000, 0x30ffff) AM_WRITE(main_video_write)
324
AM_RANGE(0x400000, 0x43ffff) AM_RAM AM_BASE_MEMBER(vcombat_state, m_vid_0_shared_RAM) AM_SHARE("share2") /* First i860 shared RAM */
325
AM_RANGE(0x440000, 0x440003) AM_RAM AM_SHARE("share6") /* M0->P0 i860 #1 com 1 */
326
AM_RANGE(0x480000, 0x480003) AM_RAM AM_SHARE("share7") /* M0<-P0 i860 #1 com 2 */
327
AM_RANGE(0x4c0000, 0x4c0003) AM_WRITE(wiggle_i860p0_pins_w) /* i860 #1 stop/start/reset */
329
AM_RANGE(0x500000, 0x53ffff) AM_RAM AM_BASE_MEMBER(vcombat_state, m_vid_1_shared_RAM) AM_SHARE("share3") /* Second i860 shared RAM */
330
AM_RANGE(0x540000, 0x540003) AM_RAM AM_SHARE("share8") /* M0->P1 i860 #2 com 1 */
331
AM_RANGE(0x580000, 0x580003) AM_RAM AM_SHARE("share9") /* M0<-P1 i860 #2 com 2 */
332
AM_RANGE(0x5c0000, 0x5c0003) AM_WRITE(wiggle_i860p1_pins_w) /* i860 #2 stop/start/reset */
334
AM_RANGE(0x600000, 0x600001) AM_READ(control_1_r) /* IN0 port */
335
AM_RANGE(0x600004, 0x600005) AM_RAM AM_SHARE("share5") /* M0<-M1 */
336
AM_RANGE(0x600008, 0x600009) AM_READ(control_2_r) /* IN1 port */
337
AM_RANGE(0x60001c, 0x60001d) AM_NOP
339
AM_RANGE(0x60000c, 0x60000d) AM_WRITE(crtc_w)
340
AM_RANGE(0x600010, 0x600011) AM_RAM AM_BASE_MEMBER(vcombat_state, m_framebuffer_ctrl)
341
AM_RANGE(0x700000, 0x7007ff) AM_RAM AM_SHARE("nvram")
342
AM_RANGE(0x701000, 0x701001) AM_READ(main_irqiack_r)
343
AM_RANGE(0x702000, 0x702001) AM_READ(control_3_r)
344
AM_RANGE(0x705000, 0x705001) AM_RAM AM_SHARE("share4") /* M1->M0 */
346
//AM_RANGE(0x703000, 0x703001) /* Headset rotation axis? */
347
//AM_RANGE(0x704000, 0x704001) /* Headset rotation axis? */
349
AM_RANGE(0x706000, 0x70601f) AM_DEVREADWRITE8("tlc34076", tlc34076_r, tlc34076_w, 0x00ff)
353
/* The first i860 - middle board */
354
static ADDRESS_MAP_START( vid_0_map, AS_PROGRAM, 64 )
355
AM_RANGE(0x00000000, 0x0001ffff) AM_RAM_WRITE(v0_fb_w) /* Shared framebuffer - half of the bits lost to 32-bit bus */
356
AM_RANGE(0x20000000, 0x20000007) AM_RAM AM_SHARE("share6") /* M0<-P0 com 1 (0x440000 in 68k-land) */
357
AM_RANGE(0x40000000, 0x401fffff) AM_ROM AM_REGION("gfx", 0)
358
AM_RANGE(0x80000000, 0x80000007) AM_RAM AM_SHARE("share7") /* M0->P0 com 2 (0x480000 in 68k-land) */
359
AM_RANGE(0xc0000000, 0xc0000fff) AM_NOP /* Dummy D$ flush page. */
360
AM_RANGE(0xfffc0000, 0xffffffff) AM_RAM AM_SHARE("share2") /* Shared RAM with main */
364
/* The second i860 - top board */
365
static ADDRESS_MAP_START( vid_1_map, AS_PROGRAM, 64 )
366
AM_RANGE(0x00000000, 0x0001ffff) AM_RAM_WRITE(v1_fb_w) /* Half of the bits lost to 32-bit bus */
367
AM_RANGE(0x20000000, 0x20000007) AM_RAM AM_SHARE("share8") /* M0->P1 com 1 (0x540000 in 68k-land) */
368
AM_RANGE(0x40000000, 0x401fffff) AM_ROM AM_REGION("gfx", 0)
369
AM_RANGE(0x80000000, 0x80000007) AM_RAM AM_SHARE("share9") /* M0<-P1 com 2 (0x580000 in 68k-land) */
370
AM_RANGE(0xc0000000, 0xc0000fff) AM_NOP /* Dummy D$ flush page. */
371
AM_RANGE(0xfffc0000, 0xffffffff) AM_RAM AM_SHARE("share3") /* Shared RAM with main */
376
static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 16 )
377
AM_RANGE(0x000000, 0x03ffff) AM_ROM
378
AM_RANGE(0x080000, 0x08ffff) AM_RAM
379
AM_RANGE(0x0c0000, 0x0c0001) AM_DEVWRITE("dac", vcombat_dac_w)
380
AM_RANGE(0x140000, 0x140001) AM_READ(sound_resetmain_r) /* Ping M0's reset line */
381
AM_RANGE(0x180000, 0x180001) AM_RAM AM_SHARE("share4") /* M1<-M0 */
382
AM_RANGE(0x1c0000, 0x1c0001) AM_RAM AM_SHARE("share5") /* M1->M0 */
383
AM_RANGE(0x200000, 0x37ffff) AM_ROM AM_REGION("samples", 0)
387
static MACHINE_RESET( vcombat )
389
vcombat_state *state = machine.driver_data<vcombat_state>();
390
i860_set_pin(machine.device("vid_0"), DEC_PIN_BUS_HOLD, 1);
391
i860_set_pin(machine.device("vid_1"), DEC_PIN_BUS_HOLD, 1);
393
state->m_crtc_select = 0;
396
static MACHINE_RESET( shadfgtr )
398
vcombat_state *state = machine.driver_data<vcombat_state>();
399
i860_set_pin(machine.device("vid_0"), DEC_PIN_BUS_HOLD, 1);
401
state->m_crtc_select = 0;
405
DIRECT_UPDATE_HANDLER( vcombat_vid_0_direct_handler )
407
vcombat_state *state = machine.driver_data<vcombat_state>();
408
if (address >= 0xfffc0000 && address <= 0xffffffff)
410
direct.explicit_configure(0xfffc0000, 0xffffffff, 0x3ffff, state->m_vid_0_shared_RAM);
416
DIRECT_UPDATE_HANDLER( vcombat_vid_1_direct_handler )
418
vcombat_state *state = machine.driver_data<vcombat_state>();
419
if (address >= 0xfffc0000 && address <= 0xffffffff)
421
direct.explicit_configure(0xfffc0000, 0xffffffff, 0x3ffff, state->m_vid_1_shared_RAM);
428
static DRIVER_INIT( vcombat )
430
vcombat_state *state = machine.driver_data<vcombat_state>();
431
UINT8 *ROM = machine.region("maincpu")->base();
433
/* The two i860s execute out of RAM */
434
address_space *space = machine.device<i860_device>("vid_0")->space(AS_PROGRAM);
435
space->set_direct_update_handler(direct_update_delegate(FUNC(vcombat_vid_0_direct_handler), &machine));
437
space = machine.device<i860_device>("vid_1")->space(AS_PROGRAM);
438
space->set_direct_update_handler(direct_update_delegate(FUNC(vcombat_vid_1_direct_handler), &machine));
440
/* Allocate the 68000 framebuffers */
441
state->m_m68k_framebuffer[0] = auto_alloc_array(machine, UINT16, 0x8000);
442
state->m_m68k_framebuffer[1] = auto_alloc_array(machine, UINT16, 0x8000);
445
state->m_i860_framebuffer[0][0] = auto_alloc_array(machine, UINT16, 0x8000);
446
state->m_i860_framebuffer[0][1] = auto_alloc_array(machine, UINT16, 0x8000);
449
state->m_i860_framebuffer[1][0] = auto_alloc_array(machine, UINT16, 0x8000);
450
state->m_i860_framebuffer[1][1] = auto_alloc_array(machine, UINT16, 0x8000);
452
/* pc==4016 : jump 4038 ... There's something strange about how it waits at 402e (interrupts all masked out)
453
I think what is happening here is that M0 snags the first time
454
it hits this point based on a counter test just above this
455
instruction. That counter gets updated just past this instruction.
456
However, the only way this can be passed is if the M0 CPU is
457
reset (the IPL=7, but irq 7 is a nop). I am almost sure that M1
458
reads a latch, which resets M0 (probably to ensure M0 and M1 are
459
both alive) and gets passed this snag. I tried to hook up a reset
460
which should work, but asserting the reset line on the m68k doesn't
461
seem to do anything. Maybe the 68k emulator doesn't respond to
462
that, or I didn't do it correctly. But I think that is what needs
463
to be done. But it isn't crucial for emulation. Shadow does not
468
static DRIVER_INIT( shadfgtr )
470
vcombat_state *state = machine.driver_data<vcombat_state>();
471
/* Allocate th 68000 frame buffers */
472
state->m_m68k_framebuffer[0] = auto_alloc_array(machine, UINT16, 0x8000);
473
state->m_m68k_framebuffer[1] = auto_alloc_array(machine, UINT16, 0x8000);
476
state->m_i860_framebuffer[0][0] = auto_alloc_array(machine, UINT16, 0x8000);
477
state->m_i860_framebuffer[0][1] = auto_alloc_array(machine, UINT16, 0x8000);
478
state->m_i860_framebuffer[1][0] = NULL;
479
state->m_i860_framebuffer[1][1] = NULL;
481
/* The i860 executes out of RAM */
482
address_space *space = machine.device<i860_device>("vid_0")->space(AS_PROGRAM);
483
space->set_direct_update_handler(direct_update_delegate(FUNC(vcombat_vid_0_direct_handler), &machine));
487
static INPUT_PORTS_START( vcombat )
489
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
490
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) /* Left button */
491
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) /* Right button */
492
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY
493
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
494
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
495
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY
496
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
499
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
500
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
501
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
502
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
503
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
504
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE )
505
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
506
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
510
static INPUT_PORTS_START( shadfgtr )
513
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2)
514
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
515
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
516
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
517
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(2)
518
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(2)
519
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY PORT_PLAYER(2)
520
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(2)
523
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
524
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
525
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
526
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
527
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START2 )
528
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE )
529
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
530
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
534
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY
535
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY
536
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY
537
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY
538
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
539
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
540
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 )
541
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 )
545
static WRITE_LINE_DEVICE_HANDLER(sound_update)
547
/* Seems reasonable */
548
device_set_input_line(device->machine().device("soundcpu"), M68K_IRQ_1, state ? ASSERT_LINE : CLEAR_LINE);
551
static const mc6845_interface mc6845_intf =
553
"screen", /* screen we are acting on */
554
16, /* number of pixels per video memory address */
555
NULL, /* before pixel update callback */
556
NULL, /* row update callback */
557
NULL, /* after pixel update callback */
558
DEVCB_NULL, /* callback for display state changes */
559
DEVCB_NULL, /* callback for cursor state changes */
560
DEVCB_LINE(sound_update), /* HSYNC callback */
561
DEVCB_NULL, /* VSYNC callback */
562
NULL /* update address callback */
566
static MACHINE_CONFIG_START( vcombat, vcombat_state )
567
MCFG_CPU_ADD("maincpu", M68000, XTAL_12MHz)
568
MCFG_CPU_PROGRAM_MAP(main_map)
569
MCFG_CPU_VBLANK_INT("screen", irq1_line_assert)
571
/* The middle board i860 */
572
MCFG_CPU_ADD("vid_0", I860, XTAL_20MHz)
573
MCFG_CPU_PROGRAM_MAP(vid_0_map)
575
/* The top board i860 */
576
MCFG_CPU_ADD("vid_1", I860, XTAL_20MHz)
577
MCFG_CPU_PROGRAM_MAP(vid_1_map)
580
MCFG_CPU_ADD("soundcpu", M68000, XTAL_12MHz)
581
MCFG_CPU_PROGRAM_MAP(sound_map)
582
MCFG_CPU_PERIODIC_INT(irq1_line_hold, 15000) /* Remove this if MC6845 is enabled */
584
MCFG_NVRAM_ADD_0FILL("nvram")
585
MCFG_MACHINE_RESET(vcombat)
587
/* Temporary hack for experimenting with timing. */
589
//MCFG_QUANTUM_TIME(attotime::from_hz(1200))
590
MCFG_QUANTUM_PERFECT_CPU("maincpu")
593
MCFG_TLC34076_ADD("tlc34076", TLC34076_6_BIT)
595
/* Disabled for now as it can't handle multiple screens */
596
// MCFG_MC6845_ADD("crtc", MC6845, 6000000 / 16, mc6845_intf)
597
MCFG_DEFAULT_LAYOUT(layout_dualhsxs)
599
MCFG_SCREEN_ADD("screen", RASTER)
600
MCFG_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
601
MCFG_SCREEN_RAW_PARAMS(XTAL_12MHz / 2, 400, 0, 256, 291, 0, 208)
602
MCFG_SCREEN_UPDATE(vcombat)
604
MCFG_SCREEN_ADD("aux", RASTER)
605
MCFG_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
606
MCFG_SCREEN_RAW_PARAMS(XTAL_12MHz / 2, 400, 0, 256, 291, 0, 208)
607
MCFG_SCREEN_UPDATE(vcombat)
609
MCFG_SPEAKER_STANDARD_MONO("mono")
611
MCFG_SOUND_ADD("dac", DAC, 0)
612
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
616
static MACHINE_CONFIG_START( shadfgtr, vcombat_state )
617
MCFG_CPU_ADD("maincpu", M68000, XTAL_12MHz)
618
MCFG_CPU_PROGRAM_MAP(main_map)
619
MCFG_CPU_VBLANK_INT("screen", irq1_line_assert)
621
/* The middle board i860 */
622
MCFG_CPU_ADD("vid_0", I860, XTAL_20MHz)
623
MCFG_CPU_PROGRAM_MAP(vid_0_map)
626
MCFG_CPU_ADD("soundcpu", M68000, XTAL_12MHz)
627
MCFG_CPU_PROGRAM_MAP(sound_map)
629
MCFG_NVRAM_ADD_0FILL("nvram")
630
MCFG_MACHINE_RESET(shadfgtr)
632
MCFG_TLC34076_ADD("tlc34076", TLC34076_6_BIT)
634
MCFG_MC6845_ADD("crtc", MC6845, XTAL_20MHz / 4 / 16, mc6845_intf)
636
MCFG_SCREEN_ADD("screen", RASTER)
637
MCFG_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
638
MCFG_SCREEN_RAW_PARAMS(XTAL_20MHz / 4, 320, 0, 256, 277, 0, 224)
639
MCFG_SCREEN_UPDATE(vcombat)
641
MCFG_SPEAKER_STANDARD_MONO("mono")
643
MCFG_SOUND_ADD("dac", DAC, 0)
644
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
649
ROM_REGION( 0x100000, "maincpu", 0 )
650
ROM_LOAD16_BYTE( "ep8v2.b49", 0x00000, 0x80000, CRC(98d5a45d) SHA1(099e314f11c93ad6e642ceaa311e2a5b6fd7193c) )
651
ROM_LOAD16_BYTE( "ep7v2.b51", 0x00001, 0x80000, CRC(06185bcb) SHA1(855b11ae7644d6c7c1c935b2f5aec484071ca870) )
653
ROM_REGION( 0x40000, "soundcpu", 0 )
654
ROM_LOAD16_BYTE( "ep1v2.b42", 0x00000, 0x20000, CRC(560b2e6c) SHA1(e35c0466a1e14beab080e3155f873e9c2a1c028b) )
655
ROM_LOAD16_BYTE( "ep6v2.b33", 0x00001, 0x20000, CRC(37928a5d) SHA1(7850be26dbd356cdeef2a0d87738de16420f6291) )
657
ROM_REGION( 0x180000, "samples", 0 )
658
ROM_LOAD16_BYTE( "ep2v2.b41", 0x000000, 0x80000, CRC(7dad3458) SHA1(deae5ebef0346250d3f9744933423253a336bb67) )
659
ROM_LOAD16_BYTE( "ep4v2.b37", 0x000001, 0x80000, CRC(b0be2e91) SHA1(66f3a9f5abeb4b95ac806e4bb165f938dca38b2d) )
660
ROM_LOAD16_BYTE( "ep3v2.b40", 0x100000, 0x40000, CRC(8c491526) SHA1(95c6bcbe0adcfffb12fd2b86c9f4ca26aa188bbf) )
661
ROM_LOAD16_BYTE( "ep5v2.b36", 0x100001, 0x40000, CRC(7592b2eb) SHA1(92a540726306d7adbf207fe86a4c4fa66958f90b) )
663
ROM_REGION( 0x800, "user1", 0 ) /* The SRAM module */
664
ROM_LOAD( "ds1220y.b53", 0x000, 0x800, CRC(b21cfe5f) SHA1(898ace3cd0913ea4b0dc84320219777773ef856f) )
666
/* These roms are identical on both of the upper boards */
667
ROM_REGION( 0x200000, "gfx", 0 )
668
ROM_LOAD64_WORD( "9.u55", 0x000000, 0x80000, CRC(a276e18b) SHA1(6d60e519196a4858b82241504592413df498e12f) )
669
ROM_LOAD64_WORD( "10.u57", 0x000002, 0x80000, CRC(8921f20e) SHA1(6e9ca2eaad3e1108ba0e1d7792fd5d0305bec201) )
670
ROM_LOAD64_WORD( "11.u54", 0x000004, 0x80000, CRC(a83094ce) SHA1(c3512375fecdb5e7eb02a4aa140ae4efe0233cb8) )
671
ROM_LOAD64_WORD( "12.u56", 0x000006, 0x80000, CRC(0cdffd4f) SHA1(65ace78711b3ef6e0ff9a7ad7343b5558e652f6c) )
673
ROM_REGION( 0x400, "plds", 0 )
674
ROM_LOAD( "pal1_w2.u51", 0x000, 0x1f1, CRC(af497420) SHA1(03aa82189d91ae194dd5a6e7b9dbdb7cd473ddb6) )
675
ROM_LOAD( "pal2_w2.u52", 0x200, 0x1f1, CRC(4a6df05d) SHA1(236b951e5daf927c050d0f35558c171a020156ab) )
678
ROM_START( shadfgtr )
679
ROM_REGION( 0x100000, "maincpu", 0 )
680
ROM_LOAD16_BYTE( "shadfgtr.b49", 0x00000, 0x80000, CRC(2d9d31a1) SHA1(45854915bcb9db2e4076a7f26a0a349077cd10bc) )
681
ROM_LOAD16_BYTE( "shadfgtr.b51", 0x00001, 0x80000, CRC(03d0f075) SHA1(06013a4363305a23d7e8ba8fe2fa961cd540391d) )
683
ROM_REGION( 0x40000, "soundcpu", 0 )
684
ROM_LOAD16_BYTE( "shadfgtr.b42", 0x00000, 0x20000, CRC(f8605dcd) SHA1(1b29f47856ccc757bc96674682ae48f87e6b0e54) )
685
ROM_LOAD16_BYTE( "shadfgtr.b33", 0x00001, 0x20000, CRC(291d59ac) SHA1(cc4904c2ac8ef6a12033c10893246a438ac44014) )
687
ROM_REGION( 0x180000, "samples", 0 )
688
ROM_LOAD16_BYTE( "shadfgtr.b41", 0x00000, 0x80000, CRC(9e4b4df3) SHA1(8101197275e9f728acdeef85737eecbdec132b27) )
689
ROM_LOAD16_BYTE( "shadfgtr.b37", 0x00001, 0x80000, CRC(98446ba2) SHA1(1c8cc0d9c5de54d9e53699a5ab281579d15edc96) )
691
ROM_REGION( 0x800, "user1", 0 ) /* The SRAM module */
692
ROM_LOAD( "shadfgtr.b53", 0x000, 0x800, CRC(e766a3ab) SHA1(e7696ec08d5c86f64d768480f43edbd19ded162d) )
694
ROM_REGION( 0x200000, "gfx", 0 )
695
ROM_LOAD64_WORD( "shadfgtr.u55", 0x000000, 0x80000, CRC(e807631d) SHA1(9027ff7dc60b808434dac292c08f0630d3d52186) )
696
ROM_LOAD64_WORD( "shadfgtr.u57", 0x000002, 0x80000, CRC(60d701d7) SHA1(936473b5e3b2e9e9e3b50cf977fc5a670a097850) )
697
ROM_LOAD64_WORD( "shadfgtr.u54", 0x000004, 0x80000, CRC(c45d68d6) SHA1(a133e4f13d3af18bccf0d060a659d64ac699b159) )
698
ROM_LOAD64_WORD( "shadfgtr.u56", 0x000006, 0x80000, CRC(fb76db5a) SHA1(fa546f465df113c13037abed1162bfa6f9b1dc9b) )
700
ROM_REGION( 0x200, "plds", 0 )
701
ROM_LOAD( "shadfgtr.u51", 0x000, 0x1f1, CRC(bab58337) SHA1(c4a79c8e53aeadb7f64d49d214b607b5b36f144e) )
702
/* The second upper-board PAL couldn't be read */
705
/* YEAR NAME PARENT MACHINE INPUT INIT MONITOR COMPANY FULLNAME FLAGS */
706
GAME( 1993, vcombat, 0, vcombat, vcombat, vcombat, ORIENTATION_FLIP_X, "VR8 Inc.", "Virtual Combat", GAME_NOT_WORKING )
707
GAME( 1993, shadfgtr, 0, shadfgtr, shadfgtr, shadfgtr, ROT0, "Dutech Inc.", "Shadow Fighters", GAME_NOT_WORKING )