94
95
target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
97
target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
96
99
int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
97
100
CPUWriteMemoryFunc * const *mem_write, void *opaque);
99
/* OMAP interrupt controller */
100
struct omap_intr_handler_s;
101
struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
102
unsigned long size, unsigned char nbanks, qemu_irq **pins,
103
qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
104
struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
105
int size, int nbanks, qemu_irq **pins,
106
qemu_irq parent_irq, qemu_irq parent_fiq,
107
omap_clk fclk, omap_clk iclk);
108
void omap_inth_reset(struct omap_intr_handler_s *s);
109
qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n);
111
102
/* OMAP2 SDRAM controller */
112
103
struct omap_sdrc_s;
113
104
struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
116
107
/* OMAP2 general purpose memory controller */
117
108
struct omap_gpmc_s;
118
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
109
struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
110
target_phys_addr_t base,
111
qemu_irq irq, qemu_irq drq);
119
112
void omap_gpmc_reset(struct omap_gpmc_s *s);
120
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
121
void (*base_upd)(void *opaque, target_phys_addr_t new),
122
void (*unmap)(void *opaque), void *opaque);
113
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
114
void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand);
125
117
* Common IRQ numbers for level 1 interrupt handler
674
666
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
676
668
struct omap_mpuio_s;
677
struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
669
struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *system_memory,
670
target_phys_addr_t base,
678
671
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
680
673
qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
681
674
void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
682
675
void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
684
/* omap1 gpio module interface */
686
struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
687
qemu_irq irq, omap_clk clk);
688
void omap_gpio_reset(struct omap_gpio_s *s);
689
qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
690
void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler);
692
/* omap2 gpio interface */
694
struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
695
qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules);
696
void omap_gpif_reset(struct omap_gpif_s *s);
697
qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start);
698
void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler);
700
677
struct uWireSlave {
701
678
uint16_t (*receive)(void *opaque);
702
679
void (*send)(void *opaque, uint16_t data);
705
682
struct omap_uwire_s;
706
struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
707
qemu_irq *irq, qemu_irq dma, omap_clk clk);
708
683
void omap_uwire_attach(struct omap_uwire_s *s,
709
684
uWireSlave *slave, int chipselect);
744
719
struct omap_mcbsp_s;
745
struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
746
qemu_irq *irq, qemu_irq *dma, omap_clk clk);
747
720
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
749
722
void omap_tap_init(struct omap_target_agent_s *ta,
753
726
struct omap_lcd_panel_s;
754
727
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
755
728
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
756
struct omap_dma_lcd_channel_s *dma,
757
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
729
struct omap_dma_lcd_channel_s *dma, omap_clk clk);
760
732
struct rfbi_chip_s {
801
773
# define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
802
774
# define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
803
775
# define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
776
# define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630)
805
778
# define cpu_is_omap15xx(cpu) \
806
779
(cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
812
785
# define cpu_class_omap1(cpu) \
813
786
(cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
814
787
# define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
815
# define cpu_class_omap3(cpu) cpu_is_omap3430(cpu)
788
# define cpu_class_omap3(cpu) \
789
(cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu))
817
791
struct omap_mpu_state_s {
818
792
enum omap_mpu_model {
812
MemoryRegion ulpd_pm_iomem;
813
MemoryRegion pin_cfg_iomem;
814
MemoryRegion id_iomem;
815
MemoryRegion id_iomem_e18;
816
MemoryRegion id_iomem_ed4;
817
MemoryRegion id_iomem_e20;
818
MemoryRegion mpui_iomem;
819
MemoryRegion tcmi_iomem;
820
MemoryRegion clkm_iomem;
821
MemoryRegion clkdsp_iomem;
822
MemoryRegion pwl_iomem;
823
MemoryRegion pwt_iomem;
824
MemoryRegion mpui_io_iomem;
825
MemoryRegion imif_ram;
826
MemoryRegion emiff_ram;
838
828
struct omap_dma_port_if_s {
839
829
uint32_t (*read[3])(struct omap_mpu_state_s *s,
840
830
target_phys_addr_t offset);
850
840
/* MPUI-TIPB peripherals */
851
841
struct omap_uart_s *uart[3];
853
struct omap_gpio_s *gpio;
855
845
struct omap_mcbsp_s *mcbsp1;
856
846
struct omap_mcbsp_s *mcbsp3;
961
struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
950
struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
951
unsigned long sdram_size,
962
952
const char *core);
1123
1113
CPUWriteMemoryFunc * const *mem_write,
1126
struct io_fn *s = qemu_malloc(sizeof(struct io_fn));
1116
struct io_fn *s = g_malloc(sizeof(struct io_fn));
1128
1118
s->mem_read = mem_read;
1129
1119
s->mem_write = mem_write;