← Back to branch summary

~ubuntu-branches/ubuntu/raring/qemu-kvm/raring

« back to all changes in this revision

Viewing changes to hw/pc.h

  • Committer: Serge Hallyn
  • Date: 2011-12-06 22:40:24 UTC
  • mfrom: (1.2.8)
  • Revision ID: serge.hallyn@ubuntu.com-20111206224024-x6bw4wnn65pgf55v
Tags: 1.0+noroms-0ubuntu1
* New upstream release
* Remaining changes from upstream:
  - removed all binary roms and tests/pi_10.com
* debian/qemu-kvm.links: qemu is now called qemu-system-i386, don't symlink
  it
* remove patches applied upstream:
  - debian/patches/vpc.patch
  - debian/patches/e1000-Dont-set-the-Capabilities-List-bit.patch
  - debian/patches/CVE-2011-4111.patch
* replace default-to-tcg.patch with simpler fallback-to-tcg.patch
* keep remaining patches:
  - larger_default_ram_size.patch
  - CVE-2011-2212-virtqueue-indirect-overflow.patch
  - qemuifup-fix-paths.patch
  - dont-try-to-hotplug-cpu.patch

Show diffs side-by-side

added added

removed removed

Lines of Context:
hw/pc.h
2
2
#define HW_PC_H
3
3
 
4
4
#include "qemu-common.h"
 
5
#include "memory.h"
5
6
#include "ioport.h"
6
7
#include "isa.h"
7
8
#include "fdc.h"
8
9
#include "net.h"
 
10
#include "memory.h"
 
11
#include "ioapic.h"
9
12
 
10
13
/* PC-style peripherals (also used by other machines).  */
11
14
 
13
16
 
14
17
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
15
18
                         CharDriverState *chr);
16
 
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
17
 
                             qemu_irq irq, int baudbase,
18
 
                             CharDriverState *chr, int ioregister,
19
 
                             int be);
 
19
SerialState *serial_mm_init(MemoryRegion *address_space,
 
20
                            target_phys_addr_t base, int it_shift,
 
21
                            qemu_irq irq, int baudbase,
 
22
                            CharDriverState *chr, enum device_endian);
20
23
static inline bool serial_isa_init(int index, CharDriverState *chr)
21
24
{
22
25
    ISADevice *dev;
57
60
 
58
61
/* i8259.c */
59
62
 
60
 
typedef struct PicState2 PicState2;
61
 
extern PicState2 *isa_pic;
62
 
void pic_set_irq(int irq, int level);
63
 
void pic_set_irq_new(void *opaque, int irq, int level);
 
63
typedef struct PicState PicState;
 
64
extern PicState *isa_pic;
64
65
qemu_irq *i8259_init(qemu_irq parent_irq);
65
66
qemu_irq *kvm_i8259_init(qemu_irq parent_irq);
66
 
int pic_read_irq(PicState2 *s);
67
 
void pic_update_irq(PicState2 *s);
68
 
uint32_t pic_intack_read(PicState2 *s);
 
67
int pic_read_irq(PicState *s);
 
68
int pic_get_output(PicState *s);
69
69
void pic_info(Monitor *mon);
70
70
void irq_info(Monitor *mon);
71
71
 
72
 
/* ISA */
73
 
#define IOAPIC_NUM_PINS 0x18
74
 
 
75
 
typedef struct isa_irq_state {
76
 
    qemu_irq *i8259;
77
 
    qemu_irq ioapic[IOAPIC_NUM_PINS];
78
 
} IsaIrqState;
79
 
 
80
 
void isa_irq_handler(void *opaque, int n, int level);
 
72
/* Global System Interrupts */
 
73
 
 
74
#define GSI_NUM_PINS IOAPIC_NUM_PINS
 
75
 
 
76
typedef struct GSIState {
 
77
    qemu_irq i8259_irq[ISA_NUM_IRQS];
 
78
    qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
 
79
} GSIState;
 
80
 
 
81
void gsi_handler(void *opaque, int n, int level);
81
82
 
82
83
/* i8254.c */
83
84
 
117
118
 
118
119
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
119
120
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
120
 
                   target_phys_addr_t base, ram_addr_t size,
 
121
                   MemoryRegion *region, ram_addr_t size,
121
122
                   target_phys_addr_t mask);
122
123
void i8042_isa_mouse_fake_event(void *opaque);
123
124
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
130
131
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
131
132
 
132
133
void pc_cpus_init(const char *cpu_model);
133
 
void pc_memory_init(const char *kernel_filename,
 
134
void pc_memory_init(MemoryRegion *system_memory,
 
135
                    const char *kernel_filename,
134
136
                    const char *kernel_cmdline,
135
137
                    const char *initrd_filename,
136
138
                    ram_addr_t below_4g_mem_size,
137
 
                    ram_addr_t above_4g_mem_size);
 
139
                    ram_addr_t above_4g_mem_size,
 
140
                    MemoryRegion *rom_memory,
 
141
                    MemoryRegion **ram_memory);
138
142
qemu_irq *pc_allocate_cpu_irq(void);
139
143
void pc_vga_init(PCIBus *pci_bus);
140
 
void pc_basic_device_init(qemu_irq *isa_irq,
 
144
void pc_basic_device_init(qemu_irq *gsi,
141
145
                          ISADevice **rtc_state,
 
146
                          ISADevice **floppy,
142
147
                          bool no_vmport);
143
148
void pc_init_ne2k_isa(NICInfo *nd);
144
149
void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
145
150
                  const char *boot_device,
146
 
                  BusState *ide0, BusState *ide1,
 
151
                  ISADevice *floppy, BusState *ide0, BusState *ide1,
147
152
                  ISADevice *s);
148
153
void pc_pci_device_init(PCIBus *pci_bus);
149
154
 
179
184
struct PCII440FXState;
180
185
typedef struct PCII440FXState PCII440FXState;
181
186
 
182
 
PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, qemu_irq *pic, ram_addr_t ram_size);
183
 
void i440fx_init_memory_mappings(PCII440FXState *d);
 
187
PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
 
188
                    qemu_irq *pic,
 
189
                    MemoryRegion *address_space_mem,
 
190
                    MemoryRegion *address_space_io,
 
191
                    ram_addr_t ram_size,
 
192
                    target_phys_addr_t pci_hole_start,
 
193
                    target_phys_addr_t pci_hole_size,
 
194
                    target_phys_addr_t pci_hole64_start,
 
195
                    target_phys_addr_t pci_hole64_size,
 
196
                    MemoryRegion *pci_memory,
 
197
                    MemoryRegion *ram_memory);
184
198
 
185
199
/* piix4.c */
186
200
extern PCIDevice *piix4_dev;
213
227
 
214
228
int pci_vga_init(PCIBus *bus);
215
229
int isa_vga_mm_init(target_phys_addr_t vram_base,
216
 
                    target_phys_addr_t ctrl_base, int it_shift);
 
230
                    target_phys_addr_t ctrl_base, int it_shift,
 
231
                    MemoryRegion *address_space);
217
232
 
218
233
/* cirrus_vga.c */
219
234
void pci_cirrus_vga_init(PCIBus *bus);
220
 
void isa_cirrus_vga_init(void);
 
235
void isa_cirrus_vga_init(MemoryRegion *address_space);
221
236
 
222
237
/* ne2000.c */
223
238
static inline bool isa_ne2000_init(int base, int irq, NICInfo *nd)
237
252
    return true;
238
253
}
239
254
 
240
 
/* extboot.c */
241
 
 
242
 
void extboot_init(BlockDriverState *bs);
243
 
 
244
255
/* e820 types */
245
256
#define E820_RAM        1
246
257
#define E820_RESERVED   2