70
71
uint8_t cfi_table[0x52];
73
/* The device replicates the flash memory across its memory space. Emulate
74
* that by having a container (.mem) filled with an array of aliases
75
* (.mem_mappings) pointing to the flash memory (.orig_mem).
78
MemoryRegion *mem_mappings; /* array; one per mapping */
79
MemoryRegion orig_mem;
75
81
int read_counter; /* used for lazy switch-back to rom mode */
86
* Set up replicated mappings of the same region.
88
static void pflash_setup_mappings(pflash_t *pfl)
91
target_phys_addr_t size = memory_region_size(&pfl->orig_mem);
93
memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
94
pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
95
for (i = 0; i < pfl->mappings; ++i) {
96
memory_region_init_alias(&pfl->mem_mappings[i], "pflash-alias",
97
&pfl->orig_mem, 0, size);
98
memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
79
102
static void pflash_register_memory(pflash_t *pfl, int rom_mode)
81
unsigned long phys_offset = pfl->fl_mem;
85
phys_offset |= pfl->off | IO_MEM_ROMD;
86
pfl->rom_mode = rom_mode;
88
for (i = 0; i < pfl->mappings; i++)
89
cpu_register_physical_memory(pfl->base + i * pfl->chip_len,
90
pfl->chip_len, phys_offset);
104
memory_region_rom_device_set_readable(&pfl->orig_mem, rom_mode);
93
107
static void pflash_timer (void *opaque)
538
552
pflash_write(pfl, addr, value, 4, 0);
541
static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
547
static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
553
static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
559
static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
555
static const MemoryRegionOps pflash_cfi02_ops_be = {
557
.read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
558
.write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
560
.endianness = DEVICE_NATIVE_ENDIAN,
563
static const MemoryRegionOps pflash_cfi02_ops_le = {
565
.read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
566
.write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
568
.endianness = DEVICE_NATIVE_ENDIAN,
565
571
/* Count trailing zeroes of a 32 bits quantity */
601
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
607
pflash_t *pflash_cfi02_register(target_phys_addr_t base,
608
DeviceState *qdev, const char *name,
609
target_phys_addr_t size,
602
610
BlockDriverState *bs, uint32_t sector_len,
603
611
int nb_blocs, int nb_mappings, int width,
604
612
uint16_t id0, uint16_t id1,
617
625
total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
620
pfl = qemu_mallocz(sizeof(pflash_t));
621
/* FIXME: Allocate ram ourselves. */
622
pfl->storage = qemu_get_ram_ptr(off);
624
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
626
pfl, DEVICE_NATIVE_ENDIAN);
628
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
630
pfl, DEVICE_NATIVE_ENDIAN);
628
pfl = g_malloc0(sizeof(pflash_t));
629
memory_region_init_rom_device(
630
&pfl->orig_mem, be ? &pflash_cfi02_ops_be : &pflash_cfi02_ops_le, pfl,
632
pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
633
633
pfl->base = base;
634
634
pfl->chip_len = chip_len;
635
635
pfl->mappings = nb_mappings;
636
pflash_register_memory(pfl, 1);
639
638
/* read the initial flash content */
640
639
ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9);
642
cpu_unregister_io_memory(pfl->fl_mem);
644
bdrv_attach_dev_nofail(pfl->bs, pfl);
646
pflash_setup_mappings(pfl);
648
memory_region_add_subregion(get_system_memory(), pfl->base, &pfl->mem);
647
649
#if 0 /* XXX: there should be a bit to set up read-only,
648
650
* the same way the hardware does (with WP pin).