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- Committer: Bazaar Package Importer
- Author(s): Vince Mulhollon
- Date: 2007-04-13 20:16:15 UTC
- mfrom: (1.1.7 upstream) (2.1.3 lenny)
- Revision ID: james.westby@ubuntu.com-20070413201615-jiar46bgkrs0dw2h
Tags: 3.7.0-1
* New upstream released 03-Feb-2007
* i7094 added which emulates the IBM 7090/7094
* Upstream has converted almost entirely to pdf format for docs
* All manpages updated
* All docs are registered with the doc-base system
* i7094 added which emulates the IBM 7090/7094
* Upstream has converted almost entirely to pdf format for docs
* All manpages updated
* All docs are registered with the doc-base system
- files added:
- 0readme_37.txt
- DOCS
- files removed:
- 0readme_36.txt
- files modified:
- AltairZ80/altairz80_cpu.c
added
removed
AltairZ80/altairz80_cpu.c
1
1
/* altairz80_cpu.c: MITS Altair CPU (8080 and Z80)
2
2
3
Copyright (c) 2002-2006, Peter Schorn
3
Copyright (c) 2002-2007, Peter Schorn
4
4
5
5
Permission is hereby granted, free of charge, to any person obtaining a
6
6
copy of this software and associated documentation files (the "Software"),
29
29
30
30
#include "altairz80_defs.h"
31
31
32
#if !defined (_WIN32)
32
#if defined (_WIN32)
33
#include <windows.h>
34
#else
33
35
#include <unistd.h>
34
36
#endif
35
37
54
56
#define SETFLAG(f,c) AF = (c) ? AF | FLAG_ ## f : AF & ~FLAG_ ## f
55
57
#define TSTFLAG(f) ((AF & FLAG_ ## f) != 0)
56
58
57
#define ldig(x) ((x) & 0xf)
58
#define hdig(x) (((x) >> 4) & 0xf)
59
#define lreg(x) ((x) & 0xff)
60
#define hreg(x) (((x) >> 8) & 0xff)
61
62
#define Setlreg(x, v) x = (((x) & 0xff00) | ((v) & 0xff))
63
#define Sethreg(x, v) x = (((x) & 0xff) | (((v) & 0xff) << 8))
64
65
#define parity(x) parityTable[(x) & 0xff]
66
/* SetPV and SetPV2 are used to provide correct parity flag semantics for the 8080 in cases
59
#define LOW_DIGIT(x) ((x) & 0xf)
60
#define HIGH_DIGIT(x) (((x) >> 4) & 0xf)
61
#define LOW_REGISTER(x) ((x) & 0xff)
62
#define HIGH_REGISTER(x) (((x) >> 8) & 0xff)
63
64
#define SET_LOW_REGISTER(x, v) x = (((x) & 0xff00) | ((v) & 0xff))
65
#define SET_HIGH_REGISTER(x, v) x = (((x) & 0xff) | (((v) & 0xff) << 8))
66
67
#define PARITY(x) parityTable[(x) & 0xff]
68
/* SET_PV and SET_PV2 are used to provide correct PARITY flag semantics for the 8080 in cases
67
69
where the Z80 uses the overflow flag
68
70
*/
69
#define SetPVS(s) ((cpu_unit.flags & UNIT_CHIP) ? (((cbits >> 6) ^ (cbits >> 5)) & 4) : (parity(s)))
70
#define SetPV (SetPVS(sum))
71
#define SetPV2(x) ((cpu_unit.flags & UNIT_CHIP) ? (((temp == (x)) << 2)) : (parity(temp)))
71
#define SET_PVS(s) ((cpu_unit.flags & UNIT_CHIP) ? (((cbits >> 6) ^ (cbits >> 5)) & 4) : (PARITY(s)))
72
#define SET_PV (SET_PVS(sum))
73
#define SET_PV2(x) ((cpu_unit.flags & UNIT_CHIP) ? (((temp == (x)) << 2)) : (PARITY(temp)))
72
74
73
/* checkCPU8080 must be invoked whenever a Z80 only instruction is executed
75
/* CHECK_CPU_8080 must be invoked whenever a Z80 only instruction is executed
74
76
In case a Z80 instruction is executed on an 8080 the following two cases exist:
75
77
1) Trapping is enabled: execution stops
76
78
2) Trapping is not enabled: decoding continues with the next byte
77
79
*/
78
#define checkCPU8080 \
80
#define CHECK_CPU_8080 \
79
81
if ((cpu_unit.flags & UNIT_CHIP) == 0) { \
80
82
if (cpu_unit.flags & UNIT_OPSTOP) { \
81
83
reason = STOP_OPCODE; \
87
89
} \
88
90
}
89
91
90
/* checkCPUZ80 must be invoked whenever a non Z80 instruction is executed */
91
#define checkCPUZ80 \
92
/* CHECK_CPU_Z80 must be invoked whenever a non Z80 instruction is executed */
93
#define CHECK_CPU_Z80 \
92
94
if (cpu_unit.flags & UNIT_OPSTOP) { \
93
95
reason = STOP_OPCODE; \
94
96
goto end_decode; \
95
97
}
96
98
97
99
#define POP(x) { \
98
register uint32 y = RAM_pp(SP); \
99
x = y + (RAM_pp(SP) << 8); \
100
register uint32 y = RAM_PP(SP); \
101
x = y + (RAM_PP(SP) << 8); \
100
102
}
101
103
102
104
#define JPC(cond) { \
103
105
tStates += 10; \
104
106
if (cond) { \
105
107
PCQ_ENTRY(PC - 1); \
106
PC = GetWORD(PC); \
108
PC = GET_WORD(PC); \
107
109
} \
108
110
else { \
109
111
PC += 2; \
112
114
113
115
#define CALLC(cond) { \
114
116
if (cond) { \
115
register uint32 adrr = GetWORD(PC); \
116
CheckBreakWord(SP - 2); \
117
register uint32 adrr = GET_WORD(PC); \
118
CHECK_BREAK_WORD(SP - 2); \
117
119
PUSH(PC + 2); \
118
120
PCQ_ENTRY(PC - 1); \
119
121
PC = adrr; \
134
136
extern int32 dsk10 (const int32 port, const int32 io, const int32 data);
135
137
extern int32 dsk11 (const int32 port, const int32 io, const int32 data);
136
138
extern int32 dsk12 (const int32 port, const int32 io, const int32 data);
139
extern int32 netStatus (const int32 port, const int32 io, const int32 data);
140
extern int32 netData (const int32 port, const int32 io, const int32 data);
137
141
extern int32 nulldev (const int32 port, const int32 io, const int32 data);
138
142
extern int32 hdsk_io (const int32 port, const int32 io, const int32 data);
139
143
extern int32 simh_dev (const int32 port, const int32 io, const int32 data);
174
178
static void reset_memory(void);
175
179
static uint32 in(const uint32 Port);
176
180
static void out(const uint32 Port, const uint32 Value);
177
static void PutBYTE(register uint32 Addr, register uint32 Value);
178
static void PutWORD(register uint32 a, register uint32 v);
181
static void PutBYTE(register uint32 Addr, const register uint32 Value);
182
static void PutWORD(register uint32 Addr, const register uint32 Value);
179
183
static t_bool sim_brk_lookup (const t_addr bloc, const int32 btyp);
180
184
static void resetCell(const int32 address, const int32 bank);
181
185
208
212
int32 SR = 0; /* switch register */
209
213
static int32 bankSelect = 0; /* determines selected memory bank */
210
214
static uint32 common = 0xc000; /* addresses >= 'common' are in common memory */
211
static uint32 ROMLow = defaultROMLow; /* lowest address of ROM */
212
static uint32 ROMHigh = defaultROMHigh; /* highest address of ROM */
215
static uint32 ROMLow = DEFAULT_ROM_LOW; /* lowest address of ROM */
216
static uint32 ROMHigh = DEFAULT_ROM_HIGH; /* highest address of ROM */
213
217
static uint32 previousCapacity = 0; /* safe for previous memory capacity */
214
218
static uint32 clockFrequency = 0; /* in kHz, 0 means as fast as possible */
215
219
static uint32 sliceLength = 10; /* length of time-slice for CPU speed */
315
319
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1C */
316
320
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 20 */
317
321
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 24 */
318
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 28 */
322
{&netStatus},{&netData},{&netStatus},{&netData}, /* 28 */
319
323
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2C */
320
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 30 */
324
{&nulldev}, {&nulldev}, {&netStatus},{&netData}, /* 30 */
321
325
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 34 */
322
326
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 38 */
323
327
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3C */
1334
1338
/*
1335
1339
uint32 temp, v;
1336
1340
for (temp = 0; temp < 256; temp++) {
1337
v = (temp & 0xa8) | (((temp & 0xff) == 0) << 6) | parity(temp);
1341
v = (temp & 0xa8) | (((temp & 0xff) == 0) << 6) | PARITY(temp);
1338
1342
printf("%3d,", v);
1339
1343
if ( ((temp+1) & 0xf) == 0) {
1340
1344
printf("\n");
1466
1470
static void warnUnsuccessfulWriteAttempt(const uint32 Addr) {
1467
1471
if (cpu_unit.flags & UNIT_WARNROM) {
1468
1472
if (addressIsInROM(Addr)) {
1469
message2("Attempt to write to ROM " AddressFormat ".", Addr);
1473
MESSAGE_2("Attempt to write to ROM " ADDRESS_FORMAT ".", Addr);
1470
1474
}
1471
1475
else {
1472
message2("Attempt to write to non existing memory " AddressFormat ".", Addr);
1476
MESSAGE_2("Attempt to write to non existing memory " ADDRESS_FORMAT ".", Addr);
1473
1477
}
1474
1478
}
1475
1479
}
1476
1480
1477
1481
static uint8 warnUnsuccessfulReadAttempt(const uint32 Addr) {
1478
1482
if (cpu_unit.flags & UNIT_WARNROM) {
1479
message2("Attempt to read from non existing memory " AddressFormat ".", Addr);
1483
MESSAGE_2("Attempt to read from non existing memory " ADDRESS_FORMAT ".", Addr);
1480
1484
}
1481
1485
return 0xff;
1482
1486
}
1486
1490
uint32 addr = Addr & ADDRMASK; /* registers are NOT guaranteed to be always 16-bit values */
1487
1491
return (cpu_unit.flags & UNIT_ROM) && ( /* must have ROM enabled */
1488
1492
/* in banked case we have standard Altair ROM */
1489
((cpu_unit.flags & UNIT_BANKED) && (defaultROMLow <= addr)) ||
1493
((cpu_unit.flags & UNIT_BANKED) && (DEFAULT_ROM_LOW <= addr)) ||
1490
1494
/* in non-banked case we check the bounds of the ROM */
1491
1495
(((cpu_unit.flags & UNIT_BANKED) == 0) && (ROMLow <= addr) && (addr <= ROMHigh)));
1492
1496
}
1505
1509
if (Addr < common) {
1506
1510
M[Addr][bankSelect] = Value;
1507
1511
}
1508
else if ((Addr < defaultROMLow) || ((cpu_unit.flags & UNIT_ROM) == 0)) {
1512
else if ((Addr < DEFAULT_ROM_LOW) || ((cpu_unit.flags & UNIT_ROM) == 0)) {
1509
1513
M[Addr][0] = Value;
1510
1514
}
1511
1515
else {
1528
1532
if (Addr < common) {
1529
1533
M[Addr][bankSelect] = Value;
1530
1534
}
1531
else if ((Addr < defaultROMLow) || ((cpu_unit.flags & UNIT_ROM) == 0)) {
1535
else if ((Addr < DEFAULT_ROM_LOW) || ((cpu_unit.flags & UNIT_ROM) == 0)) {
1532
1536
M[Addr][0] = Value;
1533
1537
}
1534
1538
else {
1538
1542
if (Addr < common) {
1539
1543
M[Addr][bankSelect] = Value >> 8;
1540
1544
}
1541
else if ((Addr < defaultROMLow) || ((cpu_unit.flags & UNIT_ROM) == 0)) {
1545
else if ((Addr < DEFAULT_ROM_LOW) || ((cpu_unit.flags & UNIT_ROM) == 0)) {
1542
1546
M[Addr][0] = Value >> 8;
1543
1547
}
1544
1548
else {
1577
1581
}
1578
1582
1579
1583
int32 install_bootrom(void) {
1580
extern int32 bootrom[bootrom_size];
1584
extern int32 bootrom[BOOTROM_SIZE];
1581
1585
int32 i, cnt = 0;
1582
for (i = 0; i < bootrom_size; i++) {
1583
if (M[i + defaultROMLow][0] != (bootrom[i] & 0xff)) {
1586
for (i = 0; i < BOOTROM_SIZE; i++) {
1587
if (M[i + DEFAULT_ROM_LOW][0] != (bootrom[i] & 0xff)) {
1584
1588
cnt++;
1585
M[i + defaultROMLow][0] = bootrom[i] & 0xff;
1589
M[i + DEFAULT_ROM_LOW][0] = bootrom[i] & 0xff;
1586
1590
}
1587
1591
}
1588
1592
return cnt;
1618
1622
return common;
1619
1623
}
1620
1624
1621
#define Reduce(Addr) ((Addr) & ADDRMASK)
1622
1623
#define GetBYTE(Addr) \
1624
((cpu_unit.flags & UNIT_BANKED) ? \
1625
(Reduce(Addr) < common ? \
1626
M[Reduce(Addr)][bankSelect] \
1627
: \
1628
M[Reduce(Addr)][0]) \
1629
: \
1630
(((Reduce(Addr) < MEMSIZE) || ( (cpu_unit.flags & UNIT_ROM) && (ROMLow <= Reduce(Addr)) && (Reduce(Addr) <= ROMHigh) )) ? \
1631
M[Reduce(Addr)][0] \
1632
: \
1633
warnUnsuccessfulReadAttempt(Reduce(Addr))))
1634
1635
#define RAM_pp(Addr) \
1636
((cpu_unit.flags & UNIT_BANKED) ? \
1637
(Reduce(Addr) < common ? \
1638
M[Reduce(Addr++)][bankSelect] \
1639
: \
1640
M[Reduce(Addr++)][0]) \
1641
: \
1642
(((Reduce(Addr) < MEMSIZE) || ( (cpu_unit.flags & UNIT_ROM) && (ROMLow <= Reduce(Addr)) && (Reduce(Addr) <= ROMHigh) )) ? \
1643
M[Reduce(Addr++)][0] \
1644
: \
1645
warnUnsuccessfulReadAttempt(Reduce(Addr++))))
1646
1647
#define RAM_mm(Addr) \
1648
((cpu_unit.flags & UNIT_BANKED) ? \
1649
(Reduce(Addr) < common ? \
1650
M[Reduce(Addr--)][bankSelect] \
1651
: \
1652
M[Reduce(Addr--)][0]) \
1653
: \
1654
(((Reduce(Addr) < MEMSIZE) || ( (cpu_unit.flags & UNIT_ROM) && (ROMLow <= Reduce(Addr)) && (Reduce(Addr) <= ROMHigh) )) ? \
1655
M[Reduce(Addr--)][0] \
1656
: \
1657
warnUnsuccessfulReadAttempt(Reduce(Addr--))))
1658
1659
#define GetWORD(Addr) (GetBYTE(Addr) | (GetBYTE(Addr + 1) << 8))
1625
#define REDUCE(Addr) ((Addr) & ADDRMASK)
1626
1627
#define GET_BYTE(Addr) \
1628
((cpu_unit.flags & UNIT_BANKED) ? \
1629
(REDUCE(Addr) < common ? \
1630
M[REDUCE(Addr)][bankSelect] \
1631
: \
1632
M[REDUCE(Addr)][0]) \
1633
: \
1634
(((REDUCE(Addr) < MEMSIZE) || ( (cpu_unit.flags & UNIT_ROM) && (ROMLow <= REDUCE(Addr)) && (REDUCE(Addr) <= ROMHigh) )) ? \
1635
M[REDUCE(Addr)][0] \
1636
: \
1637
warnUnsuccessfulReadAttempt(REDUCE(Addr))))
1638
1639
#define RAM_PP(Addr) \
1640
((cpu_unit.flags & UNIT_BANKED) ? \
1641
(REDUCE(Addr) < common ? \
1642
M[REDUCE(Addr++)][bankSelect] \
1643
: \
1644
M[REDUCE(Addr++)][0]) \
1645
: \
1646
(((REDUCE(Addr) < MEMSIZE) || ( (cpu_unit.flags & UNIT_ROM) && (ROMLow <= REDUCE(Addr)) && (REDUCE(Addr) <= ROMHigh) )) ? \
1647
M[REDUCE(Addr++)][0] \
1648
: \
1649
warnUnsuccessfulReadAttempt(REDUCE(Addr++))))
1650
1651
#define RAM_MM(Addr) \
1652
((cpu_unit.flags & UNIT_BANKED) ? \
1653
(REDUCE(Addr) < common ? \
1654
M[REDUCE(Addr--)][bankSelect] \
1655
: \
1656
M[REDUCE(Addr--)][0]) \
1657
: \
1658
(((REDUCE(Addr) < MEMSIZE) || ( (cpu_unit.flags & UNIT_ROM) && (ROMLow <= REDUCE(Addr)) && (REDUCE(Addr) <= ROMHigh) )) ? \
1659
M[REDUCE(Addr--)][0] \
1660
: \
1661
warnUnsuccessfulReadAttempt(REDUCE(Addr--))))
1662
1663
#define GET_WORD(Addr) (GET_BYTE(Addr) | (GET_BYTE(Addr + 1) << 8))
1660
1664
1661
1665
uint8 GetBYTEWrapper(const uint32 Addr) {
1662
return GetBYTE(Addr);
1666
return GET_BYTE(Addr);
1663
1667
}
1664
1668
1665
1669
void PutBYTEWrapper(const uint32 Addr, const uint32 Value) {
1666
1670
PutBYTE(Addr, Value);
1667
1671
}
1668
1672
1669
#define PutBYTE_pp(a,v) PutBYTE(a++, v)
1670
#define PutBYTE_mm(a,v) PutBYTE(a--, v)
1671
#define mm_PutBYTE(a,v) PutBYTE(--a, v)
1673
#define PUT_BYTE_PP(a,v) PutBYTE(a++, v)
1674
#define PUT_BYTE_MM(a,v) PutBYTE(a--, v)
1675
#define MM_PUT_BYTE(a,v) PutBYTE(--a, v)
1672
1676
1673
1677
#define MASK_BRK (TRUE + 1)
1674
1678
1700
1704
}
1701
1705
1702
1706
#define PUSH(x) { \
1703
mm_PutBYTE(SP, (x) >> 8); \
1704
mm_PutBYTE(SP, x); \
1707
MM_PUT_BYTE(SP, (x) >> 8); \
1708
MM_PUT_BYTE(SP, x); \
1705
1709
}
1706
1710
1707
#define CheckBreakByte(a) \
1708
if (sim_brk_summ && sim_brk_test(a, SWMASK('M'))) { \
1711
#define CHECK_BREAK_BYTE(a) \
1712
if (sim_brk_summ && sim_brk_test(a & 0xffff, SWMASK('M'))) {\
1709
1713
reason = STOP_MEM; \
1710
prepareMemoryAccessMessage(a); \
1714
prepareMemoryAccessMessage(a & 0xffff); \
1711
1715
goto end_decode; \
1712
1716
}
1713
1717
1714
#define CheckBreakTwoBytesExtended(a1, a2, iCode) \
1718
#define CHECK_BREAK_TWO_BYTES_EXTENDED(a1, a2, iCode) \
1715
1719
if (sim_brk_summ) { \
1716
br1 = sim_brk_lookup(a1, SWMASK('M')); \
1717
br2 = br1 ? FALSE : sim_brk_lookup(a2, SWMASK('M')); \
1720
br1 = sim_brk_lookup(a1 & 0xffff, SWMASK('M')); \
1721
br2 = br1 ? FALSE : sim_brk_lookup(a2 & 0xffff, SWMASK('M'));\
1718
1722
if ((br1 == MASK_BRK) || (br2 == MASK_BRK)) { \
1719
1723
sim_brk_pend[0] = FALSE; \
1720
1724
} \
1721
1725
else if (br1 || br2) { \
1722
1726
reason = STOP_MEM; \
1723
1727
if (br1) { \
1724
prepareMemoryAccessMessage(a1); \
1728
prepareMemoryAccessMessage(a1 & 0xffff); \
1725
1729
} \
1726
1730
else { \
1727
prepareMemoryAccessMessage(a2); \
1731
prepareMemoryAccessMessage(a2 & 0xffff); \
1728
1732
} \
1729
1733
iCode; \
1730
1734
goto end_decode; \
1734
1738
} \
1735
1739
}
1736
1740
1737
#define CheckBreakTwoBytes(a1, a2) CheckBreakTwoBytesExtended(a1, a2,;)
1741
#define CHECK_BREAK_TWO_BYTES(a1, a2) CHECK_BREAK_TWO_BYTES_EXTENDED(a1, a2,;)
1738
1742
1739
#define CheckBreakWord(a) CheckBreakTwoBytes(a, (a + 1))
1743
#define CHECK_BREAK_WORD(a) CHECK_BREAK_TWO_BYTES(a, (a + 1))
1740
1744
1741
1745
t_stat sim_instr (void) {
1742
1746
extern int32 sim_interval;
1766
1770
in one microsecond on a 1MHz CPU. tStates is used for real-time simulations. */
1767
1771
register uint32 tStates;
1768
1772
uint32 tStatesInSlice; /* number of t-states in 10 mSec time-slice */
1769
uint32 startTime;
1773
uint32 startTime, now;
1770
1774
int32 br1, br2, tStateModifier = FALSE;
1771
1775
1772
1776
AF = AF_S;
1789
1793
1790
1794
/* main instruction fetch/decode loop */
1791
1795
while (TRUE) { /* loop until halted */
1792
if (sim_interval <= 0) { /* check clock queue */
1796
if (sim_interval <= 0) { /* check clock queue */
1797
#if !UNIX_PLATFORM
1798
if ((reason = sim_poll_kbd()) == SCPE_STOP) { /* poll on platforms without reliable signalling */
1799
break;
1800
}
1801
#endif
1793
1802
if ( (reason = sim_process_event()) ) {
1794
1803
break;
1795
1804
}
1803
1812
/* clockFrequency != 0 implies that real time clock is available */
1804
1813
startTime += sliceLength;
1805
1814
tStates -= tStatesInSlice;
1815
if (startTime > (now = sim_os_msec())) {
1806
1816
#if defined (_WIN32)
1807
while (sim_os_msec() <= startTime) {} /* poor man's sleep */
1817
Sleep(startTime - now);
1808
1818
#else
1809
{
1810
uint32 now;
1811
if (startTime > (now = sim_os_msec())) {
1812
usleep(1000 * (startTime - now));
1813
}
1819
usleep(1000 * (startTime - now));
1820
#endif
1814
1821
}
1815
#endif
1816
1822
}
1817
1823
1818
1824
if (timerInterrupt && (IFF_S & 1)) {
1819
1825
timerInterrupt = FALSE;
1820
1826
specialProcessing = clockFrequency | sim_brk_summ;
1821
1827
IFF_S = 0; /* disable interrupts */
1822
CheckBreakTwoBytesExtended(SP - 2, SP - 1, (timerInterrupt = TRUE, IFF_S |= 1));
1828
CHECK_BREAK_TWO_BYTES_EXTENDED(SP - 2, SP - 1, (timerInterrupt = TRUE, IFF_S |= 1));
1823
1829
PUSH(PC);
1824
1830
PCQ_ENTRY(PC - 1);
1825
1831
PC = timerInterruptHandler & ADDRMASK;
1838
1844
1) Either directly to FALSE if no memory access takes place or
1839
1845
2) through a call to a Check... routine
1840
1846
*/
1841
switch(RAM_pp(PC)) {
1847
switch(RAM_PP(PC)) {
1842
1848
1843
1849
case 0x00: /* NOP */
1844
1850
tStates += 4;
1848
1854
case 0x01: /* LD BC,nnnn */
1849
1855
tStates += 10;
1850
1856
sim_brk_pend[0] = FALSE;
1851
BC = GetWORD(PC);
1857
BC = GET_WORD(PC);
1852
1858
PC += 2;
1853
1859
break;
1854
1860
1855
1861
case 0x02: /* LD (BC),A */
1856
1862
tStates += 7;
1857
CheckBreakByte(BC)
1858
PutBYTE(BC, hreg(AF));
1863
CHECK_BREAK_BYTE(BC)
1864
PutBYTE(BC, HIGH_REGISTER(AF));
1859
1865
break;
1860
1866
1861
1867
case 0x03: /* INC BC */
1868
1874
tStates += 4;
1869
1875
sim_brk_pend[0] = FALSE;
1870
1876
BC += 0x100;
1871
temp = hreg(BC);
1872
AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80); /* SetPV2 uses temp */
1877
temp = HIGH_REGISTER(BC);
1878
AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80); /* SET_PV2 uses temp */
1873
1879
break;
1874
1880
1875
1881
case 0x05: /* DEC B */
1876
1882
tStates += 4;
1877
1883
sim_brk_pend[0] = FALSE;
1878
1884
BC -= 0x100;
1879
temp = hreg(BC);
1880
AF = (AF & ~0xfe) | decTable[temp] | SetPV2(0x7f); /* SetPV2 uses temp */
1885
temp = HIGH_REGISTER(BC);
1886
AF = (AF & ~0xfe) | decTable[temp] | SET_PV2(0x7f); /* SET_PV2 uses temp */
1881
1887
break;
1882
1888
1883
1889
case 0x06: /* LD B,nn */
1884
1890
tStates += 7;
1885
1891
sim_brk_pend[0] = FALSE;
1886
Sethreg(BC, RAM_pp(PC));
1892
SET_HIGH_REGISTER(BC, RAM_PP(PC));
1887
1893
break;
1888
1894
1889
1895
case 0x07: /* RLCA */
1896
1902
case 0x08: /* EX AF,AF' */
1897
1903
tStates += 4;
1898
1904
sim_brk_pend[0] = FALSE;
1899
checkCPU8080;
1905
CHECK_CPU_8080;
1900
1906
temp = AF;
1901
1907
AF = AF1_S;
1902
1908
AF1_S = temp;
1914
1920
1915
1921
case 0x0a: /* LD A,(BC) */
1916
1922
tStates += 7;
1917
CheckBreakByte(BC)
1918
Sethreg(AF, GetBYTE(BC));
1923
CHECK_BREAK_BYTE(BC)
1924
SET_HIGH_REGISTER(AF, GET_BYTE(BC));
1919
1925
break;
1920
1926
1921
1927
case 0x0b: /* DEC BC */
1927
1933
case 0x0c: /* INC C */
1928
1934
tStates += 4;
1929
1935
sim_brk_pend[0] = FALSE;
1930
temp = lreg(BC) + 1;
1931
Setlreg(BC, temp);
1932
AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80);
1936
temp = LOW_REGISTER(BC) + 1;
1937
SET_LOW_REGISTER(BC, temp);
1938
AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80);
1933
1939
break;
1934
1940
1935
1941
case 0x0d: /* DEC C */
1936
1942
tStates += 4;
1937
1943
sim_brk_pend[0] = FALSE;
1938
temp = lreg(BC) - 1;
1939
Setlreg(BC, temp);
1940
AF = (AF & ~0xfe) | decTable[temp & 0xff] | SetPV2(0x7f);
1944
temp = LOW_REGISTER(BC) - 1;
1945
SET_LOW_REGISTER(BC, temp);
1946
AF = (AF & ~0xfe) | decTable[temp & 0xff] | SET_PV2(0x7f);
1941
1947
break;
1942
1948
1943
1949
case 0x0e: /* LD C,nn */
1944
1950
tStates += 7;
1945
1951
sim_brk_pend[0] = FALSE;
1946
Setlreg(BC, RAM_pp(PC));
1952
SET_LOW_REGISTER(BC, RAM_PP(PC));
1947
1953
break;
1948
1954
1949
1955
case 0x0f: /* RRCA */
1950
1956
tStates += 4;
1951
1957
sim_brk_pend[0] = FALSE;
1952
AF = (AF & 0xc4) | rrcaTable[hreg(AF)];
1958
AF = (AF & 0xc4) | rrcaTable[HIGH_REGISTER(AF)];
1953
1959
break;
1954
1960
1955
1961
case 0x10: /* DJNZ dd */
1956
1962
sim_brk_pend[0] = FALSE;
1957
checkCPU8080;
1963
CHECK_CPU_8080;
1958
1964
if ((BC -= 0x100) & 0xff00) {
1959
1965
PCQ_ENTRY(PC - 1);
1960
PC += (int8) GetBYTE(PC) + 1;
1966
PC += (int8) GET_BYTE(PC) + 1;
1961
1967
tStates += 13;
1962
1968
}
1963
1969
else {
1969
1975
case 0x11: /* LD DE,nnnn */
1970
1976
tStates += 10;
1971
1977
sim_brk_pend[0] = FALSE;
1972
DE = GetWORD(PC);
1978
DE = GET_WORD(PC);
1973
1979
PC += 2;
1974
1980
break;
1975
1981
1976
1982
case 0x12: /* LD (DE),A */
1977
1983
tStates += 7;
1978
CheckBreakByte(DE)
1979
PutBYTE(DE, hreg(AF));
1984
CHECK_BREAK_BYTE(DE)
1985
PutBYTE(DE, HIGH_REGISTER(AF));
1980
1986
break;
1981
1987
1982
1988
case 0x13: /* INC DE */
1989
1995
tStates += 4;
1990
1996
sim_brk_pend[0] = FALSE;
1991
1997
DE += 0x100;
1992
temp = hreg(DE);
1993
AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80); /* SetPV2 uses temp */
1998
temp = HIGH_REGISTER(DE);
1999
AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80); /* SET_PV2 uses temp */
1994
2000
break;
1995
2001
1996
2002
case 0x15: /* DEC D */
1997
2003
tStates += 4;
1998
2004
sim_brk_pend[0] = FALSE;
1999
2005
DE -= 0x100;
2000
temp = hreg(DE);
2001
AF = (AF & ~0xfe) | decTable[temp] | SetPV2(0x7f); /* SetPV2 uses temp */
2006
temp = HIGH_REGISTER(DE);
2007
AF = (AF & ~0xfe) | decTable[temp] | SET_PV2(0x7f); /* SET_PV2 uses temp */
2002
2008
break;
2003
2009
2004
2010
case 0x16: /* LD D,nn */
2005
2011
tStates += 7;
2006
2012
sim_brk_pend[0] = FALSE;
2007
Sethreg(DE, RAM_pp(PC));
2013
SET_HIGH_REGISTER(DE, RAM_PP(PC));
2008
2014
break;
2009
2015
2010
2016
case 0x17: /* RLA */
2017
2023
case 0x18: /* JR dd */
2018
2024
tStates += 12;
2019
2025
sim_brk_pend[0] = FALSE;
2020
checkCPU8080;
2026
CHECK_CPU_8080;
2021
2027
PCQ_ENTRY(PC - 1);
2022
PC += (int8) GetBYTE(PC) + 1;
2028
PC += (int8) GET_BYTE(PC) + 1;
2023
2029
break;
2024
2030
2025
2031
case 0x19: /* ADD HL,DE */
2034
2040
2035
2041
case 0x1a: /* LD A,(DE) */
2036
2042
tStates += 7;
2037
CheckBreakByte(DE)
2038
Sethreg(AF, GetBYTE(DE));
2043
CHECK_BREAK_BYTE(DE)
2044
SET_HIGH_REGISTER(AF, GET_BYTE(DE));
2039
2045
break;
2040
2046
2041
2047
case 0x1b: /* DEC DE */
2047
2053
case 0x1c: /* INC E */
2048
2054
tStates += 4;
2049
2055
sim_brk_pend[0] = FALSE;
2050
temp = lreg(DE) + 1;
2051
Setlreg(DE, temp);
2052
AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80);
2056
temp = LOW_REGISTER(DE) + 1;
2057
SET_LOW_REGISTER(DE, temp);
2058
AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80);
2053
2059
break;
2054
2060
2055
2061
case 0x1d: /* DEC E */
2056
2062
tStates += 4;
2057
2063
sim_brk_pend[0] = FALSE;
2058
temp = lreg(DE) - 1;
2059
Setlreg(DE, temp);
2060
AF = (AF & ~0xfe) | decTable[temp & 0xff] | SetPV2(0x7f);
2064
temp = LOW_REGISTER(DE) - 1;
2065
SET_LOW_REGISTER(DE, temp);
2066
AF = (AF & ~0xfe) | decTable[temp & 0xff] | SET_PV2(0x7f);
2061
2067
break;
2062
2068
2063
2069
case 0x1e: /* LD E,nn */
2064
2070
tStates += 7;
2065
2071
sim_brk_pend[0] = FALSE;
2066
Setlreg(DE, RAM_pp(PC));
2072
SET_LOW_REGISTER(DE, RAM_PP(PC));
2067
2073
break;
2068
2074
2069
2075
case 0x1f: /* RRA */
2070
2076
tStates += 4;
2071
2077
sim_brk_pend[0] = FALSE;
2072
AF = ((AF & 1) << 15) | (AF & 0xc4) | rraTable[hreg(AF)];
2078
AF = ((AF & 1) << 15) | (AF & 0xc4) | rraTable[HIGH_REGISTER(AF)];
2073
2079
break;
2074
2080
2075
2081
case 0x20: /* JR NZ,dd */
2076
2082
sim_brk_pend[0] = FALSE;
2077
checkCPU8080;
2083
CHECK_CPU_8080;
2078
2084
if (TSTFLAG(Z)) {
2079
2085
PC++;
2080
2086
tStates += 7;
2081
2087
}
2082
2088
else {
2083
2089
PCQ_ENTRY(PC - 1);
2084
PC += (int8) GetBYTE(PC) + 1;
2090
PC += (int8) GET_BYTE(PC) + 1;
2085
2091
tStates += 12;
2086
2092
}
2087
2093
break;
2089
2095
case 0x21: /* LD HL,nnnn */
2090
2096
tStates += 10;
2091
2097
sim_brk_pend[0] = FALSE;
2092
HL = GetWORD(PC);
2098
HL = GET_WORD(PC);
2093
2099
PC += 2;
2094
2100
break;
2095
2101
2096
2102
case 0x22: /* LD (nnnn),HL */
2097
2103
tStates += 16;
2098
temp = GetWORD(PC);
2099
CheckBreakWord(temp);
2104
temp = GET_WORD(PC);
2105
CHECK_BREAK_WORD(temp);
2100
2106
PutWORD(temp, HL);
2101
2107
PC += 2;
2102
2108
break;
2111
2117
tStates += 4;
2112
2118
sim_brk_pend[0] = FALSE;
2113
2119
HL += 0x100;
2114
temp = hreg(HL);
2115
AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80); /* SetPV2 uses temp */
2120
temp = HIGH_REGISTER(HL);
2121
AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80); /* SET_PV2 uses temp */
2116
2122
break;
2117
2123
2118
2124
case 0x25: /* DEC H */
2119
2125
tStates += 4;
2120
2126
sim_brk_pend[0] = FALSE;
2121
2127
HL -= 0x100;
2122
temp = hreg(HL);
2123
AF = (AF & ~0xfe) | decTable[temp] | SetPV2(0x7f); /* SetPV2 uses temp */
2128
temp = HIGH_REGISTER(HL);
2129
AF = (AF & ~0xfe) | decTable[temp] | SET_PV2(0x7f); /* SET_PV2 uses temp */
2124
2130
break;
2125
2131
2126
2132
case 0x26: /* LD H,nn */
2127
2133
tStates += 7;
2128
2134
sim_brk_pend[0] = FALSE;
2129
Sethreg(HL, RAM_pp(PC));
2135
SET_HIGH_REGISTER(HL, RAM_PP(PC));
2130
2136
break;
2131
2137
2132
2138
case 0x27: /* DAA */
2133
2139
tStates += 4;
2134
2140
sim_brk_pend[0] = FALSE;
2135
acu = hreg(AF);
2136
temp = ldig(acu);
2141
acu = HIGH_REGISTER(AF);
2142
temp = LOW_DIGIT(acu);
2137
2143
cbits = TSTFLAG(C);
2138
2144
if (TSTFLAG(N)) { /* last operation was a subtract */
2139
2145
int hd = cbits || acu > 0x99;
2162
2168
2163
2169
case 0x28: /* JR Z,dd */
2164
2170
sim_brk_pend[0] = FALSE;
2165
checkCPU8080;
2171
CHECK_CPU_8080;
2166
2172
if (TSTFLAG(Z)) {
2167
2173
PCQ_ENTRY(PC - 1);
2168
PC += (int8) GetBYTE(PC) + 1;
2174
PC += (int8) GET_BYTE(PC) + 1;
2169
2175
tStates += 12;
2170
2176
}
2171
2177
else {
2185
2191
2186
2192
case 0x2a: /* LD HL,(nnnn) */
2187
2193
tStates += 16;
2188
temp = GetWORD(PC);
2189
CheckBreakWord(temp);
2190
HL = GetWORD(temp);
2194
temp = GET_WORD(PC);
2195
CHECK_BREAK_WORD(temp);
2196
HL = GET_WORD(temp);
2191
2197
PC += 2;
2192
2198
break;
2193
2199
2200
2206
case 0x2c: /* INC L */
2201
2207
tStates += 4;
2202
2208
sim_brk_pend[0] = FALSE;
2203
temp = lreg(HL) + 1;
2204
Setlreg(HL, temp);
2205
AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80);
2209
temp = LOW_REGISTER(HL) + 1;
2210
SET_LOW_REGISTER(HL, temp);
2211
AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80);
2206
2212
break;
2207
2213
2208
2214
case 0x2d: /* DEC L */
2209
2215
tStates += 4;
2210
2216
sim_brk_pend[0] = FALSE;
2211
temp = lreg(HL) - 1;
2212
Setlreg(HL, temp);
2213
AF = (AF & ~0xfe) | decTable[temp & 0xff] | SetPV2(0x7f);
2217
temp = LOW_REGISTER(HL) - 1;
2218
SET_LOW_REGISTER(HL, temp);
2219
AF = (AF & ~0xfe) | decTable[temp & 0xff] | SET_PV2(0x7f);
2214
2220
break;
2215
2221
2216
2222
case 0x2e: /* LD L,nn */
2217
2223
tStates += 7;
2218
2224
sim_brk_pend[0] = FALSE;
2219
Setlreg(HL, RAM_pp(PC));
2225
SET_LOW_REGISTER(HL, RAM_PP(PC));
2220
2226
break;
2221
2227
2222
2228
case 0x2f: /* CPL */
2227
2233
2228
2234
case 0x30: /* JR NC,dd */
2229
2235
sim_brk_pend[0] = FALSE;
2230
checkCPU8080;
2236
CHECK_CPU_8080;
2231
2237
if (TSTFLAG(C)) {
2232
2238
PC++;
2233
2239
tStates += 7;
2234
2240
}
2235
2241
else {
2236
2242
PCQ_ENTRY(PC - 1);
2237
PC += (int8) GetBYTE(PC) + 1;
2243
PC += (int8) GET_BYTE(PC) + 1;
2238
2244
tStates += 12;
2239
2245
}
2240
2246
break;
2242
2248
case 0x31: /* LD SP,nnnn */
2243
2249
tStates += 10;
2244
2250
sim_brk_pend[0] = FALSE;
2245
SP = GetWORD(PC);
2251
SP = GET_WORD(PC);
2246
2252
PC += 2;
2247
2253
break;
2248
2254
2249
2255
case 0x32: /* LD (nnnn),A */
2250
2256
tStates += 13;
2251
temp = GetWORD(PC);
2252
CheckBreakByte(temp);
2253
PutBYTE(temp, hreg(AF));
2257
temp = GET_WORD(PC);
2258
CHECK_BREAK_BYTE(temp);
2259
PutBYTE(temp, HIGH_REGISTER(AF));
2254
2260
PC += 2;
2255
2261
break;
2256
2262
2262
2268
2263
2269
case 0x34: /* INC (HL) */
2264
2270
tStates += 11;
2265
CheckBreakByte(HL);
2266
temp = GetBYTE(HL) + 1;
2271
CHECK_BREAK_BYTE(HL);
2272
temp = GET_BYTE(HL) + 1;
2267
2273
PutBYTE(HL, temp);
2268
AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80);
2274
AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80);
2269
2275
break;
2270
2276
2271
2277
case 0x35: /* DEC (HL) */
2272
2278
tStates += 11;
2273
CheckBreakByte(HL);
2274
temp = GetBYTE(HL) - 1;
2279
CHECK_BREAK_BYTE(HL);
2280
temp = GET_BYTE(HL) - 1;
2275
2281
PutBYTE(HL, temp);
2276
AF = (AF & ~0xfe) | decTable[temp & 0xff] | SetPV2(0x7f);
2282
AF = (AF & ~0xfe) | decTable[temp & 0xff] | SET_PV2(0x7f);
2277
2283
break;
2278
2284
2279
2285
case 0x36: /* LD (HL),nn */
2280
2286
tStates += 10;
2281
CheckBreakByte(HL);
2282
PutBYTE(HL, RAM_pp(PC));
2287
CHECK_BREAK_BYTE(HL);
2288
PutBYTE(HL, RAM_PP(PC));
2283
2289
break;
2284
2290
2285
2291
case 0x37: /* SCF */
2290
2296
2291
2297
case 0x38: /* JR C,dd */
2292
2298
sim_brk_pend[0] = FALSE;
2293
checkCPU8080;
2299
CHECK_CPU_8080;
2294
2300
if (TSTFLAG(C)) {
2295
2301
PCQ_ENTRY(PC - 1);
2296
PC += (int8) GetBYTE(PC) + 1;
2302
PC += (int8) GET_BYTE(PC) + 1;
2297
2303
tStates += 12;
2298
2304
}
2299
2305
else {
2314
2320
2315
2321
case 0x3a: /* LD A,(nnnn) */
2316
2322
tStates += 13;
2317
temp = GetWORD(PC);
2318
CheckBreakByte(temp);
2319
Sethreg(AF, GetBYTE(temp));
2323
temp = GET_WORD(PC);
2324
CHECK_BREAK_BYTE(temp);
2325
SET_HIGH_REGISTER(AF, GET_BYTE(temp));
2320
2326
PC += 2;
2321
2327
break;
2322
2328
2330
2336
tStates += 4;
2331
2337
sim_brk_pend[0] = FALSE;
2332
2338
AF += 0x100;
2333
temp = hreg(AF);
2334
AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80); /* SetPV2 uses temp */
2339
temp = HIGH_REGISTER(AF);
2340
AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80); /* SET_PV2 uses temp */
2335
2341
break;
2336
2342
2337
2343
case 0x3d: /* DEC A */
2338
2344
tStates += 4;
2339
2345
sim_brk_pend[0] = FALSE;
2340
2346
AF -= 0x100;
2341
temp = hreg(AF);
2342
AF = (AF & ~0xfe) | decTable[temp] | SetPV2(0x7f); /* SetPV2 uses temp */
2347
temp = HIGH_REGISTER(AF);
2348
AF = (AF & ~0xfe) | decTable[temp] | SET_PV2(0x7f); /* SET_PV2 uses temp */
2343
2349
break;
2344
2350
2345
2351
case 0x3e: /* LD A,nn */
2346
2352
tStates += 7;
2347
2353
sim_brk_pend[0] = FALSE;
2348
Sethreg(AF, RAM_pp(PC));
2354
SET_HIGH_REGISTER(AF, RAM_PP(PC));
2349
2355
break;
2350
2356
2351
2357
case 0x3f: /* CCF */
2391
2397
2392
2398
case 0x46: /* LD B,(HL) */
2393
2399
tStates += 7;
2394
CheckBreakByte(HL);
2395
Sethreg(BC, GetBYTE(HL));
2400
CHECK_BREAK_BYTE(HL);
2401
SET_HIGH_REGISTER(BC, GET_BYTE(HL));
2396
2402
break;
2397
2403
2398
2404
case 0x47: /* LD B,A */
2438
2444
2439
2445
case 0x4e: /* LD C,(HL) */
2440
2446
tStates += 7;
2441
CheckBreakByte(HL);
2442
Setlreg(BC, GetBYTE(HL));
2447
CHECK_BREAK_BYTE(HL);
2448
SET_LOW_REGISTER(BC, GET_BYTE(HL));
2443
2449
break;
2444
2450
2445
2451
case 0x4f: /* LD C,A */
2485
2491
2486
2492
case 0x56: /* LD D,(HL) */
2487
2493
tStates += 7;
2488
CheckBreakByte(HL);
2489
Sethreg(DE, GetBYTE(HL));
2494
CHECK_BREAK_BYTE(HL);
2495
SET_HIGH_REGISTER(DE, GET_BYTE(HL));
2490
2496
break;
2491
2497
2492
2498
case 0x57: /* LD D,A */
2532
2538
2533
2539
case 0x5e: /* LD E,(HL) */
2534
2540
tStates += 7;
2535
CheckBreakByte(HL);
2536
Setlreg(DE, GetBYTE(HL));
2541
CHECK_BREAK_BYTE(HL);
2542
SET_LOW_REGISTER(DE, GET_BYTE(HL));
2537
2543
break;
2538
2544
2539
2545
case 0x5f: /* LD E,A */
2579
2585
2580
2586
case 0x66: /* LD H,(HL) */
2581
2587
tStates += 7;
2582
CheckBreakByte(HL);
2583
Sethreg(HL, GetBYTE(HL));
2588
CHECK_BREAK_BYTE(HL);
2589
SET_HIGH_REGISTER(HL, GET_BYTE(HL));
2584
2590
break;
2585
2591
2586
2592
case 0x67: /* LD H,A */
2626
2632
2627
2633
case 0x6e: /* LD L,(HL) */
2628
2634
tStates += 7;
2629
CheckBreakByte(HL);
2630
Setlreg(HL, GetBYTE(HL));
2635
CHECK_BREAK_BYTE(HL);
2636
SET_LOW_REGISTER(HL, GET_BYTE(HL));
2631
2637
break;
2632
2638
2633
2639
case 0x6f: /* LD L,A */
2638
2644
2639
2645
case 0x70: /* LD (HL),B */
2640
2646
tStates += 7;
2641
CheckBreakByte(HL);
2642
PutBYTE(HL, hreg(BC));
2647
CHECK_BREAK_BYTE(HL);
2648
PutBYTE(HL, HIGH_REGISTER(BC));
2643
2649
break;
2644
2650
2645
2651
case 0x71: /* LD (HL),C */
2646
2652
tStates += 7;
2647
CheckBreakByte(HL);
2648
PutBYTE(HL, lreg(BC));
2653
CHECK_BREAK_BYTE(HL);
2654
PutBYTE(HL, LOW_REGISTER(BC));
2649
2655
break;
2650
2656
2651
2657
case 0x72: /* LD (HL),D */
2652
2658
tStates += 7;
2653
CheckBreakByte(HL);
2654
PutBYTE(HL, hreg(DE));
2659
CHECK_BREAK_BYTE(HL);
2660
PutBYTE(HL, HIGH_REGISTER(DE));
2655
2661
break;
2656
2662
2657
2663
case 0x73: /* LD (HL),E */
2658
2664
tStates += 7;
2659
CheckBreakByte(HL);
2660
PutBYTE(HL, lreg(DE));
2665
CHECK_BREAK_BYTE(HL);
2666
PutBYTE(HL, LOW_REGISTER(DE));
2661
2667
break;
2662
2668
2663
2669
case 0x74: /* LD (HL),H */
2664
2670
tStates += 7;
2665
CheckBreakByte(HL);
2666
PutBYTE(HL, hreg(HL));
2671
CHECK_BREAK_BYTE(HL);
2672
PutBYTE(HL, HIGH_REGISTER(HL));
2667
2673
break;
2668
2674
2669
2675
case 0x75: /* LD (HL),L */
2670
2676
tStates += 7;
2671
CheckBreakByte(HL);
2672
PutBYTE(HL, lreg(HL));
2677
CHECK_BREAK_BYTE(HL);
2678
PutBYTE(HL, LOW_REGISTER(HL));
2673
2679
break;
2674
2680
2675
2681
case 0x76: /* HALT */
2681
2687
2682
2688
case 0x77: /* LD (HL),A */
2683
2689
tStates += 7;
2684
CheckBreakByte(HL);
2685
PutBYTE(HL, hreg(AF));
2690
CHECK_BREAK_BYTE(HL);
2691
PutBYTE(HL, HIGH_REGISTER(AF));
2686
2692
break;
2687
2693
2688
2694
case 0x78: /* LD A,B */
2723
2729
2724
2730
case 0x7e: /* LD A,(HL) */
2725
2731
tStates += 7;
2726
CheckBreakByte(HL);
2727
Sethreg(AF, GetBYTE(HL));
2732
CHECK_BREAK_BYTE(HL);
2733
SET_HIGH_REGISTER(AF, GET_BYTE(HL));
2728
2734
break;
2729
2735
2730
2736
case 0x7f: /* LD A,A */
2735
2741
case 0x80: /* ADD A,B */
2736
2742
tStates += 4;
2737
2743
sim_brk_pend[0] = FALSE;
2738
temp = hreg(BC);
2739
acu = hreg(AF);
2744
temp = HIGH_REGISTER(BC);
2745
acu = HIGH_REGISTER(AF);
2740
2746
sum = acu + temp;
2741
2747
cbits = acu ^ temp ^ sum;
2742
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
2748
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
2743
2749
break;
2744
2750
2745
2751
case 0x81: /* ADD A,C */
2746
2752
tStates += 4;
2747
2753
sim_brk_pend[0] = FALSE;
2748
temp = lreg(BC);
2749
acu = hreg(AF);
2754
temp = LOW_REGISTER(BC);
2755
acu = HIGH_REGISTER(AF);
2750
2756
sum = acu + temp;
2751
2757
cbits = acu ^ temp ^ sum;
2752
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
2758
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
2753
2759
break;
2754
2760
2755
2761
case 0x82: /* ADD A,D */
2756
2762
tStates += 4;
2757
2763
sim_brk_pend[0] = FALSE;
2758
temp = hreg(DE);
2759
acu = hreg(AF);
2764
temp = HIGH_REGISTER(DE);
2765
acu = HIGH_REGISTER(AF);
2760
2766
sum = acu + temp;
2761
2767
cbits = acu ^ temp ^ sum;
2762
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
2768
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
2763
2769
break;
2764
2770
2765
2771
case 0x83: /* ADD A,E */
2766
2772
tStates += 4;
2767
2773
sim_brk_pend[0] = FALSE;
2768
temp = lreg(DE);
2769
acu = hreg(AF);
2774
temp = LOW_REGISTER(DE);
2775
acu = HIGH_REGISTER(AF);
2770
2776
sum = acu + temp;
2771
2777
cbits = acu ^ temp ^ sum;
2772
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
2778
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
2773
2779
break;
2774
2780
2775
2781
case 0x84: /* ADD A,H */
2776
2782
tStates += 4;
2777
2783
sim_brk_pend[0] = FALSE;
2778
temp = hreg(HL);
2779
acu = hreg(AF);
2784
temp = HIGH_REGISTER(HL);
2785
acu = HIGH_REGISTER(AF);
2780
2786
sum = acu + temp;
2781
2787
cbits = acu ^ temp ^ sum;
2782
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
2788
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
2783
2789
break;
2784
2790
2785
2791
case 0x85: /* ADD A,L */
2786
2792
tStates += 4;
2787
2793
sim_brk_pend[0] = FALSE;
2788
temp = lreg(HL);
2789
acu = hreg(AF);
2794
temp = LOW_REGISTER(HL);
2795
acu = HIGH_REGISTER(AF);
2790
2796
sum = acu + temp;
2791
2797
cbits = acu ^ temp ^ sum;
2792
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
2798
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
2793
2799
break;
2794
2800
2795
2801
case 0x86: /* ADD A,(HL) */
2796
2802
tStates += 7;
2797
CheckBreakByte(HL);
2798
temp = GetBYTE(HL);
2799
acu = hreg(AF);
2803
CHECK_BREAK_BYTE(HL);
2804
temp = GET_BYTE(HL);
2805
acu = HIGH_REGISTER(AF);
2800
2806
sum = acu + temp;
2801
2807
cbits = acu ^ temp ^ sum;
2802
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
2808
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
2803
2809
break;
2804
2810
2805
2811
case 0x87: /* ADD A,A */
2806
2812
tStates += 4;
2807
2813
sim_brk_pend[0] = FALSE;
2808
cbits = 2 * hreg(AF);
2809
AF = cbitsDup8Table[cbits] | (SetPVS(cbits));
2814
cbits = 2 * HIGH_REGISTER(AF);
2815
AF = cbitsDup8Table[cbits] | (SET_PVS(cbits));
2810
2816
break;
2811
2817
2812
2818
case 0x88: /* ADC A,B */
2813
2819
tStates += 4;
2814
2820
sim_brk_pend[0] = FALSE;
2815
temp = hreg(BC);
2816
acu = hreg(AF);
2821
temp = HIGH_REGISTER(BC);
2822
acu = HIGH_REGISTER(AF);
2817
2823
sum = acu + temp + TSTFLAG(C);
2818
2824
cbits = acu ^ temp ^ sum;
2819
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
2825
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
2820
2826
break;
2821
2827
2822
2828
case 0x89: /* ADC A,C */
2823
2829
tStates += 4;
2824
2830
sim_brk_pend[0] = FALSE;
2825
temp = lreg(BC);
2826
acu = hreg(AF);
2831
temp = LOW_REGISTER(BC);
2832
acu = HIGH_REGISTER(AF);
2827
2833
sum = acu + temp + TSTFLAG(C);
2828
2834
cbits = acu ^ temp ^ sum;
2829
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
2835
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
2830
2836
break;
2831
2837
2832
2838
case 0x8a: /* ADC A,D */
2833
2839
tStates += 4;
2834
2840
sim_brk_pend[0] = FALSE;
2835
temp = hreg(DE);
2836
acu = hreg(AF);
2841
temp = HIGH_REGISTER(DE);
2842
acu = HIGH_REGISTER(AF);
2837
2843
sum = acu + temp + TSTFLAG(C);
2838
2844
cbits = acu ^ temp ^ sum;
2839
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
2845
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
2840
2846
break;
2841
2847
2842
2848
case 0x8b: /* ADC A,E */
2843
2849
tStates += 4;
2844
2850
sim_brk_pend[0] = FALSE;
2845
temp = lreg(DE);
2846
acu = hreg(AF);
2851
temp = LOW_REGISTER(DE);
2852
acu = HIGH_REGISTER(AF);
2847
2853
sum = acu + temp + TSTFLAG(C);
2848
2854
cbits = acu ^ temp ^ sum;
2849
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
2855
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
2850
2856
break;
2851
2857
2852
2858
case 0x8c: /* ADC A,H */
2853
2859
tStates += 4;
2854
2860
sim_brk_pend[0] = FALSE;
2855
temp = hreg(HL);
2856
acu = hreg(AF);
2861
temp = HIGH_REGISTER(HL);
2862
acu = HIGH_REGISTER(AF);
2857
2863
sum = acu + temp + TSTFLAG(C);
2858
2864
cbits = acu ^ temp ^ sum;
2859
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
2865
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
2860
2866
break;
2861
2867
2862
2868
case 0x8d: /* ADC A,L */
2863
2869
tStates += 4;
2864
2870
sim_brk_pend[0] = FALSE;
2865
temp = lreg(HL);
2866
acu = hreg(AF);
2871
temp = LOW_REGISTER(HL);
2872
acu = HIGH_REGISTER(AF);
2867
2873
sum = acu + temp + TSTFLAG(C);
2868
2874
cbits = acu ^ temp ^ sum;
2869
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
2875
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
2870
2876
break;
2871
2877
2872
2878
case 0x8e: /* ADC A,(HL) */
2873
2879
tStates += 7;
2874
CheckBreakByte(HL);
2875
temp = GetBYTE(HL);
2876
acu = hreg(AF);
2880
CHECK_BREAK_BYTE(HL);
2881
temp = GET_BYTE(HL);
2882
acu = HIGH_REGISTER(AF);
2877
2883
sum = acu + temp + TSTFLAG(C);
2878
2884
cbits = acu ^ temp ^ sum;
2879
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
2885
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
2880
2886
break;
2881
2887
2882
2888
case 0x8f: /* ADC A,A */
2883
2889
tStates += 4;
2884
2890
sim_brk_pend[0] = FALSE;
2885
cbits = 2 * hreg(AF) + TSTFLAG(C);
2886
AF = cbitsDup8Table[cbits] | (SetPVS(cbits));
2891
cbits = 2 * HIGH_REGISTER(AF) + TSTFLAG(C);
2892
AF = cbitsDup8Table[cbits] | (SET_PVS(cbits));
2887
2893
break;
2888
2894
2889
2895
case 0x90: /* SUB B */
2890
2896
tStates += 4;
2891
2897
sim_brk_pend[0] = FALSE;
2892
temp = hreg(BC);
2893
acu = hreg(AF);
2898
temp = HIGH_REGISTER(BC);
2899
acu = HIGH_REGISTER(AF);
2894
2900
sum = acu - temp;
2895
2901
cbits = acu ^ temp ^ sum;
2896
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
2902
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
2897
2903
break;
2898
2904
2899
2905
case 0x91: /* SUB C */
2900
2906
tStates += 4;
2901
2907
sim_brk_pend[0] = FALSE;
2902
temp = lreg(BC);
2903
acu = hreg(AF);
2908
temp = LOW_REGISTER(BC);
2909
acu = HIGH_REGISTER(AF);
2904
2910
sum = acu - temp;
2905
2911
cbits = acu ^ temp ^ sum;
2906
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
2912
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
2907
2913
break;
2908
2914
2909
2915
case 0x92: /* SUB D */
2910
2916
tStates += 4;
2911
2917
sim_brk_pend[0] = FALSE;
2912
temp = hreg(DE);
2913
acu = hreg(AF);
2918
temp = HIGH_REGISTER(DE);
2919
acu = HIGH_REGISTER(AF);
2914
2920
sum = acu - temp;
2915
2921
cbits = acu ^ temp ^ sum;
2916
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
2922
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
2917
2923
break;
2918
2924
2919
2925
case 0x93: /* SUB E */
2920
2926
tStates += 4;
2921
2927
sim_brk_pend[0] = FALSE;
2922
temp = lreg(DE);
2923
acu = hreg(AF);
2928
temp = LOW_REGISTER(DE);
2929
acu = HIGH_REGISTER(AF);
2924
2930
sum = acu - temp;
2925
2931
cbits = acu ^ temp ^ sum;
2926
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
2932
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
2927
2933
break;
2928
2934
2929
2935
case 0x94: /* SUB H */
2930
2936
tStates += 4;
2931
2937
sim_brk_pend[0] = FALSE;
2932
temp = hreg(HL);
2933
acu = hreg(AF);
2938
temp = HIGH_REGISTER(HL);
2939
acu = HIGH_REGISTER(AF);
2934
2940
sum = acu - temp;
2935
2941
cbits = acu ^ temp ^ sum;
2936
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
2942
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
2937
2943
break;
2938
2944
2939
2945
case 0x95: /* SUB L */
2940
2946
tStates += 4;
2941
2947
sim_brk_pend[0] = FALSE;
2942
temp = lreg(HL);
2943
acu = hreg(AF);
2948
temp = LOW_REGISTER(HL);
2949
acu = HIGH_REGISTER(AF);
2944
2950
sum = acu - temp;
2945
2951
cbits = acu ^ temp ^ sum;
2946
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
2952
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
2947
2953
break;
2948
2954
2949
2955
case 0x96: /* SUB (HL) */
2950
2956
tStates += 7;
2951
CheckBreakByte(HL);
2952
temp = GetBYTE(HL);
2953
acu = hreg(AF);
2957
CHECK_BREAK_BYTE(HL);
2958
temp = GET_BYTE(HL);
2959
acu = HIGH_REGISTER(AF);
2954
2960
sum = acu - temp;
2955
2961
cbits = acu ^ temp ^ sum;
2956
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
2962
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
2957
2963
break;
2958
2964
2959
2965
case 0x97: /* SUB A */
2965
2971
case 0x98: /* SBC A,B */
2966
2972
tStates += 4;
2967
2973
sim_brk_pend[0] = FALSE;
2968
temp = hreg(BC);
2969
acu = hreg(AF);
2974
temp = HIGH_REGISTER(BC);
2975
acu = HIGH_REGISTER(AF);
2970
2976
sum = acu - temp - TSTFLAG(C);
2971
2977
cbits = acu ^ temp ^ sum;
2972
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
2978
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
2973
2979
break;
2974
2980
2975
2981
case 0x99: /* SBC A,C */
2976
2982
tStates += 4;
2977
2983
sim_brk_pend[0] = FALSE;
2978
temp = lreg(BC);
2979
acu = hreg(AF);
2984
temp = LOW_REGISTER(BC);
2985
acu = HIGH_REGISTER(AF);
2980
2986
sum = acu - temp - TSTFLAG(C);
2981
2987
cbits = acu ^ temp ^ sum;
2982
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
2988
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
2983
2989
break;
2984
2990
2985
2991
case 0x9a: /* SBC A,D */
2986
2992
tStates += 4;
2987
2993
sim_brk_pend[0] = FALSE;
2988
temp = hreg(DE);
2989
acu = hreg(AF);
2994
temp = HIGH_REGISTER(DE);
2995
acu = HIGH_REGISTER(AF);
2990
2996
sum = acu - temp - TSTFLAG(C);
2991
2997
cbits = acu ^ temp ^ sum;
2992
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
2998
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
2993
2999
break;
2994
3000
2995
3001
case 0x9b: /* SBC A,E */
2996
3002
tStates += 4;
2997
3003
sim_brk_pend[0] = FALSE;
2998
temp = lreg(DE);
2999
acu = hreg(AF);
3004
temp = LOW_REGISTER(DE);
3005
acu = HIGH_REGISTER(AF);
3000
3006
sum = acu - temp - TSTFLAG(C);
3001
3007
cbits = acu ^ temp ^ sum;
3002
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
3008
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
3003
3009
break;
3004
3010
3005
3011
case 0x9c: /* SBC A,H */
3006
3012
tStates += 4;
3007
3013
sim_brk_pend[0] = FALSE;
3008
temp = hreg(HL);
3009
acu = hreg(AF);
3014
temp = HIGH_REGISTER(HL);
3015
acu = HIGH_REGISTER(AF);
3010
3016
sum = acu - temp - TSTFLAG(C);
3011
3017
cbits = acu ^ temp ^ sum;
3012
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
3018
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
3013
3019
break;
3014
3020
3015
3021
case 0x9d: /* SBC A,L */
3016
3022
tStates += 4;
3017
3023
sim_brk_pend[0] = FALSE;
3018
temp = lreg(HL);
3019
acu = hreg(AF);
3024
temp = LOW_REGISTER(HL);
3025
acu = HIGH_REGISTER(AF);
3020
3026
sum = acu - temp - TSTFLAG(C);
3021
3027
cbits = acu ^ temp ^ sum;
3022
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
3028
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
3023
3029
break;
3024
3030
3025
3031
case 0x9e: /* SBC A,(HL) */
3026
3032
tStates += 7;
3027
CheckBreakByte(HL);
3028
temp = GetBYTE(HL);
3029
acu = hreg(AF);
3033
CHECK_BREAK_BYTE(HL);
3034
temp = GET_BYTE(HL);
3035
acu = HIGH_REGISTER(AF);
3030
3036
sum = acu - temp - TSTFLAG(C);
3031
3037
cbits = acu ^ temp ^ sum;
3032
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
3038
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
3033
3039
break;
3034
3040
3035
3041
case 0x9f: /* SBC A,A */
3036
3042
tStates += 4;
3037
3043
sim_brk_pend[0] = FALSE;
3038
3044
cbits = -TSTFLAG(C);
3039
AF = subTable[cbits & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPVS(cbits));
3045
AF = subTable[cbits & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PVS(cbits));
3040
3046
break;
3041
3047
3042
3048
case 0xa0: /* AND B */
3077
3083
3078
3084
case 0xa6: /* AND (HL) */
3079
3085
tStates += 7;
3080
CheckBreakByte(HL);
3081
AF = andTable[((AF >> 8) & GetBYTE(HL)) & 0xff];
3086
CHECK_BREAK_BYTE(HL);
3087
AF = andTable[((AF >> 8) & GET_BYTE(HL)) & 0xff];
3082
3088
break;
3083
3089
3084
3090
case 0xa7: /* AND A */
3125
3131
3126
3132
case 0xae: /* XOR (HL) */
3127
3133
tStates += 7;
3128
CheckBreakByte(HL);
3129
AF = xororTable[((AF >> 8) ^ GetBYTE(HL)) & 0xff];
3134
CHECK_BREAK_BYTE(HL);
3135
AF = xororTable[((AF >> 8) ^ GET_BYTE(HL)) & 0xff];
3130
3136
break;
3131
3137
3132
3138
case 0xaf: /* XOR A */
3173
3179
3174
3180
case 0xb6: /* OR (HL) */
3175
3181
tStates += 7;
3176
CheckBreakByte(HL);
3177
AF = xororTable[((AF >> 8) | GetBYTE(HL)) & 0xff];
3182
CHECK_BREAK_BYTE(HL);
3183
AF = xororTable[((AF >> 8) | GET_BYTE(HL)) & 0xff];
3178
3184
break;
3179
3185
3180
3186
case 0xb7: /* OR A */
3186
3192
case 0xb8: /* CP B */
3187
3193
tStates += 4;
3188
3194
sim_brk_pend[0] = FALSE;
3189
temp = hreg(BC);
3195
temp = HIGH_REGISTER(BC);
3190
3196
AF = (AF & ~0x28) | (temp & 0x28);
3191
acu = hreg(AF);
3197
acu = HIGH_REGISTER(AF);
3192
3198
sum = acu - temp;
3193
3199
cbits = acu ^ temp ^ sum;
3194
3200
AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |
3195
(SetPV) | cbits2Table[cbits & 0x1ff];
3201
(SET_PV) | cbits2Table[cbits & 0x1ff];
3196
3202
break;
3197
3203
3198
3204
case 0xb9: /* CP C */
3199
3205
tStates += 4;
3200
3206
sim_brk_pend[0] = FALSE;
3201
temp = lreg(BC);
3207
temp = LOW_REGISTER(BC);
3202
3208
AF = (AF & ~0x28) | (temp & 0x28);
3203
acu = hreg(AF);
3209
acu = HIGH_REGISTER(AF);
3204
3210
sum = acu - temp;
3205
3211
cbits = acu ^ temp ^ sum;
3206
3212
AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |
3207
(SetPV) | cbits2Table[cbits & 0x1ff];
3213
(SET_PV) | cbits2Table[cbits & 0x1ff];
3208
3214
break;
3209
3215
3210
3216
case 0xba: /* CP D */
3211
3217
tStates += 4;
3212
3218
sim_brk_pend[0] = FALSE;
3213
temp = hreg(DE);
3219
temp = HIGH_REGISTER(DE);
3214
3220
AF = (AF & ~0x28) | (temp & 0x28);
3215
acu = hreg(AF);
3221
acu = HIGH_REGISTER(AF);
3216
3222
sum = acu - temp;
3217
3223
cbits = acu ^ temp ^ sum;
3218
3224
AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |
3219
(SetPV) | cbits2Table[cbits & 0x1ff];
3225
(SET_PV) | cbits2Table[cbits & 0x1ff];
3220
3226
break;
3221
3227
3222
3228
case 0xbb: /* CP E */
3223
3229
tStates += 4;
3224
3230
sim_brk_pend[0] = FALSE;
3225
temp = lreg(DE);
3231
temp = LOW_REGISTER(DE);
3226
3232
AF = (AF & ~0x28) | (temp & 0x28);
3227
acu = hreg(AF);
3233
acu = HIGH_REGISTER(AF);
3228
3234
sum = acu - temp;
3229
3235
cbits = acu ^ temp ^ sum;
3230
3236
AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |
3231
(SetPV) | cbits2Table[cbits & 0x1ff];
3237
(SET_PV) | cbits2Table[cbits & 0x1ff];
3232
3238
break;
3233
3239
3234
3240
case 0xbc: /* CP H */
3235
3241
tStates += 4;
3236
3242
sim_brk_pend[0] = FALSE;
3237
temp = hreg(HL);
3243
temp = HIGH_REGISTER(HL);
3238
3244
AF = (AF & ~0x28) | (temp & 0x28);
3239
acu = hreg(AF);
3245
acu = HIGH_REGISTER(AF);
3240
3246
sum = acu - temp;
3241
3247
cbits = acu ^ temp ^ sum;
3242
3248
AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |
3243
(SetPV) | cbits2Table[cbits & 0x1ff];
3249
(SET_PV) | cbits2Table[cbits & 0x1ff];
3244
3250
break;
3245
3251
3246
3252
case 0xbd: /* CP L */
3247
3253
tStates += 4;
3248
3254
sim_brk_pend[0] = FALSE;
3249
temp = lreg(HL);
3255
temp = LOW_REGISTER(HL);
3250
3256
AF = (AF & ~0x28) | (temp & 0x28);
3251
acu = hreg(AF);
3257
acu = HIGH_REGISTER(AF);
3252
3258
sum = acu - temp;
3253
3259
cbits = acu ^ temp ^ sum;
3254
3260
AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |
3255
(SetPV) | cbits2Table[cbits & 0x1ff];
3261
(SET_PV) | cbits2Table[cbits & 0x1ff];
3256
3262
break;
3257
3263
3258
3264
case 0xbe: /* CP (HL) */
3259
3265
tStates += 7;
3260
CheckBreakByte(HL);
3261
temp = GetBYTE(HL);
3266
CHECK_BREAK_BYTE(HL);
3267
temp = GET_BYTE(HL);
3262
3268
AF = (AF & ~0x28) | (temp & 0x28);
3263
acu = hreg(AF);
3269
acu = HIGH_REGISTER(AF);
3264
3270
sum = acu - temp;
3265
3271
cbits = acu ^ temp ^ sum;
3266
3272
AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |
3267
(SetPV) | cbits2Table[cbits & 0x1ff];
3273
(SET_PV) | cbits2Table[cbits & 0x1ff];
3268
3274
break;
3269
3275
3270
3276
case 0xbf: /* CP A */
3271
3277
tStates += 4;
3272
3278
sim_brk_pend[0] = FALSE;
3273
Setlreg(AF, (hreg(AF) & 0x28) | (cpu_unit.flags & UNIT_CHIP ? 0x42 : 0x46));
3279
SET_LOW_REGISTER(AF, (HIGH_REGISTER(AF) & 0x28) | (cpu_unit.flags & UNIT_CHIP ? 0x42 : 0x46));
3274
3280
break;
3275
3281
3276
3282
case 0xc0: /* RET NZ */
3279
3285
tStates += 5;
3280
3286
}
3281
3287
else {
3282
CheckBreakWord(SP);
3288
CHECK_BREAK_WORD(SP);
3283
3289
PCQ_ENTRY(PC - 1);
3284
3290
POP(PC);
3285
3291
tStates += 11;
3288
3294
3289
3295
case 0xc1: /* POP BC */
3290
3296
tStates += 10;
3291
CheckBreakWord(SP);
3297
CHECK_BREAK_WORD(SP);
3292
3298
POP(BC);
3293
3299
break;
3294
3300
3308
3314
3309
3315
case 0xc5: /* PUSH BC */
3310
3316
tStates += 11;
3311
CheckBreakWord(SP - 2);
3317
CHECK_BREAK_WORD(SP - 2);
3312
3318
PUSH(BC);
3313
3319
break;
3314
3320
3315
3321
case 0xc6: /* ADD A,nn */
3316
3322
tStates += 7;
3317
3323
sim_brk_pend[0] = FALSE;
3318
temp = RAM_pp(PC);
3319
acu = hreg(AF);
3324
temp = RAM_PP(PC);
3325
acu = HIGH_REGISTER(AF);
3320
3326
sum = acu + temp;
3321
3327
cbits = acu ^ temp ^ sum;
3322
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
3328
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
3323
3329
break;
3324
3330
3325
3331
case 0xc7: /* RST 0 */
3326
3332
tStates += 11;
3327
CheckBreakWord(SP - 2);
3333
CHECK_BREAK_WORD(SP - 2);
3328
3334
PUSH(PC);
3329
3335
PCQ_ENTRY(PC - 1);
3330
3336
PC = 0;
3332
3338
3333
3339
case 0xc8: /* RET Z */
3334
3340
if (TSTFLAG(Z)) {
3335
CheckBreakWord(SP);
3341
CHECK_BREAK_WORD(SP);
3336
3342
PCQ_ENTRY(PC - 1);
3337
3343
POP(PC);
3338
3344
tStates += 11;
3345
3351
3346
3352
case 0xc9: /* RET */
3347
3353
tStates += 10;
3348
CheckBreakWord(SP);
3354
CHECK_BREAK_WORD(SP);
3349
3355
PCQ_ENTRY(PC - 1);
3350
3356
POP(PC);
3351
3357
break;
3356
3362
break;
3357
3363
3358
3364
case 0xcb: /* CB prefix */
3359
checkCPU8080;
3365
CHECK_CPU_8080;
3360
3366
adr = HL;
3361
switch ((op = GetBYTE(PC)) & 7) {
3367
switch ((op = GET_BYTE(PC)) & 7) {
3362
3368
3363
3369
case 0:
3364
3370
sim_brk_pend[0] = tStateModifier = FALSE;
3365
3371
++PC;
3366
acu = hreg(BC);
3372
acu = HIGH_REGISTER(BC);
3367
3373
tStates += 8;
3368
3374
break;
3369
3375
3370
3376
case 1:
3371
3377
sim_brk_pend[0] = tStateModifier = FALSE;
3372
3378
++PC;
3373
acu = lreg(BC);
3379
acu = LOW_REGISTER(BC);
3374
3380
tStates += 8;
3375
3381
break;
3376
3382
3377
3383
case 2:
3378
3384
sim_brk_pend[0] = tStateModifier = FALSE;
3379
3385
++PC;
3380
acu = hreg(DE);
3386
acu = HIGH_REGISTER(DE);
3381
3387
tStates += 8;
3382
3388
break;
3383
3389
3384
3390
case 3:
3385
3391
sim_brk_pend[0] = tStateModifier = FALSE;
3386
3392
++PC;
3387
acu = lreg(DE);
3393
acu = LOW_REGISTER(DE);
3388
3394
tStates += 8;
3389
3395
break;
3390
3396
3391
3397
case 4:
3392
3398
sim_brk_pend[0] = tStateModifier = FALSE;
3393
3399
++PC;
3394
acu = hreg(HL);
3400
acu = HIGH_REGISTER(HL);
3395
3401
tStates += 8;
3396
3402
break;
3397
3403
3398
3404
case 5:
3399
3405
sim_brk_pend[0] = tStateModifier = FALSE;
3400
3406
++PC;
3401
acu = lreg(HL);
3407
acu = LOW_REGISTER(HL);
3402
3408
tStates += 8;
3403
3409
break;
3404
3410
3405
3411
case 6:
3406
CheckBreakByte(adr);
3412
CHECK_BREAK_BYTE(adr);
3407
3413
++PC;
3408
acu = GetBYTE(adr);
3414
acu = GET_BYTE(adr);
3409
3415
tStateModifier = TRUE;
3410
3416
tStates += 15;
3411
3417
break;
3413
3419
case 7:
3414
3420
sim_brk_pend[0] = tStateModifier = FALSE;
3415
3421
++PC;
3416
acu = hreg(AF);
3422
acu = HIGH_REGISTER(AF);
3417
3423
tStates += 8;
3418
3424
break;
3419
3425
}
3493
3499
switch (op & 7) {
3494
3500
3495
3501
case 0:
3496
Sethreg(BC, temp);
3502
SET_HIGH_REGISTER(BC, temp);
3497
3503
break;
3498
3504
3499
3505
case 1:
3500
Setlreg(BC, temp);
3506
SET_LOW_REGISTER(BC, temp);
3501
3507
break;
3502
3508
3503
3509
case 2:
3504
Sethreg(DE, temp);
3510
SET_HIGH_REGISTER(DE, temp);
3505
3511
break;
3506
3512
3507
3513
case 3:
3508
Setlreg(DE, temp);
3514
SET_LOW_REGISTER(DE, temp);
3509
3515
break;
3510
3516
3511
3517
case 4:
3512
Sethreg(HL, temp);
3518
SET_HIGH_REGISTER(HL, temp);
3513
3519
break;
3514
3520
3515
3521
case 5:
3516
Setlreg(HL, temp);
3522
SET_LOW_REGISTER(HL, temp);
3517
3523
break;
3518
3524
3519
3525
case 6:
3521
3527
break;
3522
3528
3523
3529
case 7:
3524
Sethreg(AF, temp);
3530
SET_HIGH_REGISTER(AF, temp);
3525
3531
break;
3526
3532
}
3527
3533
break;
3537
3543
case 0xce: /* ADC A,nn */
3538
3544
tStates += 7;
3539
3545
sim_brk_pend[0] = FALSE;
3540
temp = RAM_pp(PC);
3541
acu = hreg(AF);
3546
temp = RAM_PP(PC);
3547
acu = HIGH_REGISTER(AF);
3542
3548
sum = acu + temp + TSTFLAG(C);
3543
3549
cbits = acu ^ temp ^ sum;
3544
AF = addTable[sum] | cbitsTable[cbits] | (SetPV);
3550
AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);
3545
3551
break;
3546
3552
3547
3553
case 0xcf: /* RST 8 */
3548
3554
tStates += 11;
3549
CheckBreakWord(SP - 2);
3555
CHECK_BREAK_WORD(SP - 2);
3550
3556
PUSH(PC);
3551
3557
PCQ_ENTRY(PC - 1);
3552
3558
PC = 8;
3558
3564
tStates += 5;
3559
3565
}
3560
3566
else {
3561
CheckBreakWord(SP);
3567
CHECK_BREAK_WORD(SP);
3562
3568
PCQ_ENTRY(PC - 1);
3563
3569
POP(PC);
3564
3570
tStates += 11;
3567
3573
3568
3574
case 0xd1: /* POP DE */
3569
3575
tStates += 10;
3570
CheckBreakWord(SP);
3576
CHECK_BREAK_WORD(SP);
3571
3577
POP(DE);
3572
3578
break;
3573
3579
3579
3585
case 0xd3: /* OUT (nn),A */
3580
3586
tStates += 11;
3581
3587
sim_brk_pend[0] = FALSE;
3582
out(RAM_pp(PC), hreg(AF));
3588
out(RAM_PP(PC), HIGH_REGISTER(AF));
3583
3589
break;
3584
3590
3585
3591
case 0xd4: /* CALL NC,nnnn */
3588
3594
3589
3595
case 0xd5: /* PUSH DE */
3590
3596
tStates += 11;
3591
CheckBreakWord(SP - 2);
3597
CHECK_BREAK_WORD(SP - 2);
3592
3598
PUSH(DE);
3593
3599
break;
3594
3600
3595
3601
case 0xd6: /* SUB nn */
3596
3602
tStates += 7;
3597
3603
sim_brk_pend[0] = FALSE;
3598
temp = RAM_pp(PC);
3599
acu = hreg(AF);
3604
temp = RAM_PP(PC);
3605
acu = HIGH_REGISTER(AF);
3600
3606
sum = acu - temp;
3601
3607
cbits = acu ^ temp ^ sum;
3602
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
3608
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
3603
3609
break;
3604
3610
3605
3611
case 0xd7: /* RST 10H */
3606
3612
tStates += 11;
3607
CheckBreakWord(SP - 2);
3613
CHECK_BREAK_WORD(SP - 2);
3608
3614
PUSH(PC);
3609
3615
PCQ_ENTRY(PC - 1);
3610
3616
PC = 0x10;
3612
3618
3613
3619
case 0xd8: /* RET C */
3614
3620
if (TSTFLAG(C)) {
3615
CheckBreakWord(SP);
3621
CHECK_BREAK_WORD(SP);
3616
3622
PCQ_ENTRY(PC - 1);
3617
3623
POP(PC);
3618
3624
tStates += 11;
3626
3632
case 0xd9: /* EXX */
3627
3633
tStates += 4;
3628
3634
sim_brk_pend[0] = FALSE;
3629
checkCPU8080;
3635
CHECK_CPU_8080;
3630
3636
temp = BC;
3631
3637
BC = BC1_S;
3632
3638
BC1_S = temp;
3646
3652
case 0xdb: /* IN A,(nn) */
3647
3653
tStates += 11;
3648
3654
sim_brk_pend[0] = FALSE;
3649
Sethreg(AF, in(RAM_pp(PC)));
3655
SET_HIGH_REGISTER(AF, in(RAM_PP(PC)));
3650
3656
break;
3651
3657
3652
3658
case 0xdc: /* CALL C,nnnn */
3654
3660
break;
3655
3661
3656
3662
case 0xdd: /* DD prefix */
3657
checkCPU8080;
3658
switch (op = RAM_pp(PC)) {
3663
CHECK_CPU_8080;
3664
switch (op = RAM_PP(PC)) {
3659
3665
3660
3666
case 0x09: /* ADD IX,BC */
3661
3667
tStates += 15;
3680
3686
case 0x21: /* LD IX,nnnn */
3681
3687
tStates += 14;
3682
3688
sim_brk_pend[0] = FALSE;
3683
IX = GetWORD(PC);
3689
IX = GET_WORD(PC);
3684
3690
PC += 2;
3685
3691
break;
3686
3692
3687
3693
case 0x22: /* LD (nnnn),IX */
3688
3694
tStates += 20;
3689
temp = GetWORD(PC);
3690
CheckBreakWord(temp);
3695
temp = GET_WORD(PC);
3696
CHECK_BREAK_WORD(temp);
3691
3697
PutWORD(temp, IX);
3692
3698
PC += 2;
3693
3699
break;
3702
3708
tStates += 9;
3703
3709
sim_brk_pend[0] = FALSE;
3704
3710
IX += 0x100;
3705
AF = (AF & ~0xfe) | incZ80Table[hreg(IX)];
3711
AF = (AF & ~0xfe) | incZ80Table[HIGH_REGISTER(IX)];
3706
3712
break;
3707
3713
3708
3714
case 0x25: /* DEC IXH */
3709
3715
tStates += 9;
3710
3716
sim_brk_pend[0] = FALSE;
3711
3717
IX -= 0x100;
3712
AF = (AF & ~0xfe) | decZ80Table[hreg(IX)];
3718
AF = (AF & ~0xfe) | decZ80Table[HIGH_REGISTER(IX)];
3713
3719
break;
3714
3720
3715
3721
case 0x26: /* LD IXH,nn */
3716
3722
tStates += 9;
3717
3723
sim_brk_pend[0] = FALSE;
3718
Sethreg(IX, RAM_pp(PC));
3724
SET_HIGH_REGISTER(IX, RAM_PP(PC));
3719
3725
break;
3720
3726
3721
3727
case 0x29: /* ADD IX,IX */
3729
3735
3730
3736
case 0x2a: /* LD IX,(nnnn) */
3731
3737
tStates += 20;
3732
temp = GetWORD(PC);
3733
CheckBreakWord(temp);
3734
IX = GetWORD(temp);
3738
temp = GET_WORD(PC);
3739
CHECK_BREAK_WORD(temp);
3740
IX = GET_WORD(temp);
3735
3741
PC += 2;
3736
3742
break;
3737
3743
3744
3750
case 0x2c: /* INC IXL */
3745
3751
tStates += 9;
3746
3752
sim_brk_pend[0] = FALSE;
3747
temp = lreg(IX) + 1;
3748
Setlreg(IX, temp);
3753
temp = LOW_REGISTER(IX) + 1;
3754
SET_LOW_REGISTER(IX, temp);
3749
3755
AF = (AF & ~0xfe) | incZ80Table[temp];
3750
3756
break;
3751
3757
3752
3758
case 0x2d: /* DEC IXL */
3753
3759
tStates += 9;
3754
3760
sim_brk_pend[0] = FALSE;
3755
temp = lreg(IX) - 1;
3756
Setlreg(IX, temp);
3761
temp = LOW_REGISTER(IX) - 1;
3762
SET_LOW_REGISTER(IX, temp);
3757
3763
AF = (AF & ~0xfe) | decZ80Table[temp & 0xff];
3758
3764
break;
3759
3765
3760
3766
case 0x2e: /* LD IXL,nn */
3761
3767
tStates += 9;
3762
3768
sim_brk_pend[0] = FALSE;
3763
Setlreg(IX, RAM_pp(PC));
3769
SET_LOW_REGISTER(IX, RAM_PP(PC));
3764
3770
break;
3765
3771
3766
3772
case 0x34: /* INC (IX+dd) */
3767
3773
tStates += 23;
3768
adr = IX + (int8) RAM_pp(PC);
3769
CheckBreakByte(adr);
3770
temp = GetBYTE(adr) + 1;
3774
adr = IX + (int8) RAM_PP(PC);
3775
CHECK_BREAK_BYTE(adr);
3776
temp = GET_BYTE(adr) + 1;
3771
3777
PutBYTE(adr, temp);
3772
3778
AF = (AF & ~0xfe) | incZ80Table[temp];
3773
3779
break;
3774
3780
3775
3781
case 0x35: /* DEC (IX+dd) */
3776
3782
tStates += 23;
3777
adr = IX + (int8) RAM_pp(PC);
3778
CheckBreakByte(adr);
3779
temp = GetBYTE(adr) - 1;
3783
adr = IX + (int8) RAM_PP(PC);
3784
CHECK_BREAK_BYTE(adr);
3785
temp = GET_BYTE(adr) - 1;
3780
3786
PutBYTE(adr, temp);
3781
3787
AF = (AF & ~0xfe) | decZ80Table[temp & 0xff];
3782
3788
break;
3783
3789
3784
3790
case 0x36: /* LD (IX+dd),nn */
3785
3791
tStates += 19;
3786
adr = IX + (int8) RAM_pp(PC);
3787
CheckBreakByte(adr);
3788
PutBYTE(adr, RAM_pp(PC));
3792
adr = IX + (int8) RAM_PP(PC);
3793
CHECK_BREAK_BYTE(adr);
3794
PutBYTE(adr, RAM_PP(PC));
3789
3795
break;
3790
3796
3791
3797
case 0x39: /* ADD IX,SP */
3801
3807
case 0x44: /* LD B,IXH */
3802
3808
tStates += 9;
3803
3809
sim_brk_pend[0] = FALSE;
3804
Sethreg(BC, hreg(IX));
3810
SET_HIGH_REGISTER(BC, HIGH_REGISTER(IX));
3805
3811
break;
3806
3812
3807
3813
case 0x45: /* LD B,IXL */
3808
3814
tStates += 9;
3809
3815
sim_brk_pend[0] = FALSE;
3810
Sethreg(BC, lreg(IX));
3816
SET_HIGH_REGISTER(BC, LOW_REGISTER(IX));
3811
3817
break;
3812
3818
3813
3819
case 0x46: /* LD B,(IX+dd) */
3814
3820
tStates += 19;
3815
adr = IX + (int8) RAM_pp(PC);
3816
CheckBreakByte(adr);
3817
Sethreg(BC, GetBYTE(adr));
3821
adr = IX + (int8) RAM_PP(PC);
3822
CHECK_BREAK_BYTE(adr);
3823
SET_HIGH_REGISTER(BC, GET_BYTE(adr));
3818
3824
break;
3819
3825
3820
3826
case 0x4c: /* LD C,IXH */
3821
3827
tStates += 9;
3822
3828
sim_brk_pend[0] = FALSE;
3823
Setlreg(BC, hreg(IX));
3829
SET_LOW_REGISTER(BC, HIGH_REGISTER(IX));
3824
3830
break;
3825
3831
3826
3832
case 0x4d: /* LD C,IXL */
3827
3833
tStates += 9;
3828
3834
sim_brk_pend[0] = FALSE;
3829
Setlreg(BC, lreg(IX));
3835
SET_LOW_REGISTER(BC, LOW_REGISTER(IX));
3830
3836
break;
3831
3837
3832
3838
case 0x4e: /* LD C,(IX+dd) */
3833
3839
tStates += 19;
3834
adr = IX + (int8) RAM_pp(PC);
3835
CheckBreakByte(adr);
3836
Setlreg(BC, GetBYTE(adr));
3840
adr = IX + (int8) RAM_PP(PC);
3841
CHECK_BREAK_BYTE(adr);
3842
SET_LOW_REGISTER(BC, GET_BYTE(adr));
3837
3843
break;
3838
3844
3839
3845
case 0x54: /* LD D,IXH */
3840
3846
tStates += 9;
3841
3847
sim_brk_pend[0] = FALSE;
3842
Sethreg(DE, hreg(IX));
3848
SET_HIGH_REGISTER(DE, HIGH_REGISTER(IX));
3843
3849
break;
3844
3850
3845
3851
case 0x55: /* LD D,IXL */
3846
3852
tStates += 9;
3847
3853
sim_brk_pend[0] = FALSE;
3848
Sethreg(DE, lreg(IX));
3854
SET_HIGH_REGISTER(DE, LOW_REGISTER(IX));
3849
3855
break;
3850
3856
3851
3857
case 0x56: /* LD D,(IX+dd) */
3852
3858
tStates += 19;
3853
adr = IX + (int8) RAM_pp(PC);
3854
CheckBreakByte(adr);
3855
Sethreg(DE, GetBYTE(adr));
3859
adr = IX + (int8) RAM_PP(PC);
3860
CHECK_BREAK_BYTE(adr);
3861
SET_HIGH_REGISTER(DE, GET_BYTE(adr));
3856
3862
break;
3857
3863
3858
3864
case 0x5c: /* LD E,IXH */
3859
3865
tStates += 9;
3860
3866
sim_brk_pend[0] = FALSE;
3861
Setlreg(DE, hreg(IX));
3867
SET_LOW_REGISTER(DE, HIGH_REGISTER(IX));
3862
3868
break;
3863
3869
3864
3870
case 0x5d: /* LD E,IXL */
3865
3871
tStates += 9;
3866
3872
sim_brk_pend[0] = FALSE;
3867
Setlreg(DE, lreg(IX));
3873
SET_LOW_REGISTER(DE, LOW_REGISTER(IX));
3868
3874
break;
3869
3875
3870
3876
case 0x5e: /* LD E,(IX+dd) */
3871
3877
tStates += 19;
3872
adr = IX + (int8) RAM_pp(PC);
3873
CheckBreakByte(adr);
3874
Setlreg(DE, GetBYTE(adr));
3878
adr = IX + (int8) RAM_PP(PC);
3879
CHECK_BREAK_BYTE(adr);
3880
SET_LOW_REGISTER(DE, GET_BYTE(adr));
3875
3881
break;
3876
3882
3877
3883
case 0x60: /* LD IXH,B */
3878
3884
tStates += 9;
3879
3885
sim_brk_pend[0] = FALSE;
3880
Sethreg(IX, hreg(BC));
3886
SET_HIGH_REGISTER(IX, HIGH_REGISTER(BC));
3881
3887
break;
3882
3888
3883
3889
case 0x61: /* LD IXH,C */
3884
3890
tStates += 9;
3885
3891
sim_brk_pend[0] = FALSE;
3886
Sethreg(IX, lreg(BC));
3892
SET_HIGH_REGISTER(IX, LOW_REGISTER(BC));
3887
3893
break;
3888
3894
3889
3895
case 0x62: /* LD IXH,D */
3890
3896
tStates += 9;
3891
3897
sim_brk_pend[0] = FALSE;
3892
Sethreg(IX, hreg(DE));
3898
SET_HIGH_REGISTER(IX, HIGH_REGISTER(DE));
3893
3899
break;
3894
3900
3895
3901
case 0x63: /* LD IXH,E */
3896
3902
tStates += 9;
3897
3903
sim_brk_pend[0] = FALSE;
3898
Sethreg(IX, lreg(DE));
3904
SET_HIGH_REGISTER(IX, LOW_REGISTER(DE));
3899
3905
break;
3900
3906
3901
3907
case 0x64: /* LD IXH,IXH */
3906
3912
case 0x65: /* LD IXH,IXL */
3907
3913
tStates += 9;
3908
3914
sim_brk_pend[0] = FALSE;
3909
Sethreg(IX, lreg(IX));
3915
SET_HIGH_REGISTER(IX, LOW_REGISTER(IX));
3910
3916
break;
3911
3917
3912
3918
case 0x66: /* LD H,(IX+dd) */
3913
3919
tStates += 19;
3914
adr = IX + (int8) RAM_pp(PC);
3915
CheckBreakByte(adr);
3916
Sethreg(HL, GetBYTE(adr));
3920
adr = IX + (int8) RAM_PP(PC);
3921
CHECK_BREAK_BYTE(adr);
3922
SET_HIGH_REGISTER(HL, GET_BYTE(adr));
3917
3923
break;
3918
3924
3919
3925
case 0x67: /* LD IXH,A */
3920
3926
tStates += 9;
3921
3927
sim_brk_pend[0] = FALSE;
3922
Sethreg(IX, hreg(AF));
3928
SET_HIGH_REGISTER(IX, HIGH_REGISTER(AF));
3923
3929
break;
3924
3930
3925
3931
case 0x68: /* LD IXL,B */
3926
3932
tStates += 9;
3927
3933
sim_brk_pend[0] = FALSE;
3928
Setlreg(IX, hreg(BC));
3934
SET_LOW_REGISTER(IX, HIGH_REGISTER(BC));
3929
3935
break;
3930
3936
3931
3937
case 0x69: /* LD IXL,C */
3932
3938
tStates += 9;
3933
3939
sim_brk_pend[0] = FALSE;
3934
Setlreg(IX, lreg(BC));
3940
SET_LOW_REGISTER(IX, LOW_REGISTER(BC));
3935
3941
break;
3936
3942
3937
3943
case 0x6a: /* LD IXL,D */
3938
3944
tStates += 9;
3939
3945
sim_brk_pend[0] = FALSE;
3940
Setlreg(IX, hreg(DE));
3946
SET_LOW_REGISTER(IX, HIGH_REGISTER(DE));
3941
3947
break;
3942
3948
3943
3949
case 0x6b: /* LD IXL,E */
3944
3950
tStates += 9;
3945
3951
sim_brk_pend[0] = FALSE;
3946
Setlreg(IX, lreg(DE));
3952
SET_LOW_REGISTER(IX, LOW_REGISTER(DE));
3947
3953
break;
3948
3954
3949
3955
case 0x6c: /* LD IXL,IXH */
3950
3956
tStates += 9;
3951
3957
sim_brk_pend[0] = FALSE;
3952
Setlreg(IX, hreg(IX));
3958
SET_LOW_REGISTER(IX, HIGH_REGISTER(IX));
3953
3959
break;
3954
3960
3955
3961
case 0x6d: /* LD IXL,IXL */
3959
3965
3960
3966
case 0x6e: /* LD L,(IX+dd) */
3961
3967
tStates += 19;
3962
adr = IX + (int8) RAM_pp(PC);
3963
CheckBreakByte(adr);
3964
Setlreg(HL, GetBYTE(adr));
3968
adr = IX + (int8) RAM_PP(PC);
3969
CHECK_BREAK_BYTE(adr);
3970
SET_LOW_REGISTER(HL, GET_BYTE(adr));
3965
3971
break;
3966
3972
3967
3973
case 0x6f: /* LD IXL,A */
3968
3974
tStates += 9;
3969
3975
sim_brk_pend[0] = FALSE;
3970
Setlreg(IX, hreg(AF));
3976
SET_LOW_REGISTER(IX, HIGH_REGISTER(AF));
3971
3977
break;
3972
3978
3973
3979
case 0x70: /* LD (IX+dd),B */
3974
3980
tStates += 19;
3975
adr = IX + (int8) RAM_pp(PC);
3976
CheckBreakByte(adr);
3977
PutBYTE(adr, hreg(BC));
3981
adr = IX + (int8) RAM_PP(PC);
3982
CHECK_BREAK_BYTE(adr);
3983
PutBYTE(adr, HIGH_REGISTER(BC));
3978
3984
break;
3979
3985
3980
3986
case 0x71: /* LD (IX+dd),C */
3981
3987
tStates += 19;
3982
adr = IX + (int8) RAM_pp(PC);
3983
CheckBreakByte(adr);
3984
PutBYTE(adr, lreg(BC));
3988
adr = IX + (int8) RAM_PP(PC);
3989
CHECK_BREAK_BYTE(adr);
3990
PutBYTE(adr, LOW_REGISTER(BC));
3985
3991
break;
3986
3992
3987
3993
case 0x72: /* LD (IX+dd),D */
3988
3994
tStates += 19;
3989
adr = IX + (int8) RAM_pp(PC);
3990
CheckBreakByte(adr);
3991
PutBYTE(adr, hreg(DE));
3995
adr = IX + (int8) RAM_PP(PC);
3996
CHECK_BREAK_BYTE(adr);
3997
PutBYTE(adr, HIGH_REGISTER(DE));
3992
3998
break;
3993
3999
3994
4000
case 0x73: /* LD (IX+dd),E */
3995
4001
tStates += 19;
3996
adr = IX + (int8) RAM_pp(PC);
3997
CheckBreakByte(adr);
3998
PutBYTE(adr, lreg(DE));
4002
adr = IX + (int8) RAM_PP(PC);
4003
CHECK_BREAK_BYTE(adr);
4004
PutBYTE(adr, LOW_REGISTER(DE));
3999
4005
break;
4000
4006
4001
4007
case 0x74: /* LD (IX+dd),H */
4002
4008
tStates += 19;
4003
adr = IX + (int8) RAM_pp(PC);
4004
CheckBreakByte(adr);
4005
PutBYTE(adr, hreg(HL));
4009
adr = IX + (int8) RAM_PP(PC);
4010
CHECK_BREAK_BYTE(adr);
4011
PutBYTE(adr, HIGH_REGISTER(HL));
4006
4012
break;
4007
4013
4008
4014
case 0x75: /* LD (IX+dd),L */
4009
4015
tStates += 19;
4010
adr = IX + (int8) RAM_pp(PC);
4011
CheckBreakByte(adr);
4012
PutBYTE(adr, lreg(HL));
4016
adr = IX + (int8) RAM_PP(PC);
4017
CHECK_BREAK_BYTE(adr);
4018
PutBYTE(adr, LOW_REGISTER(HL));
4013
4019
break;
4014
4020
4015
4021
case 0x77: /* LD (IX+dd),A */
4016
4022
tStates += 19;
4017
adr = IX + (int8) RAM_pp(PC);
4018
CheckBreakByte(adr);
4019
PutBYTE(adr, hreg(AF));
4023
adr = IX + (int8) RAM_PP(PC);
4024
CHECK_BREAK_BYTE(adr);
4025
PutBYTE(adr, HIGH_REGISTER(AF));
4020
4026
break;
4021
4027
4022
4028
case 0x7c: /* LD A,IXH */
4023
4029
tStates += 9;
4024
4030
sim_brk_pend[0] = FALSE;
4025
Sethreg(AF, hreg(IX));
4031
SET_HIGH_REGISTER(AF, HIGH_REGISTER(IX));
4026
4032
break;
4027
4033
4028
4034
case 0x7d: /* LD A,IXL */
4029
4035
tStates += 9;
4030
4036
sim_brk_pend[0] = FALSE;
4031
Sethreg(AF, lreg(IX));
4037
SET_HIGH_REGISTER(AF, LOW_REGISTER(IX));
4032
4038
break;
4033
4039
4034
4040
case 0x7e: /* LD A,(IX+dd) */
4035
4041
tStates += 19;
4036
adr = IX + (int8) RAM_pp(PC);
4037
CheckBreakByte(adr);
4038
Sethreg(AF, GetBYTE(adr));
4042
adr = IX + (int8) RAM_PP(PC);
4043
CHECK_BREAK_BYTE(adr);
4044
SET_HIGH_REGISTER(AF, GET_BYTE(adr));
4039
4045
break;
4040
4046
4041
4047
case 0x84: /* ADD A,IXH */
4042
4048
tStates += 9;
4043
4049
sim_brk_pend[0] = FALSE;
4044
temp = hreg(IX);
4045
acu = hreg(AF);
4050
temp = HIGH_REGISTER(IX);
4051
acu = HIGH_REGISTER(AF);
4046
4052
sum = acu + temp;
4047
4053
AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];
4048
4054
break;
4050
4056
case 0x85: /* ADD A,IXL */
4051
4057
tStates += 9;
4052
4058
sim_brk_pend[0] = FALSE;
4053
temp = lreg(IX);
4054
acu = hreg(AF);
4059
temp = LOW_REGISTER(IX);
4060
acu = HIGH_REGISTER(AF);
4055
4061
sum = acu + temp;
4056
4062
AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];
4057
4063
break;
4058
4064
4059
4065
case 0x86: /* ADD A,(IX+dd) */
4060
4066
tStates += 19;
4061
adr = IX + (int8) RAM_pp(PC);
4062
CheckBreakByte(adr);
4063
temp = GetBYTE(adr);
4064
acu = hreg(AF);
4067
adr = IX + (int8) RAM_PP(PC);
4068
CHECK_BREAK_BYTE(adr);
4069
temp = GET_BYTE(adr);
4070
acu = HIGH_REGISTER(AF);
4065
4071
sum = acu + temp;
4066
4072
AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];
4067
4073
break;
4069
4075
case 0x8c: /* ADC A,IXH */
4070
4076
tStates += 9;
4071
4077
sim_brk_pend[0] = FALSE;
4072
temp = hreg(IX);
4073
acu = hreg(AF);
4078
temp = HIGH_REGISTER(IX);
4079
acu = HIGH_REGISTER(AF);
4074
4080
sum = acu + temp + TSTFLAG(C);
4075
4081
AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];
4076
4082
break;
4078
4084
case 0x8d: /* ADC A,IXL */
4079
4085
tStates += 9;
4080
4086
sim_brk_pend[0] = FALSE;
4081
temp = lreg(IX);
4082
acu = hreg(AF);
4087
temp = LOW_REGISTER(IX);
4088
acu = HIGH_REGISTER(AF);
4083
4089
sum = acu + temp + TSTFLAG(C);
4084
4090
AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];
4085
4091
break;
4086
4092
4087
4093
case 0x8e: /* ADC A,(IX+dd) */
4088
4094
tStates += 19;
4089
adr = IX + (int8) RAM_pp(PC);
4090
CheckBreakByte(adr);
4091
temp = GetBYTE(adr);
4092
acu = hreg(AF);
4095
adr = IX + (int8) RAM_PP(PC);
4096
CHECK_BREAK_BYTE(adr);
4097
temp = GET_BYTE(adr);
4098
acu = HIGH_REGISTER(AF);
4093
4099
sum = acu + temp + TSTFLAG(C);
4094
4100
AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];
4095
4101
break;
4096
4102
4097
4103
case 0x96: /* SUB (IX+dd) */
4098
4104
tStates += 19;
4099
adr = IX + (int8) RAM_pp(PC);
4100
CheckBreakByte(adr);
4101
temp = GetBYTE(adr);
4102
acu = hreg(AF);
4105
adr = IX + (int8) RAM_PP(PC);
4106
CHECK_BREAK_BYTE(adr);
4107
temp = GET_BYTE(adr);
4108
acu = HIGH_REGISTER(AF);
4103
4109
sum = acu - temp;
4104
4110
AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];
4105
4111
break;
4110
4116
case 0x9c: /* SBC A,IXH */
4111
4117
tStates += 9;
4112
4118
sim_brk_pend[0] = FALSE;
4113
temp = hreg(IX);
4114
acu = hreg(AF);
4119
temp = HIGH_REGISTER(IX);
4120
acu = HIGH_REGISTER(AF);
4115
4121
sum = acu - temp - TSTFLAG(C);
4116
4122
AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];
4117
4123
break;
4122
4128
case 0x9d: /* SBC A,IXL */
4123
4129
tStates += 9;
4124
4130
sim_brk_pend[0] = FALSE;
4125
temp = lreg(IX);
4126
acu = hreg(AF);
4131
temp = LOW_REGISTER(IX);
4132
acu = HIGH_REGISTER(AF);
4127
4133
sum = acu - temp - TSTFLAG(C);
4128
4134
AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];
4129
4135
break;
4130
4136
4131
4137
case 0x9e: /* SBC A,(IX+dd) */
4132
4138
tStates += 19;
4133
adr = IX + (int8) RAM_pp(PC);
4134
CheckBreakByte(adr);
4135
temp = GetBYTE(adr);
4136
acu = hreg(AF);
4139
adr = IX + (int8) RAM_PP(PC);
4140
CHECK_BREAK_BYTE(adr);
4141
temp = GET_BYTE(adr);
4142
acu = HIGH_REGISTER(AF);
4137
4143
sum = acu - temp - TSTFLAG(C);
4138
4144
AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];
4139
4145
break;
4152
4158
4153
4159
case 0xa6: /* AND (IX+dd) */
4154
4160
tStates += 19;
4155
adr = IX + (int8) RAM_pp(PC);
4156
CheckBreakByte(adr);
4157
AF = andTable[((AF >> 8) & GetBYTE(adr)) & 0xff];
4161
adr = IX + (int8) RAM_PP(PC);
4162
CHECK_BREAK_BYTE(adr);
4163
AF = andTable[((AF >> 8) & GET_BYTE(adr)) & 0xff];
4158
4164
break;
4159
4165
4160
4166
case 0xac: /* XOR IXH */
4171
4177
4172
4178
case 0xae: /* XOR (IX+dd) */
4173
4179
tStates += 19;
4174
adr = IX + (int8) RAM_pp(PC);
4175
CheckBreakByte(adr);
4176
AF = xororTable[((AF >> 8) ^ GetBYTE(adr)) & 0xff];
4180
adr = IX + (int8) RAM_PP(PC);
4181
CHECK_BREAK_BYTE(adr);
4182
AF = xororTable[((AF >> 8) ^ GET_BYTE(adr)) & 0xff];
4177
4183
break;
4178
4184
4179
4185
case 0xb4: /* OR IXH */
4190
4196
4191
4197
case 0xb6: /* OR (IX+dd) */
4192
4198
tStates += 19;
4193
adr = IX + (int8) RAM_pp(PC);
4194
CheckBreakByte(adr);
4195
AF = xororTable[((AF >> 8) | GetBYTE(adr)) & 0xff];
4199
adr = IX + (int8) RAM_PP(PC);
4200
CHECK_BREAK_BYTE(adr);
4201
AF = xororTable[((AF >> 8) | GET_BYTE(adr)) & 0xff];
4196
4202
break;
4197
4203
4198
4204
case 0xbc: /* CP IXH */
4199
4205
tStates += 9;
4200
4206
sim_brk_pend[0] = FALSE;
4201
temp = hreg(IX);
4207
temp = HIGH_REGISTER(IX);
4202
4208
AF = (AF & ~0x28) | (temp & 0x28);
4203
acu = hreg(AF);
4209
acu = HIGH_REGISTER(AF);
4204
4210
sum = acu - temp;
4205
4211
AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |
4206
4212
cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];
4209
4215
case 0xbd: /* CP IXL */
4210
4216
tStates += 9;
4211
4217
sim_brk_pend[0] = FALSE;
4212
temp = lreg(IX);
4218
temp = LOW_REGISTER(IX);
4213
4219
AF = (AF & ~0x28) | (temp & 0x28);
4214
acu = hreg(AF);
4220
acu = HIGH_REGISTER(AF);
4215
4221
sum = acu - temp;
4216
4222
AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |
4217
4223
cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];
4219
4225
4220
4226
case 0xbe: /* CP (IX+dd) */
4221
4227
tStates += 19;
4222
adr = IX + (int8) RAM_pp(PC);
4223
CheckBreakByte(adr);
4224
temp = GetBYTE(adr);
4228
adr = IX + (int8) RAM_PP(PC);
4229
CHECK_BREAK_BYTE(adr);
4230
temp = GET_BYTE(adr);
4225
4231
AF = (AF & ~0x28) | (temp & 0x28);
4226
acu = hreg(AF);
4232
acu = HIGH_REGISTER(AF);
4227
4233
sum = acu - temp;
4228
4234
AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |
4229
4235
cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];
4230
4236
break;
4231
4237
4232
4238
case 0xcb: /* CB prefix */
4233
adr = IX + (int8) RAM_pp(PC);
4234
switch ((op = GetBYTE(PC)) & 7) {
4239
adr = IX + (int8) RAM_PP(PC);
4240
switch ((op = GET_BYTE(PC)) & 7) {
4235
4241
4236
4242
case 0:
4237
4243
sim_brk_pend[0] = FALSE;
4238
4244
++PC;
4239
acu = hreg(BC);
4245
acu = HIGH_REGISTER(BC);
4240
4246
break;
4241
4247
4242
4248
case 1:
4243
4249
sim_brk_pend[0] = FALSE;
4244
4250
++PC;
4245
acu = lreg(BC);
4251
acu = LOW_REGISTER(BC);
4246
4252
break;
4247
4253
4248
4254
case 2:
4249
4255
sim_brk_pend[0] = FALSE;
4250
4256
++PC;
4251
acu = hreg(DE);
4257
acu = HIGH_REGISTER(DE);
4252
4258
break;
4253
4259
4254
4260
case 3:
4255
4261
sim_brk_pend[0] = FALSE;
4256
4262
++PC;
4257
acu = lreg(DE);
4263
acu = LOW_REGISTER(DE);
4258
4264
break;
4259
4265
4260
4266
case 4:
4261
4267
sim_brk_pend[0] = FALSE;
4262
4268
++PC;
4263
acu = hreg(HL);
4269
acu = HIGH_REGISTER(HL);
4264
4270
break;
4265
4271
4266
4272
case 5:
4267
4273
sim_brk_pend[0] = FALSE;
4268
4274
++PC;
4269
acu = lreg(HL);
4275
acu = LOW_REGISTER(HL);
4270
4276
break;
4271
4277
4272
4278
case 6:
4273
CheckBreakByte(adr);
4279
CHECK_BREAK_BYTE(adr);
4274
4280
++PC;
4275
acu = GetBYTE(adr);
4281
acu = GET_BYTE(adr);
4276
4282
break;
4277
4283
4278
4284
case 7:
4279
4285
sim_brk_pend[0] = FALSE;
4280
4286
++PC;
4281
acu = hreg(AF);
4287
acu = HIGH_REGISTER(AF);
4282
4288
break;
4283
4289
}
4284
4290
switch (op & 0xc0) {
4357
4363
switch (op & 7) {
4358
4364
4359
4365
case 0:
4360
Sethreg(BC, temp);
4366
SET_HIGH_REGISTER(BC, temp);
4361
4367
break;
4362
4368
4363
4369
case 1:
4364
Setlreg(BC, temp);
4370
SET_LOW_REGISTER(BC, temp);
4365
4371
break;
4366
4372
4367
4373
case 2:
4368
Sethreg(DE, temp);
4374
SET_HIGH_REGISTER(DE, temp);
4369
4375
break;
4370
4376
4371
4377
case 3:
4372
Setlreg(DE, temp);
4378
SET_LOW_REGISTER(DE, temp);
4373
4379
break;
4374
4380
4375
4381
case 4:
4376
Sethreg(HL, temp);
4382
SET_HIGH_REGISTER(HL, temp);
4377
4383
break;
4378
4384
4379
4385
case 5:
4380
Setlreg(HL, temp);
4386
SET_LOW_REGISTER(HL, temp);
4381
4387
break;
4382
4388
4383
4389
case 6:
4385
4391
break;
4386
4392
4387
4393
case 7:
4388
Sethreg(AF, temp);
4394
SET_HIGH_REGISTER(AF, temp);
4389
4395
break;
4390
4396
}
4391
4397
break;
4392
4398
4393
4399
case 0xe1: /* POP IX */
4394
4400
tStates += 14;
4395
CheckBreakWord(SP);
4401
CHECK_BREAK_WORD(SP);
4396
4402
POP(IX);
4397
4403
break;
4398
4404
4399
4405
case 0xe3: /* EX (SP),IX */
4400
4406
tStates += 23;
4401
CheckBreakWord(SP);
4407
CHECK_BREAK_WORD(SP);
4402
4408
temp = IX;
4403
4409
POP(IX);
4404
4410
PUSH(temp);
4406
4412
4407
4413
case 0xe5: /* PUSH IX */
4408
4414
tStates += 15;
4409
CheckBreakWord(SP - 2);
4415
CHECK_BREAK_WORD(SP - 2);
4410
4416
PUSH(IX);
4411
4417
break;
4412
4418
4425
4431
4426
4432
default: /* ignore DD */
4427
4433
sim_brk_pend[0] = FALSE;
4428
checkCPUZ80;
4434
CHECK_CPU_Z80;
4429
4435
PC--;
4430
4436
}
4431
4437
break;
4433
4439
case 0xde: /* SBC A,nn */
4434
4440
tStates += 7;
4435
4441
sim_brk_pend[0] = FALSE;
4436
temp = RAM_pp(PC);
4437
acu = hreg(AF);
4442
temp = RAM_PP(PC);
4443
acu = HIGH_REGISTER(AF);
4438
4444
sum = acu - temp - TSTFLAG(C);
4439
4445
cbits = acu ^ temp ^ sum;
4440
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPV);
4446
AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);
4441
4447
break;
4442
4448
4443
4449
case 0xdf: /* RST 18H */
4444
4450
tStates += 11;
4445
CheckBreakWord(SP - 2);
4451
CHECK_BREAK_WORD(SP - 2);
4446
4452
PUSH(PC);
4447
4453
PCQ_ENTRY(PC - 1);
4448
4454
PC = 0x18;
4454
4460
tStates += 5;
4455
4461
}
4456
4462
else {
4457
CheckBreakWord(SP);
4463
CHECK_BREAK_WORD(SP);
4458
4464
PCQ_ENTRY(PC - 1);
4459
4465
POP(PC);
4460
4466
tStates += 11;
4463
4469
4464
4470
case 0xe1: /* POP HL */
4465
4471
tStates += 10;
4466
CheckBreakWord(SP);
4472
CHECK_BREAK_WORD(SP);
4467
4473
POP(HL);
4468
4474
break;
4469
4475
4474
4480
4475
4481
case 0xe3: /* EX (SP),HL */
4476
4482
tStates += 19;
4477
CheckBreakWord(SP);
4483
CHECK_BREAK_WORD(SP);
4478
4484
temp = HL;
4479
4485
POP(HL);
4480
4486
PUSH(temp);
4486
4492
4487
4493
case 0xe5: /* PUSH HL */
4488
4494
tStates += 11;
4489
CheckBreakWord(SP - 2);
4495
CHECK_BREAK_WORD(SP - 2);
4490
4496
PUSH(HL);
4491
4497
break;
4492
4498
4493
4499
case 0xe6: /* AND nn */
4494
4500
tStates += 7;
4495
4501
sim_brk_pend[0] = FALSE;
4496
AF = andTable[((AF >> 8) & RAM_pp(PC)) & 0xff];
4502
AF = andTable[((AF >> 8) & RAM_PP(PC)) & 0xff];
4497
4503
break;
4498
4504
4499
4505
case 0xe7: /* RST 20H */
4500
4506
tStates += 11;
4501
CheckBreakWord(SP - 2);
4507
CHECK_BREAK_WORD(SP - 2);
4502
4508
PUSH(PC);
4503
4509
PCQ_ENTRY(PC - 1);
4504
4510
PC = 0x20;
4506
4512
4507
4513
case 0xe8: /* RET PE */
4508
4514
if (TSTFLAG(P)) {
4509
CheckBreakWord(SP);
4515
CHECK_BREAK_WORD(SP);
4510
4516
PCQ_ENTRY(PC - 1);
4511
4517
POP(PC);
4512
4518
tStates += 11;
4542
4548
break;
4543
4549
4544
4550
case 0xed: /* ED prefix */
4545
checkCPU8080;
4546
switch (op = RAM_pp(PC)) {
4551
CHECK_CPU_8080;
4552
switch (op = RAM_PP(PC)) {
4547
4553
4548
4554
case 0x40: /* IN B,(C) */
4549
4555
tStates += 12;
4550
4556
sim_brk_pend[0] = FALSE;
4551
temp = in(lreg(BC));
4552
Sethreg(BC, temp);
4557
temp = in(LOW_REGISTER(BC));
4558
SET_HIGH_REGISTER(BC, temp);
4553
4559
AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];
4554
4560
break;
4555
4561
4556
4562
case 0x41: /* OUT (C),B */
4557
4563
tStates += 12;
4558
4564
sim_brk_pend[0] = FALSE;
4559
out(lreg(BC), hreg(BC));
4565
out(LOW_REGISTER(BC), HIGH_REGISTER(BC));
4560
4566
break;
4561
4567
4562
4568
case 0x42: /* SBC HL,BC */
4572
4578
4573
4579
case 0x43: /* LD (nnnn),BC */
4574
4580
tStates += 20;
4575
temp = GetWORD(PC);
4576
CheckBreakWord(temp);
4581
temp = GET_WORD(PC);
4582
CHECK_BREAK_WORD(temp);
4577
4583
PutWORD(temp, BC);
4578
4584
PC += 2;
4579
4585
break;
4595
4601
case 0x7C: /* NEG, unofficial */
4596
4602
tStates += 8;
4597
4603
sim_brk_pend[0] = FALSE;
4598
temp = hreg(AF);
4604
temp = HIGH_REGISTER(AF);
4599
4605
AF = ((~(AF & 0xff00) + 1) & 0xff00); /* AF = (-(AF & 0xff00) & 0xff00); */
4600
4606
AF |= ((AF >> 8) & 0xa8) | (((AF & 0xff00) == 0) << 6) | negTable[temp];
4601
4607
break;
4615
4621
case 0x7D: /* RETN, unofficial */
4616
4622
tStates += 14;
4617
4623
IFF_S |= IFF_S >> 1;
4618
CheckBreakWord(SP);
4624
CHECK_BREAK_WORD(SP);
4619
4625
PCQ_ENTRY(PC - 2);
4620
4626
POP(PC);
4621
4627
break;
4635
4641
case 0x48: /* IN C,(C) */
4636
4642
tStates += 12;
4637
4643
sim_brk_pend[0] = FALSE;
4638
temp = in(lreg(BC));
4639
Setlreg(BC, temp);
4644
temp = in(LOW_REGISTER(BC));
4645
SET_LOW_REGISTER(BC, temp);
4640
4646
AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];
4641
4647
break;
4642
4648
4643
4649
case 0x49: /* OUT (C),C */
4644
4650
tStates += 12;
4645
4651
sim_brk_pend[0] = FALSE;
4646
out(lreg(BC), lreg(BC));
4652
out(LOW_REGISTER(BC), LOW_REGISTER(BC));
4647
4653
break;
4648
4654
4649
4655
case 0x4a: /* ADC HL,BC */
4659
4665
4660
4666
case 0x4b: /* LD BC,(nnnn) */
4661
4667
tStates += 20;
4662
temp = GetWORD(PC);
4663
CheckBreakWord(temp);
4664
BC = GetWORD(temp);
4668
temp = GET_WORD(PC);
4669
CHECK_BREAK_WORD(temp);
4670
BC = GET_WORD(temp);
4665
4671
PC += 2;
4666
4672
break;
4667
4673
4668
4674
case 0x4d: /* RETI */
4669
4675
tStates += 14;
4670
4676
IFF_S |= IFF_S >> 1;
4671
CheckBreakWord(SP);
4677
CHECK_BREAK_WORD(SP);
4672
4678
PCQ_ENTRY(PC - 2);
4673
4679
POP(PC);
4674
4680
break;
4682
4688
case 0x50: /* IN D,(C) */
4683
4689
tStates += 12;
4684
4690
sim_brk_pend[0] = FALSE;
4685
temp = in(lreg(BC));
4686
Sethreg(DE, temp);
4691
temp = in(LOW_REGISTER(BC));
4692
SET_HIGH_REGISTER(DE, temp);
4687
4693
AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];
4688
4694
break;
4689
4695
4690
4696
case 0x51: /* OUT (C),D */
4691
4697
tStates += 12;
4692
4698
sim_brk_pend[0] = FALSE;
4693
out(lreg(BC), hreg(DE));
4699
out(LOW_REGISTER(BC), HIGH_REGISTER(DE));
4694
4700
break;
4695
4701
4696
4702
case 0x52: /* SBC HL,DE */
4706
4712
4707
4713
case 0x53: /* LD (nnnn),DE */
4708
4714
tStates += 20;
4709
temp = GetWORD(PC);
4710
CheckBreakWord(temp);
4715
temp = GET_WORD(PC);
4716
CHECK_BREAK_WORD(temp);
4711
4717
PutWORD(temp, DE);
4712
4718
PC += 2;
4713
4719
break;
4727
4733
case 0x58: /* IN E,(C) */
4728
4734
tStates += 12;
4729
4735
sim_brk_pend[0] = FALSE;
4730
temp = in(lreg(BC));
4731
Setlreg(DE, temp);
4736
temp = in(LOW_REGISTER(BC));
4737
SET_LOW_REGISTER(DE, temp);
4732
4738
AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];
4733
4739
break;
4734
4740
4735
4741
case 0x59: /* OUT (C),E */
4736
4742
tStates += 12;
4737
4743
sim_brk_pend[0] = FALSE;
4738
out(lreg(BC), lreg(DE));
4744
out(LOW_REGISTER(BC), LOW_REGISTER(DE));
4739
4745
break;
4740
4746
4741
4747
case 0x5a: /* ADC HL,DE */
4751
4757
4752
4758
case 0x5b: /* LD DE,(nnnn) */
4753
4759
tStates += 20;
4754
temp = GetWORD(PC);
4755
CheckBreakWord(temp);
4756
DE = GetWORD(temp);
4760
temp = GET_WORD(PC);
4761
CHECK_BREAK_WORD(temp);
4762
DE = GET_WORD(temp);
4757
4763
PC += 2;
4758
4764
break;
4759
4765
4773
4779
case 0x60: /* IN H,(C) */
4774
4780
tStates += 12;
4775
4781
sim_brk_pend[0] = FALSE;
4776
temp = in(lreg(BC));
4777
Sethreg(HL, temp);
4782
temp = in(LOW_REGISTER(BC));
4783
SET_HIGH_REGISTER(HL, temp);
4778
4784
AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];
4779
4785
break;
4780
4786
4781
4787
case 0x61: /* OUT (C),H */
4782
4788
tStates += 12;
4783
4789
sim_brk_pend[0] = FALSE;
4784
out(lreg(BC), hreg(HL));
4790
out(LOW_REGISTER(BC), HIGH_REGISTER(HL));
4785
4791
break;
4786
4792
4787
4793
case 0x62: /* SBC HL,HL */
4796
4802
4797
4803
case 0x63: /* LD (nnnn),HL */
4798
4804
tStates += 20;
4799
temp = GetWORD(PC);
4800
CheckBreakWord(temp);
4805
temp = GET_WORD(PC);
4806
CHECK_BREAK_WORD(temp);
4801
4807
PutWORD(temp, HL);
4802
4808
PC += 2;
4803
4809
break;
4805
4811
case 0x67: /* RRD */
4806
4812
tStates += 18;
4807
4813
sim_brk_pend[0] = FALSE;
4808
temp = GetBYTE(HL);
4809
acu = hreg(AF);
4810
PutBYTE(HL, hdig(temp) | (ldig(acu) << 4));
4811
AF = rrdrldTable[(acu & 0xf0) | ldig(temp)] | (AF & 1);
4814
temp = GET_BYTE(HL);
4815
acu = HIGH_REGISTER(AF);
4816
PutBYTE(HL, HIGH_DIGIT(temp) | (LOW_DIGIT(acu) << 4));
4817
AF = rrdrldTable[(acu & 0xf0) | LOW_DIGIT(temp)] | (AF & 1);
4812
4818
break;
4813
4819
4814
4820
case 0x68: /* IN L,(C) */
4815
4821
tStates += 12;
4816
4822
sim_brk_pend[0] = FALSE;
4817
temp = in(lreg(BC));
4818
Setlreg(HL, temp);
4823
temp = in(LOW_REGISTER(BC));
4824
SET_LOW_REGISTER(HL, temp);
4819
4825
AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];
4820
4826
break;
4821
4827
4822
4828
case 0x69: /* OUT (C),L */
4823
4829
tStates += 12;
4824
4830
sim_brk_pend[0] = FALSE;
4825
out(lreg(BC), lreg(HL));
4831
out(LOW_REGISTER(BC), LOW_REGISTER(HL));
4826
4832
break;
4827
4833
4828
4834
case 0x6a: /* ADC HL,HL */
4837
4843
4838
4844
case 0x6b: /* LD HL,(nnnn) */
4839
4845
tStates += 20;
4840
temp = GetWORD(PC);
4841
CheckBreakWord(temp);
4842
HL = GetWORD(temp);
4846
temp = GET_WORD(PC);
4847
CHECK_BREAK_WORD(temp);
4848
HL = GET_WORD(temp);
4843
4849
PC += 2;
4844
4850
break;
4845
4851
4846
4852
case 0x6f: /* RLD */
4847
4853
tStates += 18;
4848
4854
sim_brk_pend[0] = FALSE;
4849
temp = GetBYTE(HL);
4850
acu = hreg(AF);
4851
PutBYTE(HL, (ldig(temp) << 4) | ldig(acu));
4852
AF = rrdrldTable[(acu & 0xf0) | hdig(temp)] | (AF & 1);
4855
temp = GET_BYTE(HL);
4856
acu = HIGH_REGISTER(AF);
4857
PutBYTE(HL, (LOW_DIGIT(temp) << 4) | LOW_DIGIT(acu));
4858
AF = rrdrldTable[(acu & 0xf0) | HIGH_DIGIT(temp)] | (AF & 1);
4853
4859
break;
4854
4860
4855
4861
case 0x70: /* IN (C) */
4856
4862
tStates += 12;
4857
4863
sim_brk_pend[0] = FALSE;
4858
temp = in(lreg(BC));
4859
Setlreg(temp, temp);
4864
temp = in(LOW_REGISTER(BC));
4865
SET_LOW_REGISTER(temp, temp);
4860
4866
AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];
4861
4867
break;
4862
4868
4863
4869
case 0x71: /* OUT (C),0 */
4864
4870
tStates += 12;
4865
4871
sim_brk_pend[0] = FALSE;
4866
out(lreg(BC), 0);
4872
out(LOW_REGISTER(BC), 0);
4867
4873
break;
4868
4874
4869
4875
case 0x72: /* SBC HL,SP */
4879
4885
4880
4886
case 0x73: /* LD (nnnn),SP */
4881
4887
tStates += 20;
4882
temp = GetWORD(PC);
4883
CheckBreakWord(temp);
4888
temp = GET_WORD(PC);
4889
CHECK_BREAK_WORD(temp);
4884
4890
PutWORD(temp, SP);
4885
4891
PC += 2;
4886
4892
break;
4888
4894
case 0x78: /* IN A,(C) */
4889
4895
tStates += 12;
4890
4896
sim_brk_pend[0] = FALSE;
4891
temp = in(lreg(BC));
4892
Sethreg(AF, temp);
4897
temp = in(LOW_REGISTER(BC));
4898
SET_HIGH_REGISTER(AF, temp);
4893
4899
AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];
4894
4900
break;
4895
4901
4896
4902
case 0x79: /* OUT (C),A */
4897
4903
tStates += 12;
4898
4904
sim_brk_pend[0] = FALSE;
4899
out(lreg(BC), hreg(AF));
4905
out(LOW_REGISTER(BC), HIGH_REGISTER(AF));
4900
4906
break;
4901
4907
4902
4908
case 0x7a: /* ADC HL,SP */
4912
4918
4913
4919
case 0x7b: /* LD SP,(nnnn) */
4914
4920
tStates += 20;
4915
temp = GetWORD(PC);
4916
CheckBreakWord(temp);
4917
SP = GetWORD(temp);
4921
temp = GET_WORD(PC);
4922
CHECK_BREAK_WORD(temp);
4923
SP = GET_WORD(temp);
4918
4924
PC += 2;
4919
4925
break;
4920
4926
4921
4927
case 0xa0: /* LDI */
4922
4928
tStates += 16;
4923
CheckBreakTwoBytes(HL, DE);
4924
acu = RAM_pp(HL);
4925
PutBYTE_pp(DE, acu);
4926
acu += hreg(AF);
4929
CHECK_BREAK_TWO_BYTES(HL, DE);
4930
acu = RAM_PP(HL);
4931
PUT_BYTE_PP(DE, acu);
4932
acu += HIGH_REGISTER(AF);
4927
4933
AF = (AF & ~0x3e) | (acu & 8) | ((acu & 2) << 4) |
4928
4934
(((--BC & ADDRMASK) != 0) << 2);
4929
4935
break;
4930
4936
4931
4937
case 0xa1: /* CPI */
4932
4938
tStates += 16;
4933
CheckBreakByte(HL);
4934
acu = hreg(AF);
4935
temp = RAM_pp(HL);
4939
CHECK_BREAK_BYTE(HL);
4940
acu = HIGH_REGISTER(AF);
4941
temp = RAM_PP(HL);
4936
4942
sum = acu - temp;
4937
4943
cbits = acu ^ temp ^ sum;
4938
4944
AF = (AF & ~0xfe) | (sum & 0x80) | (!(sum & 0xff) << 6) |
4946
4952
4947
4953
case 0xa2: /* INI */
4948
4954
tStates += 16;
4949
CheckBreakByte(HL);
4950
PutBYTE(HL, in(lreg(BC)));
4955
CHECK_BREAK_BYTE(HL);
4956
PutBYTE(HL, in(LOW_REGISTER(BC)));
4951
4957
++HL;
4952
4958
SETFLAG(N, 1);
4953
4959
SETFLAG(P, (--BC & ADDRMASK) != 0);
4955
4961
4956
4962
case 0xa3: /* OUTI */
4957
4963
tStates += 16;
4958
CheckBreakByte(HL);
4959
out(lreg(BC), GetBYTE(HL));
4964
CHECK_BREAK_BYTE(HL);
4965
out(LOW_REGISTER(BC), GET_BYTE(HL));
4960
4966
++HL;
4961
4967
SETFLAG(N, 1);
4962
Sethreg(BC, lreg(BC) - 1);
4963
SETFLAG(Z, lreg(BC) == 0);
4968
SET_HIGH_REGISTER(BC, LOW_REGISTER(BC) - 1);
4969
SETFLAG(Z, LOW_REGISTER(BC) == 0);
4964
4970
break;
4965
4971
4966
4972
case 0xa8: /* LDD */
4967
4973
tStates += 16;
4968
CheckBreakTwoBytes(HL, DE);
4969
acu = RAM_mm(HL);
4970
PutBYTE_mm(DE, acu);
4971
acu += hreg(AF);
4974
CHECK_BREAK_TWO_BYTES(HL, DE);
4975
acu = RAM_MM(HL);
4976
PUT_BYTE_MM(DE, acu);
4977
acu += HIGH_REGISTER(AF);
4972
4978
AF = (AF & ~0x3e) | (acu & 8) | ((acu & 2) << 4) |
4973
4979
(((--BC & ADDRMASK) != 0) << 2);
4974
4980
break;
4975
4981
4976
4982
case 0xa9: /* CPD */
4977
4983
tStates += 16;
4978
CheckBreakByte(HL);
4979
acu = hreg(AF);
4980
temp = RAM_mm(HL);
4984
CHECK_BREAK_BYTE(HL);
4985
acu = HIGH_REGISTER(AF);
4986
temp = RAM_MM(HL);
4981
4987
sum = acu - temp;
4982
4988
cbits = acu ^ temp ^ sum;
4983
4989
AF = (AF & ~0xfe) | (sum & 0x80) | (!(sum & 0xff) << 6) |
4991
4997
4992
4998
case 0xaa: /* IND */
4993
4999
tStates += 16;
4994
CheckBreakByte(HL);
4995
PutBYTE(HL, in(lreg(BC)));
5000
CHECK_BREAK_BYTE(HL);
5001
PutBYTE(HL, in(LOW_REGISTER(BC)));
4996
5002
--HL;
4997
5003
SETFLAG(N, 1);
4998
Sethreg(BC, lreg(BC) - 1);
4999
SETFLAG(Z, lreg(BC) == 0);
5004
SET_HIGH_REGISTER(BC, LOW_REGISTER(BC) - 1);
5005
SETFLAG(Z, LOW_REGISTER(BC) == 0);
5000
5006
break;
5001
5007
5002
5008
case 0xab: /* OUTD */
5003
5009
tStates += 16;
5004
CheckBreakByte(HL);
5005
out(lreg(BC), GetBYTE(HL));
5010
CHECK_BREAK_BYTE(HL);
5011
out(LOW_REGISTER(BC), GET_BYTE(HL));
5006
5012
--HL;
5007
5013
SETFLAG(N, 1);
5008
Sethreg(BC, lreg(BC) - 1);
5009
SETFLAG(Z, lreg(BC) == 0);
5014
SET_HIGH_REGISTER(BC, LOW_REGISTER(BC) - 1);
5015
SETFLAG(Z, LOW_REGISTER(BC) == 0);
5010
5016
break;
5011
5017
5012
5018
case 0xb0: /* LDIR */
5013
5019
tStates -= 5;
5014
acu = hreg(AF);
5020
acu = HIGH_REGISTER(AF);
5015
5021
BC &= ADDRMASK;
5016
5022
do {
5017
5023
tStates += 21;
5018
CheckBreakTwoBytes(HL, DE);
5019
acu = RAM_pp(HL);
5020
PutBYTE_pp(DE, acu);
5024
CHECK_BREAK_TWO_BYTES(HL, DE);
5025
acu = RAM_PP(HL);
5026
PUT_BYTE_PP(DE, acu);
5021
5027
} while (--BC);
5022
acu += hreg(AF);
5028
acu += HIGH_REGISTER(AF);
5023
5029
AF = (AF & ~0x3e) | (acu & 8) | ((acu & 2) << 4);
5024
5030
break;
5025
5031
5026
5032
case 0xb1: /* CPIR */
5027
5033
tStates -= 5;
5028
acu = hreg(AF);
5034
acu = HIGH_REGISTER(AF);
5029
5035
BC &= ADDRMASK;
5030
5036
do {
5031
5037
tStates += 21;
5032
CheckBreakByte(HL);
5033
temp = RAM_pp(HL);
5038
CHECK_BREAK_BYTE(HL);
5039
temp = RAM_PP(HL);
5034
5040
op = --BC != 0;
5035
5041
sum = acu - temp;
5036
5042
} while (op && sum != 0);
5046
5052
5047
5053
case 0xb2: /* INIR */
5048
5054
tStates -= 5;
5049
temp = hreg(BC);
5055
temp = HIGH_REGISTER(BC);
5050
5056
do {
5051
5057
tStates += 21;
5052
CheckBreakByte(HL);
5053
PutBYTE(HL, in(lreg(BC)));
5058
CHECK_BREAK_BYTE(HL);
5059
PutBYTE(HL, in(LOW_REGISTER(BC)));
5054
5060
++HL;
5055
5061
} while (--temp);
5056
Sethreg(BC, 0);
5062
SET_HIGH_REGISTER(BC, 0);
5057
5063
SETFLAG(N, 1);
5058
5064
SETFLAG(Z, 1);
5059
5065
break;
5060
5066
5061
5067
case 0xb3: /* OTIR */
5062
5068
tStates -= 5;
5063
temp = hreg(BC);
5069
temp = HIGH_REGISTER(BC);
5064
5070
do {
5065
5071
tStates += 21;
5066
CheckBreakByte(HL);
5067
out(lreg(BC), GetBYTE(HL));
5072
CHECK_BREAK_BYTE(HL);
5073
out(LOW_REGISTER(BC), GET_BYTE(HL));
5068
5074
++HL;
5069
5075
} while (--temp);
5070
Sethreg(BC, 0);
5076
SET_HIGH_REGISTER(BC, 0);
5071
5077
SETFLAG(N, 1);
5072
5078
SETFLAG(Z, 1);
5073
5079
break;
5077
5083
BC &= ADDRMASK;
5078
5084
do {
5079
5085
tStates += 21;
5080
CheckBreakTwoBytes(HL, DE);
5081
acu = RAM_mm(HL);
5082
PutBYTE_mm(DE, acu);
5086
CHECK_BREAK_TWO_BYTES(HL, DE);
5087
acu = RAM_MM(HL);
5088
PUT_BYTE_MM(DE, acu);
5083
5089
} while (--BC);
5084
acu += hreg(AF);
5090
acu += HIGH_REGISTER(AF);
5085
5091
AF = (AF & ~0x3e) | (acu & 8) | ((acu & 2) << 4);
5086
5092
break;
5087
5093
5088
5094
case 0xb9: /* CPDR */
5089
5095
tStates -= 5;
5090
acu = hreg(AF);
5096
acu = HIGH_REGISTER(AF);
5091
5097
BC &= ADDRMASK;
5092
5098
do {
5093
5099
tStates += 21;
5094
CheckBreakByte(HL);
5095
temp = RAM_mm(HL);
5100
CHECK_BREAK_BYTE(HL);
5101
temp = RAM_MM(HL);
5096
5102
op = --BC != 0;
5097
5103
sum = acu - temp;
5098
5104
} while (op && sum != 0);
5108
5114
5109
5115
case 0xba: /* INDR */
5110
5116
tStates -= 5;
5111
temp = hreg(BC);
5117
temp = HIGH_REGISTER(BC);
5112
5118
do {
5113
5119
tStates += 21;
5114
CheckBreakByte(HL);
5115
PutBYTE(HL, in(lreg(BC)));
5120
CHECK_BREAK_BYTE(HL);
5121
PutBYTE(HL, in(LOW_REGISTER(BC)));
5116
5122
--HL;
5117
5123
} while (--temp);
5118
Sethreg(BC, 0);
5124
SET_HIGH_REGISTER(BC, 0);
5119
5125
SETFLAG(N, 1);
5120
5126
SETFLAG(Z, 1);
5121
5127
break;
5122
5128
5123
5129
case 0xbb: /* OTDR */
5124
5130
tStates -= 5;
5125
temp = hreg(BC);
5131
temp = HIGH_REGISTER(BC);
5126
5132
do {
5127
5133
tStates += 21;
5128
CheckBreakByte(HL);
5129
out(lreg(BC), GetBYTE(HL));
5134
CHECK_BREAK_BYTE(HL);
5135
out(LOW_REGISTER(BC), GET_BYTE(HL));
5130
5136
--HL;
5131
5137
} while (--temp);
5132
Sethreg(BC, 0);
5138
SET_HIGH_REGISTER(BC, 0);
5133
5139
SETFLAG(N, 1);
5134
5140
SETFLAG(Z, 1);
5135
5141
break;
5136
5142
5137
5143
default: /* ignore ED and following byte */
5138
5144
sim_brk_pend[0] = FALSE;
5139
checkCPUZ80;
5145
CHECK_CPU_Z80;
5140
5146
}
5141
5147
break;
5142
5148
5143
5149
case 0xee: /* XOR nn */
5144
5150
tStates += 7;
5145
5151
sim_brk_pend[0] = FALSE;
5146
AF = xororTable[((AF >> 8) ^ RAM_pp(PC)) & 0xff];
5152
AF = xororTable[((AF >> 8) ^ RAM_PP(PC)) & 0xff];
5147
5153
break;
5148
5154
5149
5155
case 0xef: /* RST 28H */
5150
5156
tStates += 11;
5151
CheckBreakWord(SP - 2);
5157
CHECK_BREAK_WORD(SP - 2);
5152
5158
PUSH(PC);
5153
5159
PCQ_ENTRY(PC - 1);
5154
5160
PC = 0x28;
5160
5166
tStates += 5;
5161
5167
}
5162
5168
else {
5163
CheckBreakWord(SP);
5169
CHECK_BREAK_WORD(SP);
5164
5170
PCQ_ENTRY(PC - 1);
5165
5171
POP(PC);
5166
5172
tStates += 11;
5169
5175
5170
5176
case 0xf1: /* POP AF */
5171
5177
tStates += 10;
5172
CheckBreakWord(SP);
5178
CHECK_BREAK_WORD(SP);
5173
5179
POP(AF);
5174
5180
break;
5175
5181
5190
5196
5191
5197
case 0xf5: /* PUSH AF */
5192
5198
tStates += 11;
5193
CheckBreakWord(SP - 2);
5199
CHECK_BREAK_WORD(SP - 2);
5194
5200
PUSH(AF);
5195
5201
break;
5196
5202
5197
5203
case 0xf6: /* OR nn */
5198
5204
tStates += 7;
5199
5205
sim_brk_pend[0] = FALSE;
5200
AF = xororTable[((AF >> 8) | RAM_pp(PC)) & 0xff];
5206
AF = xororTable[((AF >> 8) | RAM_PP(PC)) & 0xff];
5201
5207
break;
5202
5208
5203
5209
case 0xf7: /* RST 30H */
5204
5210
tStates += 11;
5205
CheckBreakWord(SP - 2);
5211
CHECK_BREAK_WORD(SP - 2);
5206
5212
PUSH(PC);
5207
5213
PCQ_ENTRY(PC - 1);
5208
5214
PC = 0x30;
5210
5216
5211
5217
case 0xf8: /* RET M */
5212
5218
if (TSTFLAG(S)) {
5213
CheckBreakWord(SP);
5219
CHECK_BREAK_WORD(SP);
5214
5220
PCQ_ENTRY(PC - 1);
5215
5221
POP(PC);
5216
5222
tStates += 11;
5243
5249
break;
5244
5250
5245
5251
case 0xfd: /* FD prefix */
5246
checkCPU8080;
5247
switch (op = RAM_pp(PC)) {
5252
CHECK_CPU_8080;
5253
switch (op = RAM_PP(PC)) {
5248
5254
5249
5255
case 0x09: /* ADD IY,BC */
5250
5256
tStates += 15;
5269
5275
case 0x21: /* LD IY,nnnn */
5270
5276
tStates += 14;
5271
5277
sim_brk_pend[0] = FALSE;
5272
IY = GetWORD(PC);
5278
IY = GET_WORD(PC);
5273
5279
PC += 2;
5274
5280
break;
5275
5281
5276
5282
case 0x22: /* LD (nnnn),IY */
5277
5283
tStates += 20;
5278
temp = GetWORD(PC);
5279
CheckBreakWord(temp);
5284
temp = GET_WORD(PC);
5285
CHECK_BREAK_WORD(temp);
5280
5286
PutWORD(temp, IY);
5281
5287
PC += 2;
5282
5288
break;
5291
5297
tStates += 9;
5292
5298
sim_brk_pend[0] = FALSE;
5293
5299
IY += 0x100;
5294
AF = (AF & ~0xfe) | incZ80Table[hreg(IY)];
5300
AF = (AF & ~0xfe) | incZ80Table[HIGH_REGISTER(IY)];
5295
5301
break;
5296
5302
5297
5303
case 0x25: /* DEC IYH */
5298
5304
tStates += 9;
5299
5305
sim_brk_pend[0] = FALSE;
5300
5306
IY -= 0x100;
5301
AF = (AF & ~0xfe) | decZ80Table[hreg(IY)];
5307
AF = (AF & ~0xfe) | decZ80Table[HIGH_REGISTER(IY)];
5302
5308
break;
5303
5309
5304
5310
case 0x26: /* LD IYH,nn */
5305
5311
tStates += 9;
5306
5312
sim_brk_pend[0] = FALSE;
5307
Sethreg(IY, RAM_pp(PC));
5313
SET_HIGH_REGISTER(IY, RAM_PP(PC));
5308
5314
break;
5309
5315
5310
5316
case 0x29: /* ADD IY,IY */
5318
5324
5319
5325
case 0x2a: /* LD IY,(nnnn) */
5320
5326
tStates += 20;
5321
temp = GetWORD(PC);
5322
CheckBreakWord(temp);
5323
IY = GetWORD(temp);
5327
temp = GET_WORD(PC);
5328
CHECK_BREAK_WORD(temp);
5329
IY = GET_WORD(temp);
5324
5330
PC += 2;
5325
5331
break;
5326
5332
5333
5339
case 0x2c: /* INC IYL */
5334
5340
tStates += 9;
5335
5341
sim_brk_pend[0] = FALSE;
5336
temp = lreg(IY) + 1;
5337
Setlreg(IY, temp);
5342
temp = LOW_REGISTER(IY) + 1;
5343
SET_LOW_REGISTER(IY, temp);
5338
5344
AF = (AF & ~0xfe) | incZ80Table[temp];
5339
5345
break;
5340
5346
5341
5347
case 0x2d: /* DEC IYL */
5342
5348
tStates += 9;
5343
5349
sim_brk_pend[0] = FALSE;
5344
temp = lreg(IY) - 1;
5345
Setlreg(IY, temp);
5350
temp = LOW_REGISTER(IY) - 1;
5351
SET_LOW_REGISTER(IY, temp);
5346
5352
AF = (AF & ~0xfe) | decZ80Table[temp & 0xff];
5347
5353
break;
5348
5354
5349
5355
case 0x2e: /* LD IYL,nn */
5350
5356
tStates += 9;
5351
5357
sim_brk_pend[0] = FALSE;
5352
Setlreg(IY, RAM_pp(PC));
5358
SET_LOW_REGISTER(IY, RAM_PP(PC));
5353
5359
break;
5354
5360
5355
5361
case 0x34: /* INC (IY+dd) */
5356
5362
tStates += 23;
5357
adr = IY + (int8) RAM_pp(PC);
5358
CheckBreakByte(adr);
5359
temp = GetBYTE(adr) + 1;
5363
adr = IY + (int8) RAM_PP(PC);
5364
CHECK_BREAK_BYTE(adr);
5365
temp = GET_BYTE(adr) + 1;
5360
5366
PutBYTE(adr, temp);
5361
5367
AF = (AF & ~0xfe) | incZ80Table[temp];
5362
5368
break;
5363
5369
5364
5370
case 0x35: /* DEC (IY+dd) */
5365
5371
tStates += 23;
5366
adr = IY + (int8) RAM_pp(PC);
5367
CheckBreakByte(adr);
5368
temp = GetBYTE(adr) - 1;
5372
adr = IY + (int8) RAM_PP(PC);
5373
CHECK_BREAK_BYTE(adr);
5374
temp = GET_BYTE(adr) - 1;
5369
5375
PutBYTE(adr, temp);
5370
5376
AF = (AF & ~0xfe) | decZ80Table[temp & 0xff];
5371
5377
break;
5372
5378
5373
5379
case 0x36: /* LD (IY+dd),nn */
5374
5380
tStates += 19;
5375
adr = IY + (int8) RAM_pp(PC);
5376
CheckBreakByte(adr);
5377
PutBYTE(adr, RAM_pp(PC));
5381
adr = IY + (int8) RAM_PP(PC);
5382
CHECK_BREAK_BYTE(adr);
5383
PutBYTE(adr, RAM_PP(PC));
5378
5384
break;
5379
5385
5380
5386
case 0x39: /* ADD IY,SP */
5390
5396
case 0x44: /* LD B,IYH */
5391
5397
tStates += 9;
5392
5398
sim_brk_pend[0] = FALSE;
5393
Sethreg(BC, hreg(IY));
5399
SET_HIGH_REGISTER(BC, HIGH_REGISTER(IY));
5394
5400
break;
5395
5401
5396
5402
case 0x45: /* LD B,IYL */
5397
5403
tStates += 9;
5398
5404
sim_brk_pend[0] = FALSE;
5399
Sethreg(BC, lreg(IY));
5405
SET_HIGH_REGISTER(BC, LOW_REGISTER(IY));
5400
5406
break;
5401
5407
5402
5408
case 0x46: /* LD B,(IY+dd) */
5403
5409
tStates += 19;
5404
adr = IY + (int8) RAM_pp(PC);
5405
CheckBreakByte(adr);
5406
Sethreg(BC, GetBYTE(adr));
5410
adr = IY + (int8) RAM_PP(PC);
5411
CHECK_BREAK_BYTE(adr);
5412
SET_HIGH_REGISTER(BC, GET_BYTE(adr));
5407
5413
break;
5408
5414
5409
5415
case 0x4c: /* LD C,IYH */
5410
5416
tStates += 9;
5411
5417
sim_brk_pend[0] = FALSE;
5412
Setlreg(BC, hreg(IY));
5418
SET_LOW_REGISTER(BC, HIGH_REGISTER(IY));
5413
5419
break;
5414
5420
5415
5421
case 0x4d: /* LD C,IYL */
5416
5422
tStates += 9;
5417
5423
sim_brk_pend[0] = FALSE;
5418
Setlreg(BC, lreg(IY));
5424
SET_LOW_REGISTER(BC, LOW_REGISTER(IY));
5419
5425
break;
5420
5426
5421
5427
case 0x4e: /* LD C,(IY+dd) */
5422
5428
tStates += 19;
5423
adr = IY + (int8) RAM_pp(PC);
5424
CheckBreakByte(adr);
5425
Setlreg(BC, GetBYTE(adr));
5429
adr = IY + (int8) RAM_PP(PC);
5430
CHECK_BREAK_BYTE(adr);
5431
SET_LOW_REGISTER(BC, GET_BYTE(adr));
5426
5432
break;
5427
5433
5428
5434
case 0x54: /* LD D,IYH */
5429
5435
tStates += 9;
5430
5436
sim_brk_pend[0] = FALSE;
5431
Sethreg(DE, hreg(IY));
5437
SET_HIGH_REGISTER(DE, HIGH_REGISTER(IY));
5432
5438
break;
5433
5439
5434
5440
case 0x55: /* LD D,IYL */
5435
5441
tStates += 9;
5436
5442
sim_brk_pend[0] = FALSE;
5437
Sethreg(DE, lreg(IY));
5443
SET_HIGH_REGISTER(DE, LOW_REGISTER(IY));
5438
5444
break;
5439
5445
5440
5446
case 0x56: /* LD D,(IY+dd) */
5441
5447
tStates += 19;
5442
adr = IY + (int8) RAM_pp(PC);
5443
CheckBreakByte(adr);
5444
Sethreg(DE, GetBYTE(adr));
5448
adr = IY + (int8) RAM_PP(PC);
5449
CHECK_BREAK_BYTE(adr);
5450
SET_HIGH_REGISTER(DE, GET_BYTE(adr));
5445
5451
break;
5446
5452
5447
5453
case 0x5c: /* LD E,IYH */
5448
5454
tStates += 9;
5449
5455
sim_brk_pend[0] = FALSE;
5450
Setlreg(DE, hreg(IY));
5456
SET_LOW_REGISTER(DE, HIGH_REGISTER(IY));
5451
5457
break;
5452
5458
5453
5459
case 0x5d: /* LD E,IYL */
5454
5460
tStates += 9;
5455
5461
sim_brk_pend[0] = FALSE;
5456
Setlreg(DE, lreg(IY));
5462
SET_LOW_REGISTER(DE, LOW_REGISTER(IY));
5457
5463
break;
5458
5464
5459
5465
case 0x5e: /* LD E,(IY+dd) */
5460
5466
tStates += 19;
5461
adr = IY + (int8) RAM_pp(PC);
5462
CheckBreakByte(adr);
5463
Setlreg(DE, GetBYTE(adr));
5467
adr = IY + (int8) RAM_PP(PC);
5468
CHECK_BREAK_BYTE(adr);
5469
SET_LOW_REGISTER(DE, GET_BYTE(adr));
5464
5470
break;
5465
5471
5466
5472
case 0x60: /* LD IYH,B */
5467
5473
tStates += 9;
5468
5474
sim_brk_pend[0] = FALSE;
5469
Sethreg(IY, hreg(BC));
5475
SET_HIGH_REGISTER(IY, HIGH_REGISTER(BC));
5470
5476
break;
5471
5477
5472
5478
case 0x61: /* LD IYH,C */
5473
5479
tStates += 9;
5474
5480
sim_brk_pend[0] = FALSE;
5475
Sethreg(IY, lreg(BC));
5481
SET_HIGH_REGISTER(IY, LOW_REGISTER(BC));
5476
5482
break;
5477
5483
5478
5484
case 0x62: /* LD IYH,D */
5479
5485
tStates += 9;
5480
5486
sim_brk_pend[0] = FALSE;
5481
Sethreg(IY, hreg(DE));
5487
SET_HIGH_REGISTER(IY, HIGH_REGISTER(DE));
5482
5488
break;
5483
5489
5484
5490
case 0x63: /* LD IYH,E */
5485
5491
tStates += 9;
5486
5492
sim_brk_pend[0] = FALSE;
5487
Sethreg(IY, lreg(DE));
5493
SET_HIGH_REGISTER(IY, LOW_REGISTER(DE));
5488
5494
break;
5489
5495
5490
5496
case 0x64: /* LD IYH,IYH */
5495
5501
case 0x65: /* LD IYH,IYL */
5496
5502
tStates += 9;
5497
5503
sim_brk_pend[0] = FALSE;
5498
Sethreg(IY, lreg(IY));
5504
SET_HIGH_REGISTER(IY, LOW_REGISTER(IY));
5499
5505
break;
5500
5506
5501
5507
case 0x66: /* LD H,(IY+dd) */
5502
5508
tStates += 19;
5503
adr = IY + (int8) RAM_pp(PC);
5504
CheckBreakByte(adr);
5505
Sethreg(HL, GetBYTE(adr));
5509
adr = IY + (int8) RAM_PP(PC);
5510
CHECK_BREAK_BYTE(adr);
5511
SET_HIGH_REGISTER(HL, GET_BYTE(adr));
5506
5512
break;
5507
5513
5508
5514
case 0x67: /* LD IYH,A */
5509
5515
tStates += 9;
5510
5516
sim_brk_pend[0] = FALSE;
5511
Sethreg(IY, hreg(AF));
5517
SET_HIGH_REGISTER(IY, HIGH_REGISTER(AF));
5512
5518
break;
5513
5519
5514
5520
case 0x68: /* LD IYL,B */
5515
5521
tStates += 9;
5516
5522
sim_brk_pend[0] = FALSE;
5517
Setlreg(IY, hreg(BC));
5523
SET_LOW_REGISTER(IY, HIGH_REGISTER(BC));
5518
5524
break;
5519
5525
5520
5526
case 0x69: /* LD IYL,C */
5521
5527
tStates += 9;
5522
5528
sim_brk_pend[0] = FALSE;
5523
Setlreg(IY, lreg(BC));
5529
SET_LOW_REGISTER(IY, LOW_REGISTER(BC));
5524
5530
break;
5525
5531
5526
5532
case 0x6a: /* LD IYL,D */
5527
5533
tStates += 9;
5528
5534
sim_brk_pend[0] = FALSE;
5529
Setlreg(IY, hreg(DE));
5535
SET_LOW_REGISTER(IY, HIGH_REGISTER(DE));
5530
5536
break;
5531
5537
5532
5538
case 0x6b: /* LD IYL,E */
5533
5539
tStates += 9;
5534
5540
sim_brk_pend[0] = FALSE;
5535
Setlreg(IY, lreg(DE));
5541
SET_LOW_REGISTER(IY, LOW_REGISTER(DE));
5536
5542
break;
5537
5543
5538
5544
case 0x6c: /* LD IYL,IYH */
5539
5545
tStates += 9;
5540
5546
sim_brk_pend[0] = FALSE;
5541
Setlreg(IY, hreg(IY));
5547
SET_LOW_REGISTER(IY, HIGH_REGISTER(IY));
5542
5548
break;
5543
5549
5544
5550
case 0x6d: /* LD IYL,IYL */
5548
5554
5549
5555
case 0x6e: /* LD L,(IY+dd) */
5550
5556
tStates += 19;
5551
adr = IY + (int8) RAM_pp(PC);
5552
CheckBreakByte(adr);
5553
Setlreg(HL, GetBYTE(adr));
5557
adr = IY + (int8) RAM_PP(PC);
5558
CHECK_BREAK_BYTE(adr);
5559
SET_LOW_REGISTER(HL, GET_BYTE(adr));
5554
5560
break;
5555
5561
5556
5562
case 0x6f: /* LD IYL,A */
5557
5563
tStates += 9;
5558
5564
sim_brk_pend[0] = FALSE;
5559
Setlreg(IY, hreg(AF));
5565
SET_LOW_REGISTER(IY, HIGH_REGISTER(AF));
5560
5566
break;
5561
5567
5562
5568
case 0x70: /* LD (IY+dd),B */
5563
5569
tStates += 19;
5564
adr = IY + (int8) RAM_pp(PC);
5565
CheckBreakByte(adr);
5566
PutBYTE(adr, hreg(BC));
5570
adr = IY + (int8) RAM_PP(PC);
5571
CHECK_BREAK_BYTE(adr);
5572
PutBYTE(adr, HIGH_REGISTER(BC));
5567
5573
break;
5568
5574
5569
5575
case 0x71: /* LD (IY+dd),C */
5570
5576
tStates += 19;
5571
adr = IY + (int8) RAM_pp(PC);
5572
CheckBreakByte(adr);
5573
PutBYTE(adr, lreg(BC));
5577
adr = IY + (int8) RAM_PP(PC);
5578
CHECK_BREAK_BYTE(adr);
5579
PutBYTE(adr, LOW_REGISTER(BC));
5574
5580
break;
5575
5581
5576
5582
case 0x72: /* LD (IY+dd),D */
5577
5583
tStates += 19;
5578
adr = IY + (int8) RAM_pp(PC);
5579
CheckBreakByte(adr);
5580
PutBYTE(adr, hreg(DE));
5584
adr = IY + (int8) RAM_PP(PC);
5585
CHECK_BREAK_BYTE(adr);
5586
PutBYTE(adr, HIGH_REGISTER(DE));
5581
5587
break;
5582
5588
5583
5589
case 0x73: /* LD (IY+dd),E */
5584
5590
tStates += 19;
5585
adr = IY + (int8) RAM_pp(PC);
5586
CheckBreakByte(adr);
5587
PutBYTE(adr, lreg(DE));
5591
adr = IY + (int8) RAM_PP(PC);
5592
CHECK_BREAK_BYTE(adr);
5593
PutBYTE(adr, LOW_REGISTER(DE));
5588
5594
break;
5589
5595
5590
5596
case 0x74: /* LD (IY+dd),H */
5591
5597
tStates += 19;
5592
adr = IY + (int8) RAM_pp(PC);
5593
CheckBreakByte(adr);
5594
PutBYTE(adr, hreg(HL));
5598
adr = IY + (int8) RAM_PP(PC);
5599
CHECK_BREAK_BYTE(adr);
5600
PutBYTE(adr, HIGH_REGISTER(HL));
5595
5601
break;
5596
5602
5597
5603
case 0x75: /* LD (IY+dd),L */
5598
5604
tStates += 19;
5599
adr = IY + (int8) RAM_pp(PC);
5600
CheckBreakByte(adr);
5601
PutBYTE(adr, lreg(HL));
5605
adr = IY + (int8) RAM_PP(PC);
5606
CHECK_BREAK_BYTE(adr);
5607
PutBYTE(adr, LOW_REGISTER(HL));
5602
5608
break;
5603
5609
5604
5610
case 0x77: /* LD (IY+dd),A */
5605
5611
tStates += 19;
5606
adr = IY + (int8) RAM_pp(PC);
5607
CheckBreakByte(adr);
5608
PutBYTE(adr, hreg(AF));
5612
adr = IY + (int8) RAM_PP(PC);
5613
CHECK_BREAK_BYTE(adr);
5614
PutBYTE(adr, HIGH_REGISTER(AF));
5609
5615
break;
5610
5616
5611
5617
case 0x7c: /* LD A,IYH */
5612
5618
tStates += 9;
5613
5619
sim_brk_pend[0] = FALSE;
5614
Sethreg(AF, hreg(IY));
5620
SET_HIGH_REGISTER(AF, HIGH_REGISTER(IY));
5615
5621
break;
5616
5622
5617
5623
case 0x7d: /* LD A,IYL */
5618
5624
tStates += 9;
5619
5625
sim_brk_pend[0] = FALSE;
5620
Sethreg(AF, lreg(IY));
5626
SET_HIGH_REGISTER(AF, LOW_REGISTER(IY));
5621
5627
break;
5622
5628
5623
5629
case 0x7e: /* LD A,(IY+dd) */
5624
5630
tStates += 19;
5625
adr = IY + (int8) RAM_pp(PC);
5626
CheckBreakByte(adr);
5627
Sethreg(AF, GetBYTE(adr));
5631
adr = IY + (int8) RAM_PP(PC);
5632
CHECK_BREAK_BYTE(adr);
5633
SET_HIGH_REGISTER(AF, GET_BYTE(adr));
5628
5634
break;
5629
5635
5630
5636
case 0x84: /* ADD A,IYH */
5631
5637
tStates += 9;
5632
5638
sim_brk_pend[0] = FALSE;
5633
temp = hreg(IY);
5634
acu = hreg(AF);
5639
temp = HIGH_REGISTER(IY);
5640
acu = HIGH_REGISTER(AF);
5635
5641
sum = acu + temp;
5636
5642
AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];
5637
5643
break;
5639
5645
case 0x85: /* ADD A,IYL */
5640
5646
tStates += 9;
5641
5647
sim_brk_pend[0] = FALSE;
5642
temp = lreg(IY);
5643
acu = hreg(AF);
5648
temp = LOW_REGISTER(IY);
5649
acu = HIGH_REGISTER(AF);
5644
5650
sum = acu + temp;
5645
5651
AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];
5646
5652
break;
5647
5653
5648
5654
case 0x86: /* ADD A,(IY+dd) */
5649
5655
tStates += 19;
5650
adr = IY + (int8) RAM_pp(PC);
5651
CheckBreakByte(adr);
5652
temp = GetBYTE(adr);
5653
acu = hreg(AF);
5656
adr = IY + (int8) RAM_PP(PC);
5657
CHECK_BREAK_BYTE(adr);
5658
temp = GET_BYTE(adr);
5659
acu = HIGH_REGISTER(AF);
5654
5660
sum = acu + temp;
5655
5661
AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];
5656
5662
break;
5658
5664
case 0x8c: /* ADC A,IYH */
5659
5665
tStates += 9;
5660
5666
sim_brk_pend[0] = FALSE;
5661
temp = hreg(IY);
5662
acu = hreg(AF);
5667
temp = HIGH_REGISTER(IY);
5668
acu = HIGH_REGISTER(AF);
5663
5669
sum = acu + temp + TSTFLAG(C);
5664
5670
AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];
5665
5671
break;
5667
5673
case 0x8d: /* ADC A,IYL */
5668
5674
tStates += 9;
5669
5675
sim_brk_pend[0] = FALSE;
5670
temp = lreg(IY);
5671
acu = hreg(AF);
5676
temp = LOW_REGISTER(IY);
5677
acu = HIGH_REGISTER(AF);
5672
5678
sum = acu + temp + TSTFLAG(C);
5673
5679
AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];
5674
5680
break;
5675
5681
5676
5682
case 0x8e: /* ADC A,(IY+dd) */
5677
5683
tStates += 19;
5678
adr = IY + (int8) RAM_pp(PC);
5679
CheckBreakByte(adr);
5680
temp = GetBYTE(adr);
5681
acu = hreg(AF);
5684
adr = IY + (int8) RAM_PP(PC);
5685
CHECK_BREAK_BYTE(adr);
5686
temp = GET_BYTE(adr);
5687
acu = HIGH_REGISTER(AF);
5682
5688
sum = acu + temp + TSTFLAG(C);
5683
5689
AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];
5684
5690
break;
5685
5691
5686
5692
case 0x96: /* SUB (IY+dd) */
5687
5693
tStates += 19;
5688
adr = IY + (int8) RAM_pp(PC);
5689
CheckBreakByte(adr);
5690
temp = GetBYTE(adr);
5691
acu = hreg(AF);
5694
adr = IY + (int8) RAM_PP(PC);
5695
CHECK_BREAK_BYTE(adr);
5696
temp = GET_BYTE(adr);
5697
acu = HIGH_REGISTER(AF);
5692
5698
sum = acu - temp;
5693
5699
AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];
5694
5700
break;
5699
5705
case 0x9c: /* SBC A,IYH */
5700
5706
tStates += 9;
5701
5707
sim_brk_pend[0] = FALSE;
5702
temp = hreg(IY);
5703
acu = hreg(AF);
5708
temp = HIGH_REGISTER(IY);
5709
acu = HIGH_REGISTER(AF);
5704
5710
sum = acu - temp - TSTFLAG(C);
5705
5711
AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];
5706
5712
break;
5711
5717
case 0x9d: /* SBC A,IYL */
5712
5718
tStates += 9;
5713
5719
sim_brk_pend[0] = FALSE;
5714
temp = lreg(IY);
5715
acu = hreg(AF);
5720
temp = LOW_REGISTER(IY);
5721
acu = HIGH_REGISTER(AF);
5716
5722
sum = acu - temp - TSTFLAG(C);
5717
5723
AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];
5718
5724
break;
5719
5725
5720
5726
case 0x9e: /* SBC A,(IY+dd) */
5721
5727
tStates += 19;
5722
adr = IY + (int8) RAM_pp(PC);
5723
CheckBreakByte(adr);
5724
temp = GetBYTE(adr);
5725
acu = hreg(AF);
5728
adr = IY + (int8) RAM_PP(PC);
5729
CHECK_BREAK_BYTE(adr);
5730
temp = GET_BYTE(adr);
5731
acu = HIGH_REGISTER(AF);
5726
5732
sum = acu - temp - TSTFLAG(C);
5727
5733
AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];
5728
5734
break;
5741
5747
5742
5748
case 0xa6: /* AND (IY+dd) */
5743
5749
tStates += 19;
5744
adr = IY + (int8) RAM_pp(PC);
5745
CheckBreakByte(adr);
5746
AF = andTable[((AF >> 8) & GetBYTE(adr)) & 0xff];
5750
adr = IY + (int8) RAM_PP(PC);
5751
CHECK_BREAK_BYTE(adr);
5752
AF = andTable[((AF >> 8) & GET_BYTE(adr)) & 0xff];
5747
5753
break;
5748
5754
5749
5755
case 0xac: /* XOR IYH */
5760
5766
5761
5767
case 0xae: /* XOR (IY+dd) */
5762
5768
tStates += 19;
5763
adr = IY + (int8) RAM_pp(PC);
5764
CheckBreakByte(adr);
5765
AF = xororTable[((AF >> 8) ^ GetBYTE(adr)) & 0xff];
5769
adr = IY + (int8) RAM_PP(PC);
5770
CHECK_BREAK_BYTE(adr);
5771
AF = xororTable[((AF >> 8) ^ GET_BYTE(adr)) & 0xff];
5766
5772
break;
5767
5773
5768
5774
case 0xb4: /* OR IYH */
5779
5785
5780
5786
case 0xb6: /* OR (IY+dd) */
5781
5787
tStates += 19;
5782
adr = IY + (int8) RAM_pp(PC);
5783
CheckBreakByte(adr);
5784
AF = xororTable[((AF >> 8) | GetBYTE(adr)) & 0xff];
5788
adr = IY + (int8) RAM_PP(PC);
5789
CHECK_BREAK_BYTE(adr);
5790
AF = xororTable[((AF >> 8) | GET_BYTE(adr)) & 0xff];
5785
5791
break;
5786
5792
5787
5793
case 0xbc: /* CP IYH */
5788
5794
tStates += 9;
5789
5795
sim_brk_pend[0] = FALSE;
5790
temp = hreg(IY);
5796
temp = HIGH_REGISTER(IY);
5791
5797
AF = (AF & ~0x28) | (temp & 0x28);
5792
acu = hreg(AF);
5798
acu = HIGH_REGISTER(AF);
5793
5799
sum = acu - temp;
5794
5800
AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |
5795
5801
cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];
5798
5804
case 0xbd: /* CP IYL */
5799
5805
tStates += 9;
5800
5806
sim_brk_pend[0] = FALSE;
5801
temp = lreg(IY);
5807
temp = LOW_REGISTER(IY);
5802
5808
AF = (AF & ~0x28) | (temp & 0x28);
5803
acu = hreg(AF);
5809
acu = HIGH_REGISTER(AF);
5804
5810
sum = acu - temp;
5805
5811
AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |
5806
5812
cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];
5808
5814
5809
5815
case 0xbe: /* CP (IY+dd) */
5810
5816
tStates += 19;
5811
adr = IY + (int8) RAM_pp(PC);
5812
CheckBreakByte(adr);
5813
temp = GetBYTE(adr);
5817
adr = IY + (int8) RAM_PP(PC);
5818
CHECK_BREAK_BYTE(adr);
5819
temp = GET_BYTE(adr);
5814
5820
AF = (AF & ~0x28) | (temp & 0x28);
5815
acu = hreg(AF);
5821
acu = HIGH_REGISTER(AF);
5816
5822
sum = acu - temp;
5817
5823
AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |
5818
5824
cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];
5819
5825
break;
5820
5826
5821
5827
case 0xcb: /* CB prefix */
5822
adr = IY + (int8) RAM_pp(PC);
5823
switch ((op = GetBYTE(PC)) & 7) {
5828
adr = IY + (int8) RAM_PP(PC);
5829
switch ((op = GET_BYTE(PC)) & 7) {
5824
5830
5825
5831
case 0:
5826
5832
sim_brk_pend[0] = FALSE;
5827
5833
++PC;
5828
acu = hreg(BC);
5834
acu = HIGH_REGISTER(BC);
5829
5835
break;
5830
5836
5831
5837
case 1:
5832
5838
sim_brk_pend[0] = FALSE;
5833
5839
++PC;
5834
acu = lreg(BC);
5840
acu = LOW_REGISTER(BC);
5835
5841
break;
5836
5842
5837
5843
case 2:
5838
5844
sim_brk_pend[0] = FALSE;
5839
5845
++PC;
5840
acu = hreg(DE);
5846
acu = HIGH_REGISTER(DE);
5841
5847
break;
5842
5848
5843
5849
case 3:
5844
5850
sim_brk_pend[0] = FALSE;
5845
5851
++PC;
5846
acu = lreg(DE);
5852
acu = LOW_REGISTER(DE);
5847
5853
break;
5848
5854
5849
5855
case 4:
5850
5856
sim_brk_pend[0] = FALSE;
5851
5857
++PC;
5852
acu = hreg(HL);
5858
acu = HIGH_REGISTER(HL);
5853
5859
break;
5854
5860
5855
5861
case 5:
5856
5862
sim_brk_pend[0] = FALSE;
5857
5863
++PC;
5858
acu = lreg(HL);
5864
acu = LOW_REGISTER(HL);
5859
5865
break;
5860
5866
5861
5867
case 6:
5862
CheckBreakByte(adr);
5868
CHECK_BREAK_BYTE(adr);
5863
5869
++PC;
5864
acu = GetBYTE(adr);
5870
acu = GET_BYTE(adr);
5865
5871
break;
5866
5872
5867
5873
case 7:
5868
5874
sim_brk_pend[0] = FALSE;
5869
5875
++PC;
5870
acu = hreg(AF);
5876
acu = HIGH_REGISTER(AF);
5871
5877
break;
5872
5878
}
5873
5879
switch (op & 0xc0) {
5946
5952
switch (op & 7) {
5947
5953
5948
5954
case 0:
5949
Sethreg(BC, temp);
5955
SET_HIGH_REGISTER(BC, temp);
5950
5956
break;
5951
5957
5952
5958
case 1:
5953
Setlreg(BC, temp);
5959
SET_LOW_REGISTER(BC, temp);
5954
5960
break;
5955
5961
5956
5962
case 2:
5957
Sethreg(DE, temp);
5963
SET_HIGH_REGISTER(DE, temp);
5958
5964
break;
5959
5965
5960
5966
case 3:
5961
Setlreg(DE, temp);
5967
SET_LOW_REGISTER(DE, temp);
5962
5968
break;
5963
5969
5964
5970
case 4:
5965
Sethreg(HL, temp);
5971
SET_HIGH_REGISTER(HL, temp);
5966
5972
break;
5967
5973
5968
5974
case 5:
5969
Setlreg(HL, temp);
5975
SET_LOW_REGISTER(HL, temp);
5970
5976
break;
5971
5977
5972
5978
case 6:
5974
5980
break;
5975
5981
5976
5982
case 7:
5977
Sethreg(AF, temp);
5983
SET_HIGH_REGISTER(AF, temp);
5978
5984
break;
5979
5985
}
5980
5986
break;
5981
5987
5982
5988
case 0xe1: /* POP IY */
5983
5989
tStates += 14;
5984
CheckBreakWord(SP);
5990
CHECK_BREAK_WORD(SP);
5985
5991
POP(IY);
5986
5992
break;
5987
5993
5988
5994
case 0xe3: /* EX (SP),IY */
5989
5995
tStates += 23;
5990
CheckBreakWord(SP);
5996
CHECK_BREAK_WORD(SP);
5991
5997
temp = IY;
5992
5998
POP(IY);
5993
5999
PUSH(temp);
5995
6001
5996
6002
case 0xe5: /* PUSH IY */
5997
6003
tStates += 15;
5998
CheckBreakWord(SP - 2);
6004
CHECK_BREAK_WORD(SP - 2);
5999
6005
PUSH(IY);
6000
6006
break;
6001
6007
6014
6020
6015
6021
default: /* ignore FD */
6016
6022
sim_brk_pend[0] = FALSE;
6017
checkCPUZ80;
6023
CHECK_CPU_Z80;
6018
6024
PC--;
6019
6025
}
6020
6026
break;
6022
6028
case 0xfe: /* CP nn */
6023
6029
tStates += 7;
6024
6030
sim_brk_pend[0] = FALSE;
6025
temp = RAM_pp(PC);
6031
temp = RAM_PP(PC);
6026
6032
AF = (AF & ~0x28) | (temp & 0x28);
6027
acu = hreg(AF);
6033
acu = HIGH_REGISTER(AF);
6028
6034
sum = acu - temp;
6029
6035
cbits = acu ^ temp ^ sum;
6030
6036
AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |
6031
(SetPV) | cbits2Table[cbits & 0x1ff];
6037
(SET_PV) | cbits2Table[cbits & 0x1ff];
6032
6038
break;
6033
6039
6034
6040
case 0xff: /* RST 38H */
6035
6041
tStates += 11;
6036
CheckBreakWord(SP - 2);
6042
CHECK_BREAK_WORD(SP - 2);
6037
6043
PUSH(PC);
6038
6044
PCQ_ENTRY(PC - 1);
6039
6045
PC = 0x38;
6128
6134
ROMHigh = temp;
6129
6135
}
6130
6136
if (cpu_unit.flags & UNIT_ALTAIRROM) {
6131
if (defaultROMLow < ROMLow) {
6132
printf("ROMLOW [%04X] reset to %04X since Altair ROM was desired.\n", ROMLow, defaultROMLow);
6133
ROMLow = defaultROMLow;
6137
if (DEFAULT_ROM_LOW < ROMLow) {
6138
printf("ROMLOW [%04X] reset to %04X since Altair ROM was desired.\n", ROMLow, DEFAULT_ROM_LOW);
6139
ROMLow = DEFAULT_ROM_LOW;
6134
6140
}
6135
if (ROMHigh < defaultROMHigh) {
6136
printf("ROMHIGH [%04X] reset to %04X since Altair ROM was desired.\n", ROMHigh, defaultROMHigh);
6137
ROMHigh = defaultROMHigh;
6141
if (ROMHigh < DEFAULT_ROM_HIGH) {
6142
printf("ROMHIGH [%04X] reset to %04X since Altair ROM was desired.\n", ROMHigh, DEFAULT_ROM_HIGH);
6143
ROMHigh = DEFAULT_ROM_HIGH;
6138
6144
}
6139
6145
}
6140
6146
}
6154
6160
6155
6161
static t_stat cpu_set_altairrom(UNIT *uptr, int32 value, char *cptr, void *desc) {
6156
6162
install_bootrom();
6157
if (ROMLow != defaultROMLow) {
6158
printf("\"D ROMLOW %04X\" also executed.\n", defaultROMLow);
6159
ROMLow = defaultROMLow;
6163
if (ROMLow != DEFAULT_ROM_LOW) {
6164
printf("\"D ROMLOW %04X\" also executed.\n", DEFAULT_ROM_LOW);
6165
ROMLow = DEFAULT_ROM_LOW;
6160
6166
}
6161
if (ROMHigh != defaultROMHigh) {
6162
printf("\"D ROMHIGH %04X\" also executed.\n", defaultROMHigh);
6163
ROMHigh = defaultROMHigh;
6167
if (ROMHigh != DEFAULT_ROM_HIGH) {
6168
printf("\"D ROMHIGH %04X\" also executed.\n", DEFAULT_ROM_HIGH);
6169
ROMHigh = DEFAULT_ROM_HIGH;
6164
6170
}
6165
6171
if (!(cpu_unit.flags & UNIT_ROM)) {
6166
6172
printf("\"SET CPU ROM\" also executed.\n");
6177
6183
}
6178
6184
6179
6185
static t_stat cpu_set_banked(UNIT *uptr, int32 value, char *cptr, void *desc) {
6180
if (common > defaultROMLow) {
6186
if (common > DEFAULT_ROM_LOW) {
6181
6187
printf("Warning: COMMON [%04X] must not be greater than %04X. Reset to %04X.\n",
6182
common, defaultROMLow, defaultROMLow);
6183
common = defaultROMLow;
6188
common, DEFAULT_ROM_LOW, DEFAULT_ROM_LOW);
6189
common = DEFAULT_ROM_LOW;
6184
6190
}
6185
6191
if (MEMSIZE != (MAXBANKS * MAXMEMSIZE)) {
6186
6192
previousCapacity = MEMSIZE;
6226
6232
return SCPE_ARG;
6227
6233
}
6228
6234
for (j = lo; j <= hi; j++) {
6229
if (putc(GetBYTE(j), fileref) == EOF) {
6235
if (putc(GET_BYTE(j), fileref) == EOF) {
6230
6236
return SCPE_IOERR;
6231
6237
}
6232
6238
}
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Version: 2.0.1