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Viewing changes to debian/patches/marvell-pj4-core.diff

  • Committer: Package Import Robot
  • Author(s): Matthias Klose
  • Date: 2013-01-20 22:11:07 UTC
  • Revision ID: package-import@ubuntu.com-20130120221107-ef4j9mkxm9vu5dw4
Tags: 20130120-0ubuntu2
Fix build failure on armhf.

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debian/patches/marvell-pj4-core.diff
 
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Index: gcc/config/arm/marvell-pj4.md
 
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===================================================================
 
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--- a/src/gcc/config/arm/marvell-pj4.md (revision 0)
 
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+++ b/src/gcc/config/arm/marvell-pj4.md (revision 0)
 
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@@ -0,0 +1,205 @@
 
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+;; Marvell ARM Processor Pipeline Description
 
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+;; Copyright (C) 2010, 2011, 2012 Free Software Foundation, Inc.
 
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+;; Contributed by Marvell.
 
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+
 
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+;; This file is part of GCC.
 
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+
 
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+;; GCC is free software; you can redistribute it and/or modify it
 
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+;; under the terms of the GNU General Public License as published
 
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+;; by the Free Software Foundation; either version 3, or (at your
 
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+;; option) any later version.
 
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+
 
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+;; GCC is distributed in the hope that it will be useful, but WITHOUT
 
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+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 
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+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
 
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+;; License for more details.
 
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+
 
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+;; You should have received a copy of the GNU General Public License
 
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+;; along with GCC; see the file COPYING3.  If not see
 
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+;; <http://www.gnu.org/licenses/>.
 
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+
 
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+;; Pipeline description for the Marvell PJ4, aka "Flareon".
 
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+(define_automaton "pj4")
 
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+
 
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+;; Issue resources
 
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+(define_cpu_unit    "pj4_is1,pj4_is2"        "pj4")
 
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+(define_reservation "pj4_is"             "(pj4_is1|pj4_is2)")
 
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+(define_reservation "pj4_isb"            "(pj4_is1+pj4_is2)")
 
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+
 
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+;; Functional units
 
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+(define_cpu_unit "pj4_alu1,pj4_alu2,pj4_mul,pj4_div" "pj4")
 
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+
 
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+;; Completion ports
 
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+(define_cpu_unit "pj4_w1,pj4_w2"             "pj4")
 
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+
 
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+;; Complete/Retire control
 
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+(define_cpu_unit    "pj4_c1,pj4_c2"          "pj4")
 
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+(define_reservation "pj4_cp"             "(pj4_c1|pj4_c2)")
 
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+(define_reservation "pj4_cpb"            "(pj4_c1+pj4_c2)")
 
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+
 
45
+;; Integer arithmetic instructions
 
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+
 
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+(define_insn_reservation "pj4_alu_e1" 1
 
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+  (and (eq_attr "tune" "marvell_pj4")
 
49
+       (eq_attr "type" "alu")
 
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+       (not (eq_attr "conds" "set"))
 
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+       (eq_attr "insn" "mov,mvn"))
 
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+                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
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+
 
54
+(define_insn_reservation "pj4_alu_e1_conds" 4
 
55
+  (and (eq_attr "tune" "marvell_pj4")
 
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+       (eq_attr "type" "alu")
 
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+       (eq_attr "conds" "set")
 
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+       (eq_attr "insn" "mov,mvn"))
 
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+                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
60
+
 
61
+(define_insn_reservation "pj4_alu" 1
 
62
+  (and (eq_attr "tune" "marvell_pj4")
 
63
+       (eq_attr "type" "alu")
 
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+       (not (eq_attr "conds" "set"))
 
65
+       (not (eq_attr "insn" "mov,mvn")))
 
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+                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
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+
 
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+(define_insn_reservation "pj4_alu_conds" 4
 
69
+  (and (eq_attr "tune" "marvell_pj4")
 
70
+       (eq_attr "type" "alu")
 
71
+       (eq_attr "conds" "set")
 
72
+       (not (eq_attr "insn" "mov,mvn")))
 
73
+                               "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
74
+
 
75
+(define_insn_reservation "pj4_shift" 1
 
76
+  (and (eq_attr "tune" "marvell_pj4")
 
77
+       (eq_attr "type" "alu_shift,alu_shift_reg")
 
78
+       (not (eq_attr "conds" "set"))
 
79
+       (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
80
+
 
81
+(define_insn_reservation "pj4_shift_conds" 4
 
82
+  (and (eq_attr "tune" "marvell_pj4")
 
83
+       (eq_attr "type" "alu_shift,alu_shift_reg")
 
84
+       (eq_attr "conds" "set")
 
85
+       (eq_attr "shift" "1"))  "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
 
86
+
 
87
+(define_insn_reservation "pj4_alu_shift" 1
 
88
+  (and (eq_attr "tune" "marvell_pj4")
 
89
+       (not (eq_attr "conds" "set"))
 
90
+       (eq_attr "type" "alu_shift,alu_shift_reg"))
 
91
+                               "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
 
92
+
 
93
+(define_insn_reservation "pj4_alu_shift_conds" 4
 
94
+  (and (eq_attr "tune" "marvell_pj4")
 
95
+       (eq_attr "conds" "set")
 
96
+       (eq_attr "type" "alu_shift,alu_shift_reg"))
 
97
+                               "pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
 
98
+
 
99
+(define_bypass 2 "pj4_alu_shift,pj4_shift"
 
100
+                 "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp")
 
101
+
 
102
+(define_insn_reservation "pj4_ir_mul" 3
 
103
+  (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "mult")) "pj4_is,pj4_mul,nothing*2,pj4_cp")
 
104
+
 
105
+(define_insn_reservation "pj4_ir_div" 20
 
106
+  (and (eq_attr "tune" "marvell_pj4") (eq_attr "insn" "udiv,sdiv")) "pj4_is,pj4_div*19,pj4_cp")
 
107
+
 
108
+;; Branches and calls.
 
109
+
 
110
+(define_insn_reservation "pj4_branches" 0
 
111
+  (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "branch")) "pj4_is")
 
112
+
 
113
+(define_insn_reservation "pj4_calls" 32
 
114
+  (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "call")) "pj4_is")
 
115
+
 
116
+;; Load/store instructions
 
117
+
 
118
+(define_insn_reservation "pj4_ldr"  3
 
119
+  (and (eq_attr "tune" "marvell_pj4")
 
120
+       (eq_attr "type" "load_byte,load1"))
 
121
+                       "pj4_is,pj4_alu1,nothing*2,pj4_cp")
 
122
+
 
123
+(define_insn_reservation "pj4_ldrd" 3
 
124
+  (and (eq_attr "tune" "marvell_pj4")
 
125
+       (eq_attr "type" "load2"))
 
126
+                       "pj4_is,pj4_alu1,nothing*2,pj4_cpb")
 
127
+
 
128
+(define_insn_reservation "pj4_str"  1
 
129
+  (and (eq_attr "tune" "marvell_pj4")
 
130
+       (eq_attr "type" "store1"))
 
131
+                       "pj4_is,pj4_alu1,nothing*2,pj4_cp")
 
132
+
 
133
+(define_insn_reservation "pj4_strd" 1
 
134
+  (and (eq_attr "tune" "marvell_pj4")
 
135
+       (eq_attr "type" "store2"))
 
136
+                       "pj4_is,pj4_alu1,nothing*2,pj4_cpb")
 
137
+
 
138
+(define_insn_reservation "pj4_ldm" 4
 
139
+  (and (eq_attr "tune" "marvell_pj4")
 
140
+       (eq_attr "type" "load3,load4")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,nothing,pj4_cp,pj4_cp")
 
141
+
 
142
+(define_insn_reservation "pj4_stm" 2
 
143
+  (and (eq_attr "tune" "marvell_pj4")
 
144
+       (eq_attr "type" "store3,store4")) "pj4_isb,pj4_isb+pj4_alu1,pj4_alu1,nothing,pj4_cp,pj4_cp")
 
145
+
 
146
+;; Loads forward at WR-stage to ALU pipes
 
147
+(define_bypass 2 "pj4_ldr,pj4_ldrd" "pj4_alu")
 
148
+(define_bypass 2 "pj4_ldr,pj4_ldrd" "pj4_alu_shift" "arm_no_early_alu_shift_dep")
 
149
+
 
150
+(define_bypass 4 "pj4_ldr,pj4_ldrd" "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp")
 
151
+(define_bypass 5 "pj4_ldm" "pj4_ir_mul,pj4_ir_div,pj4_core_to_vfp")
 
152
+
 
153
+;; Loads to stores can back-to-back forward
 
154
+(define_bypass 1 "pj4_ldr,pj4_ldrd" "pj4_str,pj4_strd" "arm_no_early_store_addr_dep")
 
155
+
 
156
+;; PJ4 VFP floating point unit
 
157
+(define_automaton "pj4_vfp")
 
158
+
 
159
+(define_cpu_unit "vissue" "pj4_vfp")
 
160
+(define_cpu_unit "vadd"   "pj4_vfp")
 
161
+(define_cpu_unit "vmul"   "pj4_vfp")
 
162
+(define_cpu_unit "vdiv"   "pj4_vfp")
 
163
+(define_cpu_unit "vfast"  "pj4_vfp")
 
164
+
 
165
+(define_insn_reservation "pj4_vfp_add"  5
 
166
+  (and (eq_attr "tune" "marvell_pj4")
 
167
+       (eq_attr "type" "fadds,faddd")) "pj4_is,nothing*2,vissue,vadd,nothing*3")
 
168
+
 
169
+(define_insn_reservation "pj4_vfp_mul"  6
 
170
+  (and (eq_attr "tune" "marvell_pj4")
 
171
+       (eq_attr "type" "fmuls,fmuld")) "pj4_is,nothing*2,vissue,vmul,nothing*4")
 
172
+
 
173
+(define_insn_reservation "pj4_vfp_divs" 20
 
174
+  (and (eq_attr "tune" "marvell_pj4")
 
175
+       (eq_attr "type" "fdivs"))       "pj4_is,nothing*2,vissue,vdiv*18,nothing")
 
176
+
 
177
+(define_insn_reservation "pj4_vfp_divd" 34
 
178
+  (and (eq_attr "tune" "marvell_pj4")
 
179
+       (eq_attr "type" "fdivd"))       "pj4_is,nothing*2,vissue,vdiv*32,nothing")
 
180
+
 
181
+(define_insn_reservation "pj4_vfp_mac"  9
 
182
+  (and (eq_attr "tune" "marvell_pj4")
 
183
+       (eq_attr "type" "fmacs,fmacd"))
 
184
+                       "pj4_is,nothing*2,vissue,vmul,nothing*3,vadd,nothing*3")
 
185
+
 
186
+(define_bypass 5 "pj4_vfp_mac" "pj4_vfp_mac" "arm_no_early_mul_dep")
 
187
+
 
188
+(define_insn_reservation "pj4_vfp_cpy"  4
 
189
+  (and (eq_attr "tune" "marvell_pj4")
 
190
+       (eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,\
 
191
+                        fcmps,fcmpd,f_cvt"))  "pj4_is,nothing*2,vissue,vfast,nothing*2")
 
192
+
 
193
+;; Enlarge latency, and wish that more nondependent insns are
 
194
+;; scheduled immediately after VFP load.
 
195
+(define_insn_reservation "pj4_vfp_load" 4
 
196
+  (and (eq_attr "tune" "marvell_pj4")
 
197
+       (eq_attr "type" "f_loads,f_loadd"))    "pj4_isb,pj4_alu1,nothing,vissue,pj4_cp")
 
198
+
 
199
+(define_insn_reservation "pj4_vfp_store" 1
 
200
+  (and (eq_attr "tune" "marvell_pj4")
 
201
+       (eq_attr "type" "f_stores,f_stored"))  "pj4_isb,pj4_alu1,nothing,vissue,pj4_cp")
 
202
+
 
203
+(define_insn_reservation "pj4_vfp_to_core" 7
 
204
+  (and (eq_attr "tune" "marvell_pj4")
 
205
+       (eq_attr "type" "f_2_r,f_flag"))       "pj4_isb,nothing,nothing,vissue,vfast,nothing*2")
 
206
+
 
207
+(define_insn_reservation "pj4_core_to_vfp" 2
 
208
+  (and (eq_attr "tune" "marvell_pj4")
 
209
+       (eq_attr "type" "r_2_f"))              "pj4_isb,pj4_alu1,pj4_w1,vissue,pj4_cp")
 
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+