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50
by Matthias Klose
* Merge with Debian; remaining changes: |
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# DP: Changes for the Linaro 4.9-2014.09 release (documentation). |
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by Matthias Klose
Package GCC 4.9 snapshot. |
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10.1.15
by Matthias Klose
* Update to SVN 20140724 (r213031) from the gcc-4_9-branch. |
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--- a/src/gcc/doc/extend.texi
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+++ b/src/gcc/doc/extend.texi
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@@ -9109,6 +9109,8 @@
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instructions, but allow the compiler to schedule those calls. |
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||
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@menu |
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+* AArch64 Built-in Functions::
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+* AArch64 intrinsics::
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* Alpha Built-in Functions:: |
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* Altera Nios II Built-in Functions:: |
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* ARC Built-in Functions:: |
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@@ -9116,6 +9118,7 @@
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* ARM iWMMXt Built-in Functions:: |
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* ARM NEON Intrinsics:: |
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* ARM ACLE Intrinsics:: |
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+* ARM Floating Point Status and Control Intrinsics::
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* AVR Built-in Functions:: |
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* Blackfin Built-in Functions:: |
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* FR-V Built-in Functions:: |
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@@ -9141,6 +9144,23 @@
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* TILEPro Built-in Functions:: |
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@end menu |
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||
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+@node AArch64 Built-in Functions
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+@subsection AArch64 Built-in Functions
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+
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+These built-in functions are available for the AArch64 family of
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+processors.
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+@smallexample
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+unsigned int __builtin_aarch64_get_fpcr ()
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+void __builtin_aarch64_set_fpcr (unsigned int)
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+unsigned int __builtin_aarch64_get_fpsr ()
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+void __builtin_aarch64_set_fpsr (unsigned int)
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+@end smallexample
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+
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+@node AArch64 intrinsics
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+@subsection ACLE Intrinsics for AArch64
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+
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+@include aarch64-acle-intrinsics.texi
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+
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@node Alpha Built-in Functions |
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@subsection Alpha Built-in Functions |
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@@ -9917,6 +9937,17 @@
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@include arm-acle-intrinsics.texi |
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+@node ARM Floating Point Status and Control Intrinsics
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+@subsection ARM Floating Point Status and Control Intrinsics
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+
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+These built-in functions are available for the ARM family of
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+processors with floating-point unit.
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+
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+@smallexample
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+unsigned int __builtin_arm_get_fpscr ()
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+void __builtin_arm_set_fpscr (unsigned int)
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+@end smallexample
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+
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@node AVR Built-in Functions |
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@subsection AVR Built-in Functions |
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||
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--- a/src/gcc/doc/aarch64-acle-intrinsics.texi
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+++ b/src/gcc/doc/aarch64-acle-intrinsics.texi
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@@ -0,0 +1,55 @@
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+@c Copyright (C) 2014 Free Software Foundation, Inc.
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+@c This is part of the GCC manual.
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+@c For copying conditions, see the file gcc.texi.
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+
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+@subsubsection CRC32 intrinsics
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+
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+These intrinsics are available when the CRC32 architecture extension is
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+specified, e.g. when the @option{-march=armv8-a+crc} switch is used, or when
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+the target processor specified with @option{-mcpu} supports it.
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+
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+@itemize @bullet
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+@item uint32_t __crc32b (uint32_t, uint8_t)
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+@*@emph{Form of expected instruction(s):} @code{crc32b @var{w0}, @var{w1}, @var{w2}}
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+@end itemize
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+
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+
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+@itemize @bullet
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+@item uint32_t __crc32h (uint32_t, uint16_t)
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+@*@emph{Form of expected instruction(s):} @code{crc32h @var{w0}, @var{w1}, @var{w2}}
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+@end itemize
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+
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+
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+@itemize @bullet
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+@item uint32_t __crc32w (uint32_t, uint32_t)
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+@*@emph{Form of expected instruction(s):} @code{crc32w @var{w0}, @var{w1}, @var{w2}}
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+@end itemize
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+
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+
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+@itemize @bullet
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+@item uint32_t __crc32d (uint32_t, uint64_t)
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+@*@emph{Form of expected instruction(s):} @code{crc32x @var{w0}, @var{w1}, @var{x2}}
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+@end itemize
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+
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+@itemize @bullet
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+@item uint32_t __crc32cb (uint32_t, uint8_t)
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+@*@emph{Form of expected instruction(s):} @code{crc32cb @var{w0}, @var{w1}, @var{w2}}
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+@end itemize
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+
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+
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+@itemize @bullet
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+@item uint32_t __crc32ch (uint32_t, uint16_t)
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+@*@emph{Form of expected instruction(s):} @code{crc32ch @var{w0}, @var{w1}, @var{w2}}
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+@end itemize
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+
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+
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+@itemize @bullet
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+@item uint32_t __crc32cw (uint32_t, uint32_t)
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+@*@emph{Form of expected instruction(s):} @code{crc32cw @var{w0}, @var{w1}, @var{w2}}
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+@end itemize
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+
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+
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+@itemize @bullet
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+@item uint32_t __crc32cd (uint32_t, uint64_t)
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+@*@emph{Form of expected instruction(s):} @code{crc32cx @var{w0}, @var{w1}, @var{x2}}
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+@end itemize
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10.1.23
by Matthias Klose
* Update to SVN 20140830 (r214751) from the gcc-4_9-branch. |
122 |
--- a/src/gcc/doc/md.texi
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+++ b/src/gcc/doc/md.texi
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50
by Matthias Klose
* Merge with Debian; remaining changes: |
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@@ -5319,10 +5319,18 @@
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10.1.23
by Matthias Klose
* Update to SVN 20140830 (r214751) from the gcc-4_9-branch. |
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The @code{ffs} built-in function of C always uses the mode which
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corresponds to the C data type @code{int}.
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||
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+@cindex @code{clrsb@var{m}2} instruction pattern
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+@item @samp{clrsb@var{m}2}
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+Count leading redundant sign bits.
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+Store into operand 0 the number of redundant sign bits in operand 1, starting
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+at the most significant bit position.
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+A redundant sign bit is defined as any sign bit after the first. As such,
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+this count will be one less than the count of leading sign bits.
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+
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@cindex @code{clz@var{m}2} instruction pattern
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@item @samp{clz@var{m}2}
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-Store into operand 0 the number of leading 0-bits in @var{x}, starting
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-at the most significant bit position. If @var{x} is 0, the
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+Store into operand 0 the number of leading 0-bits in operand 1, starting
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+at the most significant bit position. If operand 1 is 0, the
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@code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
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the result is undefined or has a useful value. |
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@var{m} is the mode of operand 0; operand 1's mode is
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50
by Matthias Klose
* Merge with Debian; remaining changes: |
145 |
@@ -5331,8 +5339,8 @@
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10.1.23
by Matthias Klose
* Update to SVN 20140830 (r214751) from the gcc-4_9-branch. |
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@cindex @code{ctz@var{m}2} instruction pattern
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@item @samp{ctz@var{m}2}
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-Store into operand 0 the number of trailing 0-bits in @var{x}, starting
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-at the least significant bit position. If @var{x} is 0, the
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+Store into operand 0 the number of trailing 0-bits in operand 1, starting
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+at the least significant bit position. If operand 1 is 0, the
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@code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
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the result is undefined or has a useful value. |
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@var{m} is the mode of operand 0; operand 1's mode is
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50
by Matthias Klose
* Merge with Debian; remaining changes: |
156 |
@@ -5341,7 +5349,7 @@
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10.1.23
by Matthias Klose
* Update to SVN 20140830 (r214751) from the gcc-4_9-branch. |
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@cindex @code{popcount@var{m}2} instruction pattern
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@item @samp{popcount@var{m}2}
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-Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
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+Store into operand 0 the number of 1-bits in operand 1. @var{m} is the
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mode of operand 0; operand 1's mode is specified by the instruction |
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pattern, and the compiler will convert the operand to that mode before |
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generating the instruction. |
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50
by Matthias Klose
* Merge with Debian; remaining changes: |
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@@ -5348,8 +5356,8 @@
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10.1.23
by Matthias Klose
* Update to SVN 20140830 (r214751) from the gcc-4_9-branch. |
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@cindex @code{parity@var{m}2} instruction pattern
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@item @samp{parity@var{m}2}
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-Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
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-in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
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+Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits
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+in operand 1 modulo 2. @var{m} is the mode of operand 0; operand 1's mode
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is specified by the instruction pattern, and the compiler will convert |
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the operand to that mode before generating the instruction. |
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