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* Copyright (c) 2012 SUSE LINUX Products GmbH
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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#include "qemu-common.h"
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#include "hw/qdev-properties.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#include "hw/arm/arm.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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static void arm_cpu_set_pc(CPUState *cs, vaddr value)
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ARMCPU *cpu = ARM_CPU(cs);
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cpu->env.regs[15] = value;
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static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
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/* Reset a single ARMCPRegInfo register */
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ARMCPRegInfo *ri = value;
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if (ri->type & ARM_CP_SPECIAL) {
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ri->resetfn(&cpu->env, ri);
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/* A zero offset is never possible as it would be regs[0]
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* so we use it to indicate that reset is being handled elsewhere.
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* This is basically only used for fields in non-core coprocessors
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* (like the pxa2xx ones).
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if (!ri->fieldoffset) {
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if (ri->type & ARM_CP_64BIT) {
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CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
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CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
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/* CPUClass::reset() */
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static void arm_cpu_reset(CPUState *s)
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ARMCPU *cpu = ARM_CPU(s);
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
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CPUARMState *env = &cpu->env;
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memset(env, 0, offsetof(CPUARMState, breakpoints));
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g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
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env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
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env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
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env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
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if (arm_feature(env, ARM_FEATURE_AARCH64)) {
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/* 64 bit CPUs always start in 64 bit mode */
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#if defined(CONFIG_USER_ONLY)
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env->uncached_cpsr = ARM_CPU_MODE_USR;
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/* For user mode we must enable access to coprocessors */
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env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
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if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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env->cp15.c15_cpar = 3;
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} else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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env->cp15.c15_cpar = 1;
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/* SVC mode with interrupts disabled. */
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env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
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/* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
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clear at reset. Initial SP and PC are loaded from ROM. */
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env->uncached_cpsr &= ~CPSR_I;
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/* We should really use ldl_phys here, in case the guest
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modified flash and reset itself. However images
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loaded via -kernel have not been copied yet, so load the
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values directly from there. */
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env->regs[13] = ldl_p(rom) & 0xFFFFFFFC;
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env->regs[15] = pc & ~1;
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env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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set_flush_to_zero(1, &env->vfp.standard_fp_status);
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set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
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set_default_nan_mode(1, &env->vfp.standard_fp_status);
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set_float_detect_tininess(float_tininess_before_rounding,
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&env->vfp.fp_status);
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set_float_detect_tininess(float_tininess_before_rounding,
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&env->vfp.standard_fp_status);
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/* Reset is a state change for some CPUARMState fields which we
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* bake assumptions about into translated code, so we need to
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#ifndef CONFIG_USER_ONLY
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static void arm_cpu_set_irq(void *opaque, int irq, int level)
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ARMCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
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cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
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hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
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static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
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ARMCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
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kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
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kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
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hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
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kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
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kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
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static inline void set_feature(CPUARMState *env, int feature)
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env->features |= 1ULL << feature;
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static void arm_cpu_initfn(Object *obj)
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CPUState *cs = CPU(obj);
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ARMCPU *cpu = ARM_CPU(obj);
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cs->env_ptr = &cpu->env;
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cpu_exec_init(&cpu->env);
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cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
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#ifndef CONFIG_USER_ONLY
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/* Our inbound IRQ and FIQ lines */
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qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
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qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
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cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
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arm_gt_ptimer_cb, cpu);
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cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
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arm_gt_vtimer_cb, cpu);
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qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
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ARRAY_SIZE(cpu->gt_timer_outputs));
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/* DTB consumers generally don't in fact care what the 'compatible'
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* string is, so always provide some string and trust that a hypothetical
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* picky DTB consumer will also provide a helpful error message.
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cpu->dtb_compatible = "qemu,unknown";
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if (tcg_enabled() && !inited) {
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arm_translate_init();
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static void arm_cpu_finalizefn(Object *obj)
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ARMCPU *cpu = ARM_CPU(obj);
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g_hash_table_destroy(cpu->cp_regs);
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static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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CPUState *cs = CPU(dev);
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ARMCPU *cpu = ARM_CPU(dev);
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
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CPUARMState *env = &cpu->env;
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/* Some features automatically imply others: */
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if (arm_feature(env, ARM_FEATURE_V8)) {
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set_feature(env, ARM_FEATURE_V7);
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set_feature(env, ARM_FEATURE_ARM_DIV);
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set_feature(env, ARM_FEATURE_LPAE);
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if (arm_feature(env, ARM_FEATURE_V7)) {
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set_feature(env, ARM_FEATURE_VAPA);
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set_feature(env, ARM_FEATURE_THUMB2);
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set_feature(env, ARM_FEATURE_MPIDR);
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_V6K);
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set_feature(env, ARM_FEATURE_V6);
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if (arm_feature(env, ARM_FEATURE_V6K)) {
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set_feature(env, ARM_FEATURE_V6);
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set_feature(env, ARM_FEATURE_MVFR);
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if (arm_feature(env, ARM_FEATURE_V6)) {
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set_feature(env, ARM_FEATURE_V5);
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if (!arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_AUXCR);
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if (arm_feature(env, ARM_FEATURE_V5)) {
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set_feature(env, ARM_FEATURE_V4T);
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if (arm_feature(env, ARM_FEATURE_M)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV);
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if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
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set_feature(env, ARM_FEATURE_THUMB_DIV);
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if (arm_feature(env, ARM_FEATURE_VFP4)) {
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set_feature(env, ARM_FEATURE_VFP3);
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if (arm_feature(env, ARM_FEATURE_VFP3)) {
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set_feature(env, ARM_FEATURE_VFP);
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if (arm_feature(env, ARM_FEATURE_LPAE)) {
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set_feature(env, ARM_FEATURE_V7MP);
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set_feature(env, ARM_FEATURE_PXN);
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register_cp_regs_for_features(cpu);
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arm_cpu_register_gdb_regs_for_features(cpu);
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init_cpreg_list(cpu);
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acc->parent_realize(dev, errp);
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static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
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typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
313
oc = object_class_by_name(typename);
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if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
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object_class_is_abstract(oc)) {
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/* CPU models. These are not needed for the AArch64 linux-user build. */
323
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
325
static void arm926_initfn(Object *obj)
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,arm926";
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
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set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
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cpu->midr = 0x41069265;
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cpu->reset_fpsid = 0x41011090;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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static void arm946_initfn(Object *obj)
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,arm946";
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_MPU);
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
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cpu->midr = 0x41059461;
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cpu->ctr = 0x0f004006;
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cpu->reset_sctlr = 0x00000078;
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static void arm1026_initfn(Object *obj)
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,arm1026";
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set_feature(&cpu->env, ARM_FEATURE_V5);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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set_feature(&cpu->env, ARM_FEATURE_AUXCR);
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
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set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
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cpu->midr = 0x4106a262;
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cpu->reset_fpsid = 0x410110a0;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00090078;
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cpu->reset_auxcr = 1;
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/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
370
ARMCPRegInfo ifar = {
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.name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
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.fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
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define_one_arm_cp_reg(cpu, &ifar);
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static void arm1136_r2_initfn(Object *obj)
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ARMCPU *cpu = ARM_CPU(obj);
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/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
384
* older core than plain "arm1136". In particular this does not
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* have the v6K features.
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* These ID register values are correct for 1136 but may be wrong
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* for 1136_r2 (in particular r0p2 does not actually implement most
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* of the ID registers).
391
cpu->dtb_compatible = "arm,arm1136";
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set_feature(&cpu->env, ARM_FEATURE_V6);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
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set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
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set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
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cpu->midr = 0x4107b362;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->id_isar0 = 0x00140011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11231111;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->reset_auxcr = 7;
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static void arm1136_initfn(Object *obj)
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,arm1136";
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set_feature(&cpu->env, ARM_FEATURE_V6K);
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set_feature(&cpu->env, ARM_FEATURE_V6);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
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set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
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set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
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cpu->midr = 0x4117b363;
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cpu->reset_fpsid = 0x410120b4;
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cpu->mvfr0 = 0x11111111;
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cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->id_isar0 = 0x00140011;
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cpu->id_isar1 = 0x12002111;
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cpu->id_isar2 = 0x11231111;
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cpu->id_isar3 = 0x01102131;
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cpu->id_isar4 = 0x141;
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cpu->reset_auxcr = 7;
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static void arm1176_initfn(Object *obj)
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,arm1176";
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set_feature(&cpu->env, ARM_FEATURE_V6K);
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set_feature(&cpu->env, ARM_FEATURE_VFP);
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set_feature(&cpu->env, ARM_FEATURE_VAPA);
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set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
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set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
460
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
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set_feature(&cpu->env, ARM_FEATURE_TRUSTZONE);
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cpu->midr = 0x410fb767;
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cpu->reset_fpsid = 0x410120b5;
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cpu->mvfr0 = 0x11111111;
465
cpu->mvfr1 = 0x00000000;
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cpu->ctr = 0x1dd20d2;
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cpu->reset_sctlr = 0x00050078;
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cpu->id_pfr0 = 0x111;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222100;
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cpu->id_isar0 = 0x0140011;
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cpu->id_isar1 = 0x12002111;
477
cpu->id_isar2 = 0x11231121;
478
cpu->id_isar3 = 0x01102131;
479
cpu->id_isar4 = 0x01141;
480
cpu->reset_auxcr = 7;
483
static void arm11mpcore_initfn(Object *obj)
485
ARMCPU *cpu = ARM_CPU(obj);
487
cpu->dtb_compatible = "arm,arm11mpcore";
488
set_feature(&cpu->env, ARM_FEATURE_V6K);
489
set_feature(&cpu->env, ARM_FEATURE_VFP);
490
set_feature(&cpu->env, ARM_FEATURE_VAPA);
491
set_feature(&cpu->env, ARM_FEATURE_MPIDR);
492
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
493
cpu->midr = 0x410fb022;
494
cpu->reset_fpsid = 0x410120b4;
495
cpu->mvfr0 = 0x11111111;
496
cpu->mvfr1 = 0x00000000;
497
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
498
cpu->id_pfr0 = 0x111;
502
cpu->id_mmfr0 = 0x01100103;
503
cpu->id_mmfr1 = 0x10020302;
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cpu->id_mmfr2 = 0x01222000;
505
cpu->id_isar0 = 0x00100011;
506
cpu->id_isar1 = 0x12002111;
507
cpu->id_isar2 = 0x11221011;
508
cpu->id_isar3 = 0x01102131;
509
cpu->id_isar4 = 0x141;
510
cpu->reset_auxcr = 1;
513
static void cortex_m3_initfn(Object *obj)
515
ARMCPU *cpu = ARM_CPU(obj);
516
set_feature(&cpu->env, ARM_FEATURE_V7);
517
set_feature(&cpu->env, ARM_FEATURE_M);
518
cpu->midr = 0x410fc231;
521
static void arm_v7m_class_init(ObjectClass *oc, void *data)
523
#ifndef CONFIG_USER_ONLY
524
CPUClass *cc = CPU_CLASS(oc);
526
cc->do_interrupt = arm_v7m_cpu_do_interrupt;
530
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
531
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
532
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
533
{ .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
534
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
538
static void cortex_a8_initfn(Object *obj)
540
ARMCPU *cpu = ARM_CPU(obj);
542
cpu->dtb_compatible = "arm,cortex-a8";
543
set_feature(&cpu->env, ARM_FEATURE_V7);
544
set_feature(&cpu->env, ARM_FEATURE_VFP3);
545
set_feature(&cpu->env, ARM_FEATURE_NEON);
546
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
547
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
548
set_feature(&cpu->env, ARM_FEATURE_TRUSTZONE);
549
cpu->midr = 0x410fc080;
550
cpu->reset_fpsid = 0x410330c0;
551
cpu->mvfr0 = 0x11110222;
552
cpu->mvfr1 = 0x00011100;
553
cpu->ctr = 0x82048004;
554
cpu->reset_sctlr = 0x00c50078;
555
cpu->id_pfr0 = 0x1031;
557
cpu->id_dfr0 = 0x400;
559
cpu->id_mmfr0 = 0x31100003;
560
cpu->id_mmfr1 = 0x20000000;
561
cpu->id_mmfr2 = 0x01202000;
562
cpu->id_mmfr3 = 0x11;
563
cpu->id_isar0 = 0x00101111;
564
cpu->id_isar1 = 0x12112111;
565
cpu->id_isar2 = 0x21232031;
566
cpu->id_isar3 = 0x11112131;
567
cpu->id_isar4 = 0x00111142;
568
cpu->clidr = (1 << 27) | (2 << 24) | 3;
569
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
570
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
571
cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
572
cpu->reset_auxcr = 2;
573
define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
576
static void cortex_a8_r2_initfn(Object *obj)
579
* 1. do we really need this?
580
* 2. are these register values all correct? mostly same as A8 currently
582
ARMCPU *cpu = ARM_CPU(obj);
583
set_feature(&cpu->env, ARM_FEATURE_V7);
584
set_feature(&cpu->env, ARM_FEATURE_VFP3);
585
set_feature(&cpu->env, ARM_FEATURE_NEON);
586
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
587
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
588
set_feature(&cpu->env, ARM_FEATURE_TRUSTZONE);
589
cpu->midr = 0x410fc083;
590
cpu->reset_fpsid = 0x410330c2;
591
cpu->mvfr0 = 0x11110222;
592
cpu->mvfr1 = 0x00011111;
593
cpu->ctr = 0x82048004;
594
cpu->reset_sctlr = 0x00c50078;
595
cpu->id_pfr0 = 0x1031;
597
cpu->id_dfr0 = 0x400;
599
cpu->id_mmfr0 = 0x31100003;
600
cpu->id_mmfr1 = 0x20000000;
601
cpu->id_mmfr2 = 0x01202000;
602
cpu->id_mmfr3 = 0x11;
603
cpu->id_isar0 = 0x00101111;
604
cpu->id_isar1 = 0x12112111;
605
cpu->id_isar2 = 0x21232031;
606
cpu->id_isar3 = 0x11112131;
607
cpu->id_isar4 = 0x00111142;
608
cpu->clidr = (1 << 27) | (2 << 24) | 3;
609
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
610
cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
611
cpu->ccsidr[2] = 0xf03fe03a; /* 256k L2 cache. */
612
cpu->reset_auxcr = 2;
613
define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
616
static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
617
/* power_control should be set to maximum latency. Again,
618
* default to 0 and set by private hook
620
{ .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
621
.access = PL1_RW, .resetvalue = 0,
622
.fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
623
{ .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
624
.access = PL1_RW, .resetvalue = 0,
625
.fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
626
{ .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
627
.access = PL1_RW, .resetvalue = 0,
628
.fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
629
{ .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
630
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
631
/* TLB lockdown control */
632
{ .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
633
.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
634
{ .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
635
.access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
636
{ .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
637
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
638
{ .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
639
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
640
{ .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
641
.access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
645
static void cortex_a9_initfn(Object *obj)
647
ARMCPU *cpu = ARM_CPU(obj);
649
cpu->dtb_compatible = "arm,cortex-a9";
650
set_feature(&cpu->env, ARM_FEATURE_V7);
651
set_feature(&cpu->env, ARM_FEATURE_VFP3);
652
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
653
set_feature(&cpu->env, ARM_FEATURE_NEON);
654
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
655
/* Note that A9 supports the MP extensions even for
656
* A9UP and single-core A9MP (which are both different
657
* and valid configurations; we don't model A9UP).
659
set_feature(&cpu->env, ARM_FEATURE_V7MP);
660
set_feature(&cpu->env, ARM_FEATURE_TRUSTZONE);
661
cpu->midr = 0x410fc090;
662
cpu->reset_fpsid = 0x41033090;
663
cpu->mvfr0 = 0x11110222;
664
cpu->mvfr1 = 0x01111111;
665
cpu->ctr = 0x80038003;
666
cpu->reset_sctlr = 0x00c50078;
667
cpu->id_pfr0 = 0x1031;
669
cpu->id_dfr0 = 0x000;
671
cpu->id_mmfr0 = 0x00100103;
672
cpu->id_mmfr1 = 0x20000000;
673
cpu->id_mmfr2 = 0x01230000;
674
cpu->id_mmfr3 = 0x00002111;
675
cpu->id_isar0 = 0x00101111;
676
cpu->id_isar1 = 0x13112111;
677
cpu->id_isar2 = 0x21232041;
678
cpu->id_isar3 = 0x11112131;
679
cpu->id_isar4 = 0x00111142;
680
cpu->clidr = (1 << 27) | (1 << 24) | 3;
681
cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
682
cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
684
ARMCPRegInfo cbar = {
685
.name = "CBAR", .cp = 15, .crn = 15, .crm = 0, .opc1 = 4,
686
.opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
687
.fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
689
define_one_arm_cp_reg(cpu, &cbar);
690
define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
694
#ifndef CONFIG_USER_ONLY
695
static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
698
/* Linux wants the number of processors from here.
699
* Might as well set the interrupt-controller bit too.
701
*value = ((smp_cpus - 1) << 24) | (1 << 23);
706
static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
707
#ifndef CONFIG_USER_ONLY
708
{ .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
709
.access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
710
.writefn = arm_cp_write_ignore, },
712
{ .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
713
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
717
static void cortex_a15_initfn(Object *obj)
719
ARMCPU *cpu = ARM_CPU(obj);
721
cpu->dtb_compatible = "arm,cortex-a15";
722
set_feature(&cpu->env, ARM_FEATURE_V7);
723
set_feature(&cpu->env, ARM_FEATURE_VFP4);
724
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
725
set_feature(&cpu->env, ARM_FEATURE_NEON);
726
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
727
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
728
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
729
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
730
set_feature(&cpu->env, ARM_FEATURE_LPAE);
731
set_feature(&cpu->env, ARM_FEATURE_TRUSTZONE);
732
cpu->midr = 0x412fc0f1;
733
cpu->reset_fpsid = 0x410430f0;
734
cpu->mvfr0 = 0x10110222;
735
cpu->mvfr1 = 0x11111111;
736
cpu->ctr = 0x8444c004;
737
cpu->reset_sctlr = 0x00c50078;
738
cpu->id_pfr0 = 0x00001131;
739
cpu->id_pfr1 = 0x00011011;
740
cpu->id_dfr0 = 0x02010555;
741
cpu->id_afr0 = 0x00000000;
742
cpu->id_mmfr0 = 0x10201105;
743
cpu->id_mmfr1 = 0x20000000;
744
cpu->id_mmfr2 = 0x01240000;
745
cpu->id_mmfr3 = 0x02102211;
746
cpu->id_isar0 = 0x02101110;
747
cpu->id_isar1 = 0x13112111;
748
cpu->id_isar2 = 0x21232041;
749
cpu->id_isar3 = 0x11112131;
750
cpu->id_isar4 = 0x10011142;
751
cpu->clidr = 0x0a200023;
752
cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
753
cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
754
cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
755
define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
758
static void ti925t_initfn(Object *obj)
760
ARMCPU *cpu = ARM_CPU(obj);
761
set_feature(&cpu->env, ARM_FEATURE_V4T);
762
set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
763
cpu->midr = ARM_CPUID_TI925T;
764
cpu->ctr = 0x5109149;
765
cpu->reset_sctlr = 0x00000070;
768
static void sa1100_initfn(Object *obj)
770
ARMCPU *cpu = ARM_CPU(obj);
772
cpu->dtb_compatible = "intel,sa1100";
773
set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
774
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
775
cpu->midr = 0x4401A11B;
776
cpu->reset_sctlr = 0x00000070;
779
static void sa1110_initfn(Object *obj)
781
ARMCPU *cpu = ARM_CPU(obj);
782
set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
783
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
784
cpu->midr = 0x6901B119;
785
cpu->reset_sctlr = 0x00000070;
788
static void pxa250_initfn(Object *obj)
790
ARMCPU *cpu = ARM_CPU(obj);
792
cpu->dtb_compatible = "marvell,xscale";
793
set_feature(&cpu->env, ARM_FEATURE_V5);
794
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
795
cpu->midr = 0x69052100;
796
cpu->ctr = 0xd172172;
797
cpu->reset_sctlr = 0x00000078;
800
static void pxa255_initfn(Object *obj)
802
ARMCPU *cpu = ARM_CPU(obj);
804
cpu->dtb_compatible = "marvell,xscale";
805
set_feature(&cpu->env, ARM_FEATURE_V5);
806
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
807
cpu->midr = 0x69052d00;
808
cpu->ctr = 0xd172172;
809
cpu->reset_sctlr = 0x00000078;
812
static void pxa260_initfn(Object *obj)
814
ARMCPU *cpu = ARM_CPU(obj);
816
cpu->dtb_compatible = "marvell,xscale";
817
set_feature(&cpu->env, ARM_FEATURE_V5);
818
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
819
cpu->midr = 0x69052903;
820
cpu->ctr = 0xd172172;
821
cpu->reset_sctlr = 0x00000078;
824
static void pxa261_initfn(Object *obj)
826
ARMCPU *cpu = ARM_CPU(obj);
828
cpu->dtb_compatible = "marvell,xscale";
829
set_feature(&cpu->env, ARM_FEATURE_V5);
830
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
831
cpu->midr = 0x69052d05;
832
cpu->ctr = 0xd172172;
833
cpu->reset_sctlr = 0x00000078;
836
static void pxa262_initfn(Object *obj)
838
ARMCPU *cpu = ARM_CPU(obj);
840
cpu->dtb_compatible = "marvell,xscale";
841
set_feature(&cpu->env, ARM_FEATURE_V5);
842
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
843
cpu->midr = 0x69052d06;
844
cpu->ctr = 0xd172172;
845
cpu->reset_sctlr = 0x00000078;
848
static void pxa270a0_initfn(Object *obj)
850
ARMCPU *cpu = ARM_CPU(obj);
852
cpu->dtb_compatible = "marvell,xscale";
853
set_feature(&cpu->env, ARM_FEATURE_V5);
854
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
855
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
856
cpu->midr = 0x69054110;
857
cpu->ctr = 0xd172172;
858
cpu->reset_sctlr = 0x00000078;
861
static void pxa270a1_initfn(Object *obj)
863
ARMCPU *cpu = ARM_CPU(obj);
865
cpu->dtb_compatible = "marvell,xscale";
866
set_feature(&cpu->env, ARM_FEATURE_V5);
867
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
868
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
869
cpu->midr = 0x69054111;
870
cpu->ctr = 0xd172172;
871
cpu->reset_sctlr = 0x00000078;
874
static void pxa270b0_initfn(Object *obj)
876
ARMCPU *cpu = ARM_CPU(obj);
878
cpu->dtb_compatible = "marvell,xscale";
879
set_feature(&cpu->env, ARM_FEATURE_V5);
880
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
881
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
882
cpu->midr = 0x69054112;
883
cpu->ctr = 0xd172172;
884
cpu->reset_sctlr = 0x00000078;
887
static void pxa270b1_initfn(Object *obj)
889
ARMCPU *cpu = ARM_CPU(obj);
891
cpu->dtb_compatible = "marvell,xscale";
892
set_feature(&cpu->env, ARM_FEATURE_V5);
893
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
894
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
895
cpu->midr = 0x69054113;
896
cpu->ctr = 0xd172172;
897
cpu->reset_sctlr = 0x00000078;
900
static void pxa270c0_initfn(Object *obj)
902
ARMCPU *cpu = ARM_CPU(obj);
904
cpu->dtb_compatible = "marvell,xscale";
905
set_feature(&cpu->env, ARM_FEATURE_V5);
906
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
907
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
908
cpu->midr = 0x69054114;
909
cpu->ctr = 0xd172172;
910
cpu->reset_sctlr = 0x00000078;
913
static void pxa270c5_initfn(Object *obj)
915
ARMCPU *cpu = ARM_CPU(obj);
917
cpu->dtb_compatible = "marvell,xscale";
918
set_feature(&cpu->env, ARM_FEATURE_V5);
919
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
920
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
921
cpu->midr = 0x69054117;
922
cpu->ctr = 0xd172172;
923
cpu->reset_sctlr = 0x00000078;
926
#ifdef CONFIG_USER_ONLY
927
static void arm_any_initfn(Object *obj)
929
ARMCPU *cpu = ARM_CPU(obj);
930
set_feature(&cpu->env, ARM_FEATURE_V8);
931
set_feature(&cpu->env, ARM_FEATURE_VFP4);
932
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
933
set_feature(&cpu->env, ARM_FEATURE_NEON);
934
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
935
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
936
set_feature(&cpu->env, ARM_FEATURE_V7MP);
937
#ifdef TARGET_AARCH64
938
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
940
cpu->midr = 0xffffffff;
944
#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
946
typedef struct ARMCPUInfo {
948
void (*initfn)(Object *obj);
949
void (*class_init)(ObjectClass *oc, void *data);
952
static const ARMCPUInfo arm_cpus[] = {
953
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
954
{ .name = "arm926", .initfn = arm926_initfn },
955
{ .name = "arm946", .initfn = arm946_initfn },
956
{ .name = "arm1026", .initfn = arm1026_initfn },
957
/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
958
* older core than plain "arm1136". In particular this does not
959
* have the v6K features.
961
{ .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
962
{ .name = "arm1136", .initfn = arm1136_initfn },
963
{ .name = "arm1176", .initfn = arm1176_initfn },
964
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
965
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
966
.class_init = arm_v7m_class_init },
967
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
968
{ .name = "cortex-a8-r2",.initfn = cortex_a8_r2_initfn },
969
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
970
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
971
{ .name = "ti925t", .initfn = ti925t_initfn },
972
{ .name = "sa1100", .initfn = sa1100_initfn },
973
{ .name = "sa1110", .initfn = sa1110_initfn },
974
{ .name = "pxa250", .initfn = pxa250_initfn },
975
{ .name = "pxa255", .initfn = pxa255_initfn },
976
{ .name = "pxa260", .initfn = pxa260_initfn },
977
{ .name = "pxa261", .initfn = pxa261_initfn },
978
{ .name = "pxa262", .initfn = pxa262_initfn },
979
/* "pxa270" is an alias for "pxa270-a0" */
980
{ .name = "pxa270", .initfn = pxa270a0_initfn },
981
{ .name = "pxa270-a0", .initfn = pxa270a0_initfn },
982
{ .name = "pxa270-a1", .initfn = pxa270a1_initfn },
983
{ .name = "pxa270-b0", .initfn = pxa270b0_initfn },
984
{ .name = "pxa270-b1", .initfn = pxa270b1_initfn },
985
{ .name = "pxa270-c0", .initfn = pxa270c0_initfn },
986
{ .name = "pxa270-c5", .initfn = pxa270c5_initfn },
987
#ifdef CONFIG_USER_ONLY
988
{ .name = "any", .initfn = arm_any_initfn },
993
static Property arm_cpu_properties[] = {
994
DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
995
DEFINE_PROP_END_OF_LIST()
998
static void arm_cpu_class_init(ObjectClass *oc, void *data)
1000
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1001
CPUClass *cc = CPU_CLASS(acc);
1002
DeviceClass *dc = DEVICE_CLASS(oc);
1004
acc->parent_realize = dc->realize;
1005
dc->realize = arm_cpu_realizefn;
1006
dc->props = arm_cpu_properties;
1008
acc->parent_reset = cc->reset;
1009
cc->reset = arm_cpu_reset;
1011
cc->class_by_name = arm_cpu_class_by_name;
1012
cc->do_interrupt = arm_cpu_do_interrupt;
1013
cc->dump_state = arm_cpu_dump_state;
1014
cc->set_pc = arm_cpu_set_pc;
1015
cc->gdb_read_register = arm_cpu_gdb_read_register;
1016
cc->gdb_write_register = arm_cpu_gdb_write_register;
1017
#ifndef CONFIG_USER_ONLY
1018
cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1019
cc->vmsd = &vmstate_arm_cpu;
1021
cc->gdb_num_core_regs = 26;
1022
cc->gdb_core_xml_file = "arm-core.xml";
1025
static void cpu_register(const ARMCPUInfo *info)
1027
TypeInfo type_info = {
1028
.parent = TYPE_ARM_CPU,
1029
.instance_size = sizeof(ARMCPU),
1030
.instance_init = info->initfn,
1031
.class_size = sizeof(ARMCPUClass),
1032
.class_init = info->class_init,
1035
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1036
type_register(&type_info);
1037
g_free((void *)type_info.name);
1040
static const TypeInfo arm_cpu_type_info = {
1041
.name = TYPE_ARM_CPU,
1043
.instance_size = sizeof(ARMCPU),
1044
.instance_init = arm_cpu_initfn,
1045
.instance_finalize = arm_cpu_finalizefn,
1047
.class_size = sizeof(ARMCPUClass),
1048
.class_init = arm_cpu_class_init,
1051
static void arm_cpu_register_types(void)
1055
type_register_static(&arm_cpu_type_info);
1056
for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
1057
cpu_register(&arm_cpus[i]);
1061
type_init(arm_cpu_register_types)