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Viewing changes to fpga/usrp3/top/x300/x300_pcie_int.v

  • Committer: Package Import Robot
  • Author(s): A. Maitland Bottoms
  • Date: 2014-07-01 22:34:32 UTC
  • mfrom: (9.1.11 sid)
  • Revision ID: package-import@ubuntu.com-20140701223432-beg73ip3q8b3lgeg
Tags: 3.7.1-2
* Apply maint branch fixes through release_003_007_001-49-gdf4cf6d
* Fix B2xx udev rules

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fpga/usrp3/top/x300/x300_pcie_int.v
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    //---------------------------------------------------------
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    // Misc
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    //---------------------------------------------------------
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    input [31:0]    misc_status,
 
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    input [15:0]    misc_status,
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    output [127:0]  debug
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);
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    //
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    //*******************************************************************************
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    wire [NUM_TX_STREAMS-1:0]                           dmatx_clear, dmatx_samp_stb, dmatx_pkt_stb, dmatx_error;
 
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    wire [NUM_TX_STREAMS-1:0]                           dmatx_clear, dmatx_enabled;
 
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    wire [NUM_TX_STREAMS-1:0]                           dmatx_samp_stb, dmatx_pkt_stb, dmatx_busy, dmatx_error;
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    wire [(NUM_TX_STREAMS*DMA_FRAME_SIZE_WIDTH)-1:0]    dmatx_frame_size;
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    wire [(NUM_TX_STREAMS*3)-1:0]                       dmatx_swap;
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    wire [NUM_RX_STREAMS-1:0]                           dmarx_clear, dmarx_samp_stb, dmarx_pkt_stb, dmarx_error;
 
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    wire [NUM_RX_STREAMS-1:0]                           dmarx_clear, dmarx_enabled;
 
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    wire [NUM_RX_STREAMS-1:0]                           dmarx_samp_stb, dmarx_pkt_stb, dmarx_busy, dmarx_error;
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    wire [(NUM_RX_STREAMS*DMA_FRAME_SIZE_WIDTH)-1:0]    dmarx_frame_size;
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    wire [(NUM_TX_STREAMS*3)-1:0]                       dmarx_swap;
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    wire [DMA_STREAM_WIDTH-1:0]                         dmarx_header;
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        .e3_rego_tdata(rego_tdata), .e3_rego_tvalid(rego_tvalid), .e3_rego_tready(rego_tready)
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    );
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    assign regi_tlast = regi_tvalid;
 
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    wire [15:0] fpga_status;
 
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    assign fpga_status[7:0]    = {|(dmatx_error), 1'b0, dmatx_enabled};
 
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    assign fpga_status[15:8]   = {|(dmarx_error), 1'b0, dmarx_enabled};
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    pcie_basic_regs basic_regs (
 
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    pcie_basic_regs #(
 
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        .SIGNATURE(32'h58333030 /*ASCII:"X300"*/), .CLK_FREQ(32'd166666667 /*bus_clk = 166.666667MHz*/)
 
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    ) basic_regs (
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        .clk(bus_clk), .reset(bus_rst),
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        .regi_tdata(basic_regi_tdata), .regi_tvalid(basic_regi_tvalid), .regi_tready(basic_regi_tready),
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        .rego_tdata(basic_rego_tdata), .rego_tvalid(basic_rego_tvalid), .rego_tready(basic_rego_tready),
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        .misc_status(misc_status)
 
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        .misc_status({fpga_status, misc_status})
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    );
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    pcie_dma_ctrl #(
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        .clk(bus_clk), .reset(bus_rst),
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        .regi_tdata(dmatx_regi_tdata), .regi_tvalid(dmatx_regi_tvalid), .regi_tready(dmatx_regi_tready),
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        .rego_tdata(dmatx_rego_tdata), .rego_tvalid(dmatx_rego_tvalid), .rego_tready(dmatx_rego_tready),
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        .set_clear(dmatx_clear), .set_frame_size(dmatx_frame_size), .sample_stb(dmatx_samp_stb), .packet_stb(dmatx_pkt_stb), 
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        .swap_lanes(dmatx_swap), .stream_err(dmatx_error), .rtr_sid(8'h00), .rtr_dst()
 
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        .set_enabled(dmatx_enabled), .set_clear(dmatx_clear), .set_frame_size(dmatx_frame_size),
 
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        .sample_stb(dmatx_samp_stb), .packet_stb(dmatx_pkt_stb), 
 
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        .swap_lanes(dmatx_swap), .stream_busy(dmatx_busy), .stream_err(dmatx_error), .rtr_sid(8'h00), .rtr_dst()
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    );
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    pcie_dma_ctrl #(
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        .clk(bus_clk), .reset(bus_rst),
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        .regi_tdata(dmarx_regi_tdata), .regi_tvalid(dmarx_regi_tvalid), .regi_tready(dmarx_regi_tready),
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        .rego_tdata(dmarx_rego_tdata), .rego_tvalid(dmarx_rego_tvalid), .rego_tready(dmarx_rego_tready),
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        .set_clear(dmarx_clear), .set_frame_size(dmarx_frame_size), .sample_stb(dmarx_samp_stb), .packet_stb(dmarx_pkt_stb), 
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        .swap_lanes(dmarx_swap), .stream_err(dmarx_error), .rtr_sid(dmarx_header[7:0]), .rtr_dst(dmarx_pkt_dest)
 
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        .set_enabled(dmarx_enabled), .set_clear(dmarx_clear), .set_frame_size(dmarx_frame_size),
 
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        .sample_stb(dmarx_samp_stb), .packet_stb(dmarx_pkt_stb), 
 
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        .swap_lanes(dmarx_swap), .stream_busy(dmarx_busy), .stream_err(dmarx_error), .rtr_sid(dmarx_header[7:0]), .rtr_dst(dmarx_pkt_dest)
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    );
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    //
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    //*******************************************************************************
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    //*******************************************************************************
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    // TX DMA Datapath
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    //
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    wire [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0]    dmatx_tdata_bclk,  dmatx_tdata_trun,  dmatx_tdata_gt, dmatx_tdata_swap;
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    wire [NUM_TX_STREAMS-1:0]                       dmatx_tvalid_bclk, dmatx_tvalid_trun, dmatx_tvalid_gt;
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    wire [NUM_TX_STREAMS-1:0]                       dmatx_tready_bclk, dmatx_tready_trun, dmatx_tready_gt;
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    wire [NUM_TX_STREAMS-1:0]                                          dmatx_tlast_trun,  dmatx_tlast_gt;
 
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    wire [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0]    dmatx_tdata_bclk,  dmatx_tdata_in, dmatx_tdata_trun,  dmatx_tdata_gt, dmatx_tdata_swap;
 
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    wire [NUM_TX_STREAMS-1:0]                       dmatx_tvalid_bclk, dmatx_tvalid_in, dmatx_tvalid_trun, dmatx_tvalid_gt;
 
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    wire [NUM_TX_STREAMS-1:0]                       dmatx_tready_bclk, dmatx_tready_in, dmatx_tready_trun, dmatx_tready_gt;
 
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    wire [NUM_TX_STREAMS-1:0]                       dmatx_tlast_trun,  dmatx_tlast_gt;
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    wire [DMA_STREAM_WIDTH-1:0]                     dmatx_tdata_mux;
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    wire                                            dmatx_tvalid_mux, dmatx_tlast_mux, dmatx_tready_mux;
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                .o_aclk(bus_clk), .o_tdata(`GET_DMA_BUS(dmatx_tdata_bclk,i)), .o_tvalid(dmatx_tvalid_bclk[i]), .o_tready(dmatx_tready_bclk[i])
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            );
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            pcie_lossy_samp_gate tx_samp_gate (
 
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                .i_tdata(`GET_DMA_BUS(dmatx_tdata_bclk,i)), .i_tvalid(dmatx_tvalid_bclk[i]), .i_tready(dmatx_tready_bclk[i]),
 
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                .o_tdata(`GET_DMA_BUS(dmatx_tdata_in,i)), .o_tvalid(dmatx_tvalid_in[i]), .o_tready(dmatx_tready_in[i]),
 
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                .drop(~dmatx_enabled[i]), .dropping(dmatx_busy[i])
 
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            );
 
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            data_swapper_64 tx_data_swapper (
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                .swap_lanes(`GET_SWAP_BUS(dmatx_swap,i)), .i_tdata(`GET_DMA_BUS(dmatx_tdata_bclk,i)), .o_tdata(`GET_DMA_BUS(dmatx_tdata_swap,i))
 
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                .swap_lanes(`GET_SWAP_BUS(dmatx_swap,i)), .i_tdata(`GET_DMA_BUS(dmatx_tdata_in,i)), .o_tdata(`GET_DMA_BUS(dmatx_tdata_swap,i))
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            );
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            cvita_dechunker tx_dma_dechunker (
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                .clk(bus_clk), .reset(bus_rst), .clear(dmatx_clear[i]), .frame_size(`GET_FSIZE_BUS(dmatx_frame_size, i)),
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                .i_tdata(`GET_DMA_BUS(dmatx_tdata_swap,i)), .i_tvalid(dmatx_tvalid_bclk[i]), .i_tready(dmatx_tready_bclk[i]),
 
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                .i_tdata(`GET_DMA_BUS(dmatx_tdata_swap,i)), .i_tvalid(dmatx_tvalid_in[i]), .i_tready(dmatx_tready_in[i]),
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                .o_tdata(`GET_DMA_BUS(dmatx_tdata_trun,i)), .o_tlast(dmatx_tlast_trun[i]), .o_tvalid(dmatx_tvalid_trun[i]), .o_tready(dmatx_tready_trun[i]),
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                .error(dmatx_error[i])
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            );
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    //*******************************************************************************
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    // RX DMA Datapath
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    //
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    wire [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0]    dmarx_tdata_bclk,  dmarx_tdata_pad, dmarx_tdata_swap;
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    wire [NUM_RX_STREAMS-1:0]                       dmarx_tvalid_bclk, dmarx_tvalid_pad;
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    wire [NUM_RX_STREAMS-1:0]                       dmarx_tready_bclk, dmarx_tready_pad;
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    wire [NUM_RX_STREAMS-1:0]                       dmarx_tlast_bclk,  dmarx_tlast_pad;
 
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    wire [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0]    dmarx_tdata_bclk,  dmarx_tdata_pad, dmarx_tdata_swap, dmarx_tdata_out;
 
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    wire [NUM_RX_STREAMS-1:0]                       dmarx_tvalid_bclk, dmarx_tvalid_pad, dmarx_tvalid_out;
 
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    wire [NUM_RX_STREAMS-1:0]                       dmarx_tready_bclk, dmarx_tready_pad, dmarx_tready_out;
 
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    wire [NUM_RX_STREAMS-1:0]                       dmarx_tlast_bclk,  dmarx_tlast_pad, dmarx_tlast_out;
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    wire [DMA_STREAM_WIDTH-1:0]                     dmarx_tdata_mux;
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    wire                                            dmarx_tvalid_mux, dmarx_tlast_mux, dmarx_tready_mux;
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                .swap_lanes(`GET_SWAP_BUS(dmarx_swap,j)), .i_tdata(`GET_DMA_BUS(dmarx_tdata_pad,j)), .o_tdata(`GET_DMA_BUS(dmarx_tdata_swap,j))
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            );
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            pcie_lossy_samp_gate rx_samp_gate (
 
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                .i_tdata(`GET_DMA_BUS(dmarx_tdata_swap,j)), .i_tvalid(dmarx_tvalid_pad[j]), .i_tready(dmarx_tready_pad[j]),
 
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                .o_tdata(`GET_DMA_BUS(dmarx_tdata_out,j)), .o_tvalid(dmarx_tvalid_out[j]), .o_tready(dmarx_tready_out[j]),
 
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                .drop(~dmarx_enabled[j]), .dropping(dmarx_busy[j])
 
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            );
 
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            axi_fifo_2clk #(.WIDTH(DMA_STREAM_WIDTH), .SIZE(DMA_CLK_XING_FIFO_SIZE)) rx_dma_clock_crossing_fifo (
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                .reset(bus_rst),
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                .i_aclk(bus_clk), .i_tdata(`GET_DMA_BUS(dmarx_tdata_swap,j)), .i_tvalid(dmarx_tvalid_pad[j]), .i_tready(dmarx_tready_pad[j]),
 
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                .i_aclk(bus_clk), .i_tdata(`GET_DMA_BUS(dmarx_tdata_out,j)), .i_tvalid(dmarx_tvalid_out[j]), .i_tready(dmarx_tready_out[j]),
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                .o_aclk(ioport2_clk), .o_tdata(`GET_DMA_BUS(dmarx_tdata_iop2,j)), .o_tvalid(dmarx_tvalid_iop2[j]), .o_tready(dmarx_tready_iop2[j])
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            );
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        end
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    endgenerate
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    //
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    //*******************************************************************************
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endmodule
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`undef GET_DMA_BUS