1
by Clint Adams
Import upstream version 2010.06~rc1 |
1 |
/*
|
2 |
* (C) Copyright 2001-2004
|
|
3 |
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
|
4 |
*
|
|
5 |
* See file CREDITS for list of people who contributed to this
|
|
6 |
* project.
|
|
7 |
*
|
|
8 |
* This program is free software; you can redistribute it and/or
|
|
9 |
* modify it under the terms of the GNU General Public License as
|
|
10 |
* published by the Free Software Foundation; either version 2 of
|
|
11 |
* the License, or (at your option) any later version.
|
|
12 |
*
|
|
13 |
* This program is distributed in the hope that it will be useful,
|
|
14 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
15 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
16 |
* GNU General Public License for more details.
|
|
17 |
*
|
|
18 |
* You should have received a copy of the GNU General Public License
|
|
19 |
* along with this program; if not, write to the Free Software
|
|
20 |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
21 |
* MA 02111-1307 USA
|
|
22 |
*/
|
|
23 |
||
24 |
/*
|
|
25 |
* board/config.h - configuration options, board specific
|
|
26 |
*/
|
|
27 |
||
28 |
#ifndef __CONFIG_H
|
|
29 |
#define __CONFIG_H
|
|
30 |
||
31 |
/*
|
|
32 |
* High Level Configuration Options
|
|
33 |
* (easy to change)
|
|
34 |
*/
|
|
35 |
||
36 |
#define CONFIG_405GP 1 /* This is a PPC405 CPU */ |
|
37 |
#define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
|
38 |
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ |
|
39 |
#define CONFIG_CPCI405_VER2 1 /* ...version 2 */ |
|
40 |
||
1.1.7
by Clint Adams
Import upstream version 2010.12~rc2 |
41 |
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
|
42 |
||
1
by Clint Adams
Import upstream version 2010.06~rc1 |
43 |
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
44 |
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
|
45 |
||
46 |
#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ |
|
47 |
||
48 |
#define CONFIG_BAUDRATE 9600
|
|
49 |
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
|
50 |
||
51 |
#undef CONFIG_BOOTARGS
|
|
52 |
#undef CONFIG_BOOTCOMMAND
|
|
53 |
||
54 |
#define CONFIG_PREBOOT /* enable preboot variable */ |
|
55 |
||
56 |
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
|
57 |
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
|
58 |
||
59 |
#define CONFIG_PPC4xx_EMAC
|
|
60 |
#define CONFIG_MII 1 /* MII PHY management */ |
|
61 |
#define CONFIG_PHY_ADDR 0 /* PHY address */ |
|
62 |
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
|
63 |
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
|
64 |
||
65 |
#undef CONFIG_HAS_ETH1
|
|
66 |
||
67 |
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ |
|
68 |
||
69 |
/*
|
|
70 |
* BOOTP options
|
|
71 |
*/
|
|
72 |
#define CONFIG_BOOTP_SUBNETMASK
|
|
73 |
#define CONFIG_BOOTP_GATEWAY
|
|
74 |
#define CONFIG_BOOTP_HOSTNAME
|
|
75 |
#define CONFIG_BOOTP_BOOTPATH
|
|
76 |
#define CONFIG_BOOTP_DNS
|
|
77 |
#define CONFIG_BOOTP_DNS2
|
|
78 |
#define CONFIG_BOOTP_SEND_HOSTNAME
|
|
79 |
||
80 |
||
81 |
/*
|
|
82 |
* Command line configuration.
|
|
83 |
*/
|
|
84 |
#include <config_cmd_default.h> |
|
85 |
||
86 |
#define CONFIG_CMD_DHCP
|
|
87 |
#define CONFIG_CMD_PCI
|
|
88 |
#define CONFIG_CMD_IRQ
|
|
89 |
#define CONFIG_CMD_IDE
|
|
90 |
#define CONFIG_CMD_FAT
|
|
91 |
#define CONFIG_CMD_ELF
|
|
92 |
#define CONFIG_CMD_DATE
|
|
93 |
#define CONFIG_CMD_I2C
|
|
94 |
#define CONFIG_CMD_MII
|
|
95 |
#define CONFIG_CMD_PING
|
|
96 |
#define CONFIG_CMD_BSP
|
|
97 |
#define CONFIG_CMD_EEPROM
|
|
98 |
||
99 |
#define CONFIG_MAC_PARTITION
|
|
100 |
#define CONFIG_DOS_PARTITION
|
|
101 |
||
102 |
#define CONFIG_SUPPORT_VFAT
|
|
103 |
||
104 |
#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */ |
|
105 |
||
106 |
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
|
107 |
||
108 |
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
|
109 |
||
110 |
/*
|
|
111 |
* Miscellaneous configurable options
|
|
112 |
*/
|
|
113 |
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
|
114 |
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
|
115 |
||
116 |
#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
|
117 |
#ifdef CONFIG_SYS_HUSH_PARSER
|
|
118 |
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
|
119 |
#endif
|
|
120 |
||
121 |
#if defined(CONFIG_CMD_KGDB)
|
|
122 |
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
|
123 |
#else
|
|
124 |
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
|
125 |
#endif
|
|
126 |
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
|
127 |
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
|
128 |
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
|
129 |
||
130 |
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
|
131 |
||
132 |
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
|
133 |
||
134 |
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
|
135 |
||
136 |
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
|
137 |
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
|
138 |
||
1.1.7
by Clint Adams
Import upstream version 2010.12~rc2 |
139 |
#define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
140 |
#define CONFIG_SYS_NS16550
|
|
141 |
#define CONFIG_SYS_NS16550_SERIAL
|
|
142 |
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
|
143 |
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
|
|
144 |
||
1
by Clint Adams
Import upstream version 2010.06~rc1 |
145 |
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
146 |
#define CONFIG_SYS_BASE_BAUD 691200
|
|
147 |
||
148 |
/* The following table includes the supported baudrates */
|
|
149 |
#define CONFIG_SYS_BAUDRATE_TABLE \
|
|
150 |
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
|
|
151 |
57600, 115200, 230400, 460800, 921600 }
|
|
152 |
||
153 |
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
|
154 |
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
|
155 |
||
156 |
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
|
157 |
||
158 |
#define CONFIG_LOOPW 1 /* enable loopw command */ |
|
159 |
||
160 |
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
|
161 |
||
162 |
/* Only interrupt boot if special string is typed */
|
|
163 |
#define CONFIG_AUTOBOOT_KEYED 1
|
|
164 |
#define CONFIG_AUTOBOOT_PROMPT \
|
|
165 |
"Autobooting in %d seconds\n", bootdelay
|
|
166 |
#undef CONFIG_AUTOBOOT_DELAY_STR
|
|
167 |
#undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */ |
|
168 |
#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/ |
|
169 |
||
170 |
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
|
171 |
||
172 |
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
|
173 |
||
174 |
/*-----------------------------------------------------------------------
|
|
175 |
* PCI stuff
|
|
176 |
*-----------------------------------------------------------------------
|
|
177 |
*/
|
|
178 |
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
|
179 |
#define PCI_HOST_FORCE 1 /* configure as pci host */ |
|
180 |
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
|
181 |
||
182 |
#define CONFIG_PCI /* include pci support */ |
|
183 |
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
|
184 |
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
|
185 |
/* resource configuration */
|
|
186 |
||
187 |
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
|
188 |
||
189 |
#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ |
|
190 |
||
191 |
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ |
|
192 |
||
193 |
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
|
194 |
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ |
|
195 |
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ |
|
196 |
#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ |
|
197 |
#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ |
|
198 |
#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ |
|
199 |
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
|
200 |
#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ |
|
201 |
#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ |
|
202 |
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
|
203 |
||
204 |
#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ |
|
205 |
||
206 |
/*-----------------------------------------------------------------------
|
|
207 |
* IDE/ATA stuff
|
|
208 |
*-----------------------------------------------------------------------
|
|
209 |
*/
|
|
210 |
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
|
211 |
#undef CONFIG_IDE_LED /* no led for ide supported */ |
|
212 |
#define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
|
213 |
||
214 |
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
|
215 |
#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ |
|
216 |
||
217 |
#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
|
|
218 |
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
|
219 |
||
220 |
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
|
221 |
#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ |
|
222 |
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ |
|
223 |
||
224 |
/*-----------------------------------------------------------------------
|
|
225 |
* Start addresses for the final memory configuration
|
|
226 |
* (Set up by the startup code)
|
|
227 |
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
|
228 |
*/
|
|
229 |
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
|
230 |
#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
|
|
231 |
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
|
232 |
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ |
|
233 |
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
|
234 |
||
235 |
/*
|
|
236 |
* For booting Linux, the board info and command line data
|
|
237 |
* have to be in the first 8 MB of memory, since this is
|
|
238 |
* the maximum mapped by the Linux kernel during initialization.
|
|
239 |
*/
|
|
240 |
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
|
241 |
/*-----------------------------------------------------------------------
|
|
242 |
* FLASH organization
|
|
243 |
*/
|
|
244 |
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
|
245 |
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
|
246 |
||
247 |
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
|
248 |
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
|
249 |
||
250 |
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
|
251 |
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
|
252 |
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
|
253 |
/*
|
|
254 |
* The following defines are added for buggy IOP480 byte interface.
|
|
255 |
* All other boards should use the standard values (CPCI405 etc.)
|
|
256 |
*/
|
|
257 |
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
|
258 |
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ |
|
259 |
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ |
|
260 |
||
261 |
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
|
262 |
||
263 |
#if 0 /* Use NVRAM for environment variables */ |
|
264 |
/*-----------------------------------------------------------------------
|
|
265 |
* NVRAM organization
|
|
266 |
*/
|
|
267 |
#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
|
|
268 |
#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
|
|
269 |
#define CONFIG_ENV_ADDR \
|
|
270 |
(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
|
|
271 |
||
272 |
#else /* Use EEPROM for environment variables */
|
|
273 |
||
274 |
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
|
275 |
#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
|
276 |
#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ |
|
277 |
/* total size of a CAT24WC16 is 2048 bytes */
|
|
278 |
#endif
|
|
279 |
||
280 |
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ |
|
281 |
#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ |
|
282 |
#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ |
|
283 |
||
284 |
/*-----------------------------------------------------------------------
|
|
285 |
* I2C EEPROM (CAT24WC16) for environment
|
|
286 |
*/
|
|
287 |
#define CONFIG_HARD_I2C /* I2c with hardware support */ |
|
288 |
#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
|
289 |
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
|
290 |
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
|
291 |
||
292 |
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
|
293 |
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
|
294 |
/* mask of address bits that overflow into the "EEPROM chip address" */
|
|
295 |
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
|
296 |
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
|
297 |
/* 16 byte page write mode using*/
|
|
298 |
/* last 4 bits of the address */
|
|
299 |
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
|
300 |
||
301 |
/*
|
|
302 |
* Init Memory Controller:
|
|
303 |
*
|
|
304 |
* BR0/1 and OR0/1 (FLASH)
|
|
305 |
*/
|
|
306 |
||
307 |
#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ |
|
308 |
#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ |
|
309 |
||
310 |
/*-----------------------------------------------------------------------
|
|
311 |
* External Bus Controller (EBC) Setup
|
|
312 |
*/
|
|
313 |
||
314 |
/* Memory Bank 0 (Flash Bank 0) initialization */
|
|
315 |
#define CONFIG_SYS_EBC_PB0AP 0x92015480
|
|
316 |
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
|
317 |
||
318 |
/* Memory Bank 1 (Flash Bank 1) initialization */
|
|
319 |
#define CONFIG_SYS_EBC_PB1AP 0x92015480
|
|
320 |
#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ |
|
321 |
||
322 |
/* Memory Bank 2 (CAN0, 1) initialization */
|
|
323 |
#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
|
324 |
#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
|
325 |
#define CONFIG_SYS_LED_ADDR 0xF0000380
|
|
326 |
||
327 |
/* Memory Bank 3 (CompactFlash IDE) initialization */
|
|
328 |
#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
|
329 |
#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ |
|
330 |
||
331 |
/* Memory Bank 4 (NVRAM/RTC) initialization */
|
|
332 |
/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
|
|
333 |
#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ |
|
334 |
#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ |
|
335 |
||
336 |
/* Memory Bank 5 (optional Quart) initialization */
|
|
337 |
#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ |
|
338 |
#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ |
|
339 |
||
340 |
/* Memory Bank 6 (FPGA internal) initialization */
|
|
341 |
#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
|
342 |
#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ |
|
343 |
#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
|
|
344 |
||
345 |
/*-----------------------------------------------------------------------
|
|
346 |
* FPGA stuff
|
|
347 |
*/
|
|
348 |
/* FPGA internal regs */
|
|
349 |
#define CONFIG_SYS_FPGA_MODE 0x00
|
|
350 |
#define CONFIG_SYS_FPGA_STATUS 0x02
|
|
351 |
#define CONFIG_SYS_FPGA_TS 0x04
|
|
352 |
#define CONFIG_SYS_FPGA_TS_LOW 0x06
|
|
353 |
#define CONFIG_SYS_FPGA_TS_CAP0 0x10
|
|
354 |
#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
|
|
355 |
#define CONFIG_SYS_FPGA_TS_CAP1 0x14
|
|
356 |
#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
|
|
357 |
#define CONFIG_SYS_FPGA_TS_CAP2 0x18
|
|
358 |
#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
|
|
359 |
#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
|
|
360 |
#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
|
|
361 |
||
362 |
/* FPGA Mode Reg */
|
|
363 |
#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
|
|
364 |
#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
|
|
365 |
#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ |
|
366 |
#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
|
|
367 |
#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
|
|
368 |
#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
|
|
369 |
||
370 |
/* FPGA Status Reg */
|
|
371 |
#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
|
|
372 |
#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
|
|
373 |
#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
|
|
374 |
#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
|
|
375 |
#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
|
|
376 |
||
377 |
#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
|
378 |
#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ |
|
379 |
||
380 |
/* FPGA program pin configuration */
|
|
381 |
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
|
382 |
#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ |
|
383 |
#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ |
|
384 |
#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ |
|
385 |
#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ |
|
386 |
||
387 |
/*-----------------------------------------------------------------------
|
|
388 |
* Definitions for initial stack pointer and data area (in data cache)
|
|
389 |
*/
|
|
390 |
#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ |
|
391 |
||
392 |
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ |
|
1.1.7
by Clint Adams
Import upstream version 2010.12~rc2 |
393 |
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
394 |
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
1
by Clint Adams
Import upstream version 2010.06~rc1 |
395 |
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
396 |
||
397 |
#endif /* __CONFIG_H */ |