- Committer: blueswir1
- Date: 2008-07-10 17:21:31 UTC
- Revision ID: git-v1:d03d860b151d382e3a158e8e27838729cfcda075
Link ARM prologue closer to code segment to avoid a build failure
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4867 c046a42c-6fe2-441c-8c8c-71466251a162
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4867 c046a42c-6fe2-441c-8c8c-71466251a162
| Filename | Latest Rev | Last Changed | Committer | Comment | Size | ||
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cpu.h |
4806 | 16 years ago | pbrook | Move interrupt_request and user_mode_only to commo | 5.7 KB |
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crisv32-decode.h |
3979 | 16 years ago | edgar_igl | Silently ignore CRIS cache flushes, instead of abo | 5.5 KB |
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exec.h |
3374 | 17 years ago | j_mayer | Replace is_user variable with mmu_idx in softmmu c | 1.8 KB |
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helper.c |
4708 | 16 years ago | edgar_igl | CRIS: Emulate NMIs. git-svn-id: svn://svn.savanna | 4.7 KB |
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helper.h |
4707 | 16 years ago | edgar_igl | CRIS: Support RFN insn. git-svn-id: svn://svn.sav | 990 bytes |
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machine.c |
4710 | 16 years ago | edgar_igl | CRIS: Add (untested) cpu-state save/load. git-svn | 2.3 KB |
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mmu.c |
4793 | 16 years ago | edgar_igl | Avoid CRIS related warnings by Jan Kiszka. git-sv | 8.8 KB |
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mmu.h |
4439 | 16 years ago | edgar_igl | CRIS: Improve TLB management and handle delayslots | 381 bytes |
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op.c |
4288 | 16 years ago | edgar_igl | CRIS updates: * Support both the I and D MMUs and | 15.9 KB |
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op_helper.c |
4829 | 16 years ago | ths | Convert remaining __builtin_expect to likely/unlik | 12.5 KB |
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op_mem.c |
3351 | 17 years ago | ths | The remainder of CRIS CPU emulation files, by Edga | 1.6 KB |
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op_template.h |
3351 | 17 years ago | ths | The remainder of CRIS CPU emulation files, by Edga | 1.2 KB |
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opcode-cris.h |
3346 | 17 years ago | ths | CRIS disassembler, originally from binutils, by Ed | 10 KB |
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translate.c |
4829 | 16 years ago | ths | Convert remaining __builtin_expect to likely/unlik | 80.5 KB |
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