101
by bellard
symbol fix |
1 |
#ifndef _QEMU_ELF_H
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2 |
#define _QEMU_ELF_H
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2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
3 |
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#include <inttypes.h> |
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75
by bellard
more cpu support |
6 |
/* 32-bit ELF base types. */
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typedef uint32_t Elf32_Addr; |
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2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
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typedef uint16_t Elf32_Half; |
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typedef uint32_t Elf32_Off; |
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typedef int32_t Elf32_Sword; |
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typedef uint32_t Elf32_Word; |
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75
by bellard
more cpu support |
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/* 64-bit ELF base types. */
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typedef uint64_t Elf64_Addr; |
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typedef uint16_t Elf64_Half; |
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typedef int16_t Elf64_SHalf; |
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typedef uint64_t Elf64_Off; |
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typedef int32_t Elf64_Sword; |
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typedef uint32_t Elf64_Word; |
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typedef uint64_t Elf64_Xword; |
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typedef int64_t Elf64_Sxword; |
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2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
23 |
/* These constants are for the segment types stored in the image headers */
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#define PT_NULL 0
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#define PT_LOAD 1
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#define PT_DYNAMIC 2
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#define PT_INTERP 3
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#define PT_NOTE 4
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#define PT_SHLIB 5
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#define PT_PHDR 6
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#define PT_LOPROC 0x70000000
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#define PT_HIPROC 0x7fffffff
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75
by bellard
more cpu support |
33 |
#define PT_MIPS_REGINFO 0x70000000
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1458
by bellard
MIPS target (Jocelyn Mayer) |
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#define PT_MIPS_OPTIONS 0x70000001
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75
by bellard
more cpu support |
35 |
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/* Flags in the e_flags field of the header */
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1458
by bellard
MIPS target (Jocelyn Mayer) |
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/* MIPS architecture level. */
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#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ |
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#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ |
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#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ |
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#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ |
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#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ |
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#define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */ |
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#define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */ |
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/* The ABI of a file. */
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#define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */ |
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#define EF_MIPS_ABI_O64 0x00002000 /* O32 extended for 64 bit. */ |
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75
by bellard
more cpu support |
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#define EF_MIPS_NOREORDER 0x00000001
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#define EF_MIPS_PIC 0x00000002
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#define EF_MIPS_CPIC 0x00000004
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1458
by bellard
MIPS target (Jocelyn Mayer) |
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#define EF_MIPS_ABI2 0x00000020
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#define EF_MIPS_OPTIONS_FIRST 0x00000080
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#define EF_MIPS_32BITMODE 0x00000100
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#define EF_MIPS_ABI 0x0000f000
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75
by bellard
more cpu support |
57 |
#define EF_MIPS_ARCH 0xf0000000
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2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
58 |
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/* These constants define the different elf file types */
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#define ET_NONE 0
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#define ET_REL 1
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#define ET_EXEC 2
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#define ET_DYN 3
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#define ET_CORE 4
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75
by bellard
more cpu support |
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#define ET_LOPROC 0xff00
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#define ET_HIPROC 0xffff
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2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
67 |
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/* These constants define the various ELF target machines */
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#define EM_NONE 0
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#define EM_M32 1
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#define EM_SPARC 2
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#define EM_386 3
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#define EM_68K 4
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#define EM_88K 5
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#define EM_486 6 /* Perhaps disused */ |
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#define EM_860 7
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#define EM_MIPS 8 /* MIPS R3000 (officially, big-endian only) */ |
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#define EM_MIPS_RS4_BE 10 /* MIPS R4000 big-endian */ |
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#define EM_PARISC 15 /* HPPA */ |
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#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ |
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#define EM_PPC 20 /* PowerPC */ |
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75
by bellard
more cpu support |
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#define EM_PPC64 21 /* PowerPC64 */ |
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#define EM_ARM 40 /* ARM */ |
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#define EM_SH 42 /* SuperH */ |
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#define EM_SPARCV9 43 /* SPARC v9 64-bit */ |
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#define EM_IA_64 50 /* HP/Intel IA-64 */ |
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#define EM_X86_64 62 /* AMD x86-64 */ |
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#define EM_S390 22 /* IBM S/390 */ |
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#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ |
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#define EM_V850 87 /* NEC v850 */ |
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#define EM_H8_300H 47 /* Hitachi H8/300H */ |
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#define EM_H8S 48 /* Hitachi H8S */ |
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2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
107 |
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/*
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* This is an interim value that we will use until the committee comes
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* up with a final number.
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*/
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#define EM_ALPHA 0x9026
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75
by bellard
more cpu support |
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/* Bogus old v850 magic number, used by old tools. */
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#define EM_CYGNUS_V850 0x9080
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/*
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* This is the old interim value for S/390 architecture
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*/
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#define EM_S390_OLD 0xA390
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2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
121 |
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/* This is the info that is needed to parse the dynamic section of the file */
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#define DT_NULL 0
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#define DT_NEEDED 1
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#define DT_PLTRELSZ 2
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#define DT_PLTGOT 3
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#define DT_HASH 4
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#define DT_STRTAB 5
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#define DT_SYMTAB 6
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#define DT_RELA 7
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#define DT_RELASZ 8
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#define DT_RELAENT 9
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#define DT_STRSZ 10
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#define DT_SYMENT 11
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#define DT_INIT 12
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#define DT_FINI 13
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#define DT_SONAME 14
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#define DT_RPATH 15
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#define DT_SYMBOLIC 16
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#define DT_REL 17
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#define DT_RELSZ 18
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#define DT_RELENT 19
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#define DT_PLTREL 20
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#define DT_DEBUG 21
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#define DT_TEXTREL 22
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#define DT_JMPREL 23
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#define DT_LOPROC 0x70000000
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#define DT_HIPROC 0x7fffffff
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75
by bellard
more cpu support |
149 |
#define DT_MIPS_RLD_VERSION 0x70000001
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#define DT_MIPS_TIME_STAMP 0x70000002
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#define DT_MIPS_ICHECKSUM 0x70000003
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#define DT_MIPS_IVERSION 0x70000004
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#define DT_MIPS_FLAGS 0x70000005
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#define RHF_NONE 0
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#define RHF_HARDWAY 1
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#define RHF_NOTPOT 2
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#define DT_MIPS_BASE_ADDRESS 0x70000006
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#define DT_MIPS_CONFLICT 0x70000008
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#define DT_MIPS_LIBLIST 0x70000009
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#define DT_MIPS_LOCAL_GOTNO 0x7000000a
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#define DT_MIPS_CONFLICTNO 0x7000000b
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#define DT_MIPS_LIBLISTNO 0x70000010
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#define DT_MIPS_SYMTABNO 0x70000011
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#define DT_MIPS_UNREFEXTNO 0x70000012
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#define DT_MIPS_GOTSYM 0x70000013
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#define DT_MIPS_HIPAGENO 0x70000014
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#define DT_MIPS_RLD_MAP 0x70000016
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2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
168 |
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/* This info is needed when parsing the symbol table */
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#define STB_LOCAL 0
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#define STB_GLOBAL 1
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#define STB_WEAK 2
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#define STT_NOTYPE 0
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#define STT_OBJECT 1
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#define STT_FUNC 2
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#define STT_SECTION 3
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#define STT_FILE 4
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75
by bellard
more cpu support |
180 |
#define ELF_ST_BIND(x) ((x) >> 4)
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#define ELF_ST_TYPE(x) (((unsigned int) x) & 0xf)
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#define ELF32_ST_BIND(x) ELF_ST_BIND(x)
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#define ELF32_ST_TYPE(x) ELF_ST_TYPE(x)
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#define ELF64_ST_BIND(x) ELF_ST_BIND(x)
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#define ELF64_ST_TYPE(x) ELF_ST_TYPE(x)
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2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
186 |
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/* Symbolic values for the entries in the auxiliary table
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put on the initial stack */
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#define AT_NULL 0 /* end of vector */ |
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#define AT_IGNORE 1 /* entry should be ignored */ |
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#define AT_EXECFD 2 /* file descriptor of program */ |
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#define AT_PHDR 3 /* program headers for program */ |
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#define AT_PHENT 4 /* size of program header entry */ |
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#define AT_PHNUM 5 /* number of program headers */ |
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#define AT_PAGESZ 6 /* system page size */ |
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#define AT_BASE 7 /* base address of interpreter */ |
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#define AT_FLAGS 8 /* flags */ |
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#define AT_ENTRY 9 /* entry point of program */ |
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#define AT_NOTELF 10 /* program is not ELF */ |
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#define AT_UID 11 /* real uid */ |
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#define AT_EUID 12 /* effective uid */ |
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#define AT_GID 13 /* real gid */ |
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#define AT_EGID 14 /* effective gid */ |
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75
by bellard
more cpu support |
204 |
#define AT_PLATFORM 15 /* string identifying CPU for optimizations */ |
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#define AT_HWCAP 16 /* arch dependent hints at CPU capabilities */ |
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#define AT_CLKTCK 17 /* frequency at which times() increments */ |
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2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
207 |
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typedef struct dynamic{ |
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Elf32_Sword d_tag; |
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union{ |
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Elf32_Sword d_val; |
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Elf32_Addr d_ptr; |
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} d_un; |
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} Elf32_Dyn; |
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typedef struct { |
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75
by bellard
more cpu support |
217 |
Elf64_Sxword d_tag; /* entry tag value */ |
2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
218 |
union { |
75
by bellard
more cpu support |
219 |
Elf64_Xword d_val; |
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Elf64_Addr d_ptr; |
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2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
221 |
} d_un; |
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} Elf64_Dyn; |
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/* The following are used with relocations */
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#define ELF32_R_SYM(x) ((x) >> 8)
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#define ELF32_R_TYPE(x) ((x) & 0xff)
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75
by bellard
more cpu support |
228 |
#define ELF64_R_SYM(i) ((i) >> 32)
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#define ELF64_R_TYPE(i) ((i) & 0xffffffff)
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2056
by bellard
Sparc64 host support (Blue Swirl) |
230 |
#define ELF64_R_TYPE_DATA(i) (((ELF64_R_TYPE(i) >> 8) ^ 0x00800000) - 0x00800000)
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75
by bellard
more cpu support |
231 |
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2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
232 |
#define R_386_NONE 0
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#define R_386_32 1
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#define R_386_PC32 2
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#define R_386_GOT32 3
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#define R_386_PLT32 4
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#define R_386_COPY 5
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#define R_386_GLOB_DAT 6
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#define R_386_JMP_SLOT 7
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#define R_386_RELATIVE 8
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#define R_386_GOTOFF 9
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#define R_386_GOTPC 10
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#define R_386_NUM 11
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||
75
by bellard
more cpu support |
245 |
#define R_MIPS_NONE 0
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#define R_MIPS_16 1
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#define R_MIPS_32 2
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#define R_MIPS_REL32 3
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#define R_MIPS_26 4
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#define R_MIPS_HI16 5
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#define R_MIPS_LO16 6
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#define R_MIPS_GPREL16 7
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#define R_MIPS_LITERAL 8
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#define R_MIPS_GOT16 9
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#define R_MIPS_PC16 10
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#define R_MIPS_CALL16 11
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#define R_MIPS_GPREL32 12
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/* The remaining relocs are defined on Irix, although they are not
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in the MIPS ELF ABI. */
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#define R_MIPS_UNUSED1 13
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#define R_MIPS_UNUSED2 14
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#define R_MIPS_UNUSED3 15
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#define R_MIPS_SHIFT5 16
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#define R_MIPS_SHIFT6 17
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#define R_MIPS_64 18
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#define R_MIPS_GOT_DISP 19
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#define R_MIPS_GOT_PAGE 20
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#define R_MIPS_GOT_OFST 21
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/*
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* The following two relocation types are specified in the MIPS ABI
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* conformance guide version 1.2 but not yet in the psABI.
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*/
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#define R_MIPS_GOTHI16 22
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#define R_MIPS_GOTLO16 23
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#define R_MIPS_SUB 24
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#define R_MIPS_INSERT_A 25
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#define R_MIPS_INSERT_B 26
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#define R_MIPS_DELETE 27
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#define R_MIPS_HIGHER 28
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#define R_MIPS_HIGHEST 29
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/*
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* The following two relocation types are specified in the MIPS ABI
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* conformance guide version 1.2 but not yet in the psABI.
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*/
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#define R_MIPS_CALLHI16 30
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#define R_MIPS_CALLLO16 31
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/*
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* This range is reserved for vendor specific relocations.
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*/
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#define R_MIPS_LOVENDOR 100
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#define R_MIPS_HIVENDOR 127
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||
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||
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/*
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* Sparc ELF relocation types
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*/
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#define R_SPARC_NONE 0
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#define R_SPARC_8 1
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#define R_SPARC_16 2
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#define R_SPARC_32 3
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#define R_SPARC_DISP8 4
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#define R_SPARC_DISP16 5
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#define R_SPARC_DISP32 6
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#define R_SPARC_WDISP30 7
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#define R_SPARC_WDISP22 8
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#define R_SPARC_HI22 9
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#define R_SPARC_22 10
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#define R_SPARC_13 11
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#define R_SPARC_LO10 12
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#define R_SPARC_GOT10 13
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#define R_SPARC_GOT13 14
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#define R_SPARC_GOT22 15
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#define R_SPARC_PC10 16
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#define R_SPARC_PC22 17
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#define R_SPARC_WPLT30 18
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#define R_SPARC_COPY 19
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#define R_SPARC_GLOB_DAT 20
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#define R_SPARC_JMP_SLOT 21
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#define R_SPARC_RELATIVE 22
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#define R_SPARC_UA32 23
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#define R_SPARC_PLT32 24
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#define R_SPARC_HIPLT22 25
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#define R_SPARC_LOPLT10 26
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#define R_SPARC_PCPLT32 27
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#define R_SPARC_PCPLT22 28
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#define R_SPARC_PCPLT10 29
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#define R_SPARC_10 30
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#define R_SPARC_11 31
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#define R_SPARC_64 32
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2056
by bellard
Sparc64 host support (Blue Swirl) |
330 |
#define R_SPARC_OLO10 33
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2397
by ths
Support for more SPARC relocations, by Martin Bochnig. |
331 |
#define R_SPARC_HH22 34
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#define R_SPARC_HM10 35
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#define R_SPARC_LM22 36
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75
by bellard
more cpu support |
334 |
#define R_SPARC_WDISP16 40
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#define R_SPARC_WDISP19 41
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#define R_SPARC_7 43
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#define R_SPARC_5 44
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#define R_SPARC_6 45
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/* Bits present in AT_HWCAP, primarily for Sparc32. */
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#define HWCAP_SPARC_FLUSH 1 /* CPU supports flush instruction. */ |
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#define HWCAP_SPARC_STBAR 2
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#define HWCAP_SPARC_SWAP 4
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#define HWCAP_SPARC_MULDIV 8
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#define HWCAP_SPARC_V9 16
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#define HWCAP_SPARC_ULTRA3 32
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/*
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* 68k ELF relocation types
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*/
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#define R_68K_NONE 0
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#define R_68K_32 1
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#define R_68K_16 2
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#define R_68K_8 3
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#define R_68K_PC32 4
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#define R_68K_PC16 5
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#define R_68K_PC8 6
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#define R_68K_GOT32 7
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#define R_68K_GOT16 8
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#define R_68K_GOT8 9
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#define R_68K_GOT32O 10
|
|
363 |
#define R_68K_GOT16O 11
|
|
364 |
#define R_68K_GOT8O 12
|
|
365 |
#define R_68K_PLT32 13
|
|
366 |
#define R_68K_PLT16 14
|
|
367 |
#define R_68K_PLT8 15
|
|
368 |
#define R_68K_PLT32O 16
|
|
369 |
#define R_68K_PLT16O 17
|
|
370 |
#define R_68K_PLT8O 18
|
|
371 |
#define R_68K_COPY 19
|
|
372 |
#define R_68K_GLOB_DAT 20
|
|
373 |
#define R_68K_JMP_SLOT 21
|
|
374 |
#define R_68K_RELATIVE 22
|
|
375 |
||
376 |
/*
|
|
377 |
* Alpha ELF relocation types
|
|
378 |
*/
|
|
379 |
#define R_ALPHA_NONE 0 /* No reloc */ |
|
380 |
#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ |
|
381 |
#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ |
|
382 |
#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ |
|
383 |
#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ |
|
384 |
#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ |
|
385 |
#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ |
|
386 |
#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ |
|
387 |
#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ |
|
388 |
#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ |
|
389 |
#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ |
|
390 |
#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ |
|
391 |
#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ |
|
392 |
#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ |
|
393 |
#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ |
|
394 |
#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ |
|
395 |
#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ |
|
396 |
#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ |
|
397 |
#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ |
|
398 |
#define R_ALPHA_BRSGP 28
|
|
399 |
#define R_ALPHA_TLSGD 29
|
|
400 |
#define R_ALPHA_TLS_LDM 30
|
|
401 |
#define R_ALPHA_DTPMOD64 31
|
|
402 |
#define R_ALPHA_GOTDTPREL 32
|
|
403 |
#define R_ALPHA_DTPREL64 33
|
|
404 |
#define R_ALPHA_DTPRELHI 34
|
|
405 |
#define R_ALPHA_DTPRELLO 35
|
|
406 |
#define R_ALPHA_DTPREL16 36
|
|
407 |
#define R_ALPHA_GOTTPREL 37
|
|
408 |
#define R_ALPHA_TPREL64 38
|
|
409 |
#define R_ALPHA_TPRELHI 39
|
|
410 |
#define R_ALPHA_TPRELLO 40
|
|
411 |
#define R_ALPHA_TPREL16 41
|
|
412 |
||
413 |
#define SHF_ALPHA_GPREL 0x10000000
|
|
414 |
||
415 |
||
416 |
/* PowerPC relocations defined by the ABIs */
|
|
417 |
#define R_PPC_NONE 0
|
|
418 |
#define R_PPC_ADDR32 1 /* 32bit absolute address */ |
|
419 |
#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ |
|
420 |
#define R_PPC_ADDR16 3 /* 16bit absolute address */ |
|
421 |
#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ |
|
422 |
#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ |
|
423 |
#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ |
|
424 |
#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ |
|
425 |
#define R_PPC_ADDR14_BRTAKEN 8
|
|
426 |
#define R_PPC_ADDR14_BRNTAKEN 9
|
|
427 |
#define R_PPC_REL24 10 /* PC relative 26 bit */ |
|
428 |
#define R_PPC_REL14 11 /* PC relative 16 bit */ |
|
429 |
#define R_PPC_REL14_BRTAKEN 12
|
|
430 |
#define R_PPC_REL14_BRNTAKEN 13
|
|
431 |
#define R_PPC_GOT16 14
|
|
432 |
#define R_PPC_GOT16_LO 15
|
|
433 |
#define R_PPC_GOT16_HI 16
|
|
434 |
#define R_PPC_GOT16_HA 17
|
|
435 |
#define R_PPC_PLTREL24 18
|
|
436 |
#define R_PPC_COPY 19
|
|
437 |
#define R_PPC_GLOB_DAT 20
|
|
438 |
#define R_PPC_JMP_SLOT 21
|
|
439 |
#define R_PPC_RELATIVE 22
|
|
440 |
#define R_PPC_LOCAL24PC 23
|
|
441 |
#define R_PPC_UADDR32 24
|
|
442 |
#define R_PPC_UADDR16 25
|
|
443 |
#define R_PPC_REL32 26
|
|
444 |
#define R_PPC_PLT32 27
|
|
445 |
#define R_PPC_PLTREL32 28
|
|
446 |
#define R_PPC_PLT16_LO 29
|
|
447 |
#define R_PPC_PLT16_HI 30
|
|
448 |
#define R_PPC_PLT16_HA 31
|
|
449 |
#define R_PPC_SDAREL16 32
|
|
450 |
#define R_PPC_SECTOFF 33
|
|
451 |
#define R_PPC_SECTOFF_LO 34
|
|
452 |
#define R_PPC_SECTOFF_HI 35
|
|
453 |
#define R_PPC_SECTOFF_HA 36
|
|
454 |
/* Keep this the last entry. */
|
|
455 |
#define R_PPC_NUM 37
|
|
456 |
||
457 |
/* ARM specific declarations */
|
|
458 |
||
459 |
/* Processor specific flags for the ELF header e_flags field. */
|
|
460 |
#define EF_ARM_RELEXEC 0x01
|
|
461 |
#define EF_ARM_HASENTRY 0x02
|
|
462 |
#define EF_ARM_INTERWORK 0x04
|
|
463 |
#define EF_ARM_APCS_26 0x08
|
|
464 |
#define EF_ARM_APCS_FLOAT 0x10
|
|
465 |
#define EF_ARM_PIC 0x20
|
|
466 |
#define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use */ |
|
467 |
#define EF_NEW_ABI 0x80
|
|
468 |
#define EF_OLD_ABI 0x100
|
|
469 |
||
470 |
/* Additional symbol types for Thumb */
|
|
471 |
#define STT_ARM_TFUNC 0xd
|
|
472 |
||
473 |
/* ARM-specific values for sh_flags */
|
|
474 |
#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ |
|
475 |
#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined |
|
476 |
in the input to a link step */
|
|
477 |
||
478 |
/* ARM-specific program header flags */
|
|
479 |
#define PF_ARM_SB 0x10000000 /* Segment contains the location |
|
480 |
addressed by the static base */
|
|
481 |
||
482 |
/* ARM relocs. */
|
|
483 |
#define R_ARM_NONE 0 /* No reloc */ |
|
484 |
#define R_ARM_PC24 1 /* PC relative 26 bit branch */ |
|
485 |
#define R_ARM_ABS32 2 /* Direct 32 bit */ |
|
486 |
#define R_ARM_REL32 3 /* PC relative 32 bit */ |
|
487 |
#define R_ARM_PC13 4
|
|
488 |
#define R_ARM_ABS16 5 /* Direct 16 bit */ |
|
489 |
#define R_ARM_ABS12 6 /* Direct 12 bit */ |
|
490 |
#define R_ARM_THM_ABS5 7
|
|
491 |
#define R_ARM_ABS8 8 /* Direct 8 bit */ |
|
492 |
#define R_ARM_SBREL32 9
|
|
493 |
#define R_ARM_THM_PC22 10
|
|
494 |
#define R_ARM_THM_PC8 11
|
|
495 |
#define R_ARM_AMP_VCALL9 12
|
|
496 |
#define R_ARM_SWI24 13
|
|
497 |
#define R_ARM_THM_SWI8 14
|
|
498 |
#define R_ARM_XPC25 15
|
|
499 |
#define R_ARM_THM_XPC22 16
|
|
500 |
#define R_ARM_COPY 20 /* Copy symbol at runtime */ |
|
501 |
#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ |
|
502 |
#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ |
|
503 |
#define R_ARM_RELATIVE 23 /* Adjust by program base */ |
|
504 |
#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ |
|
505 |
#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ |
|
506 |
#define R_ARM_GOT32 26 /* 32 bit GOT entry */ |
|
507 |
#define R_ARM_PLT32 27 /* 32 bit PLT address */ |
|
2062
by pbrook
Rewrite Arm host support. |
508 |
#define R_ARM_CALL 28
|
509 |
#define R_ARM_JUMP24 29
|
|
75
by bellard
more cpu support |
510 |
#define R_ARM_GNU_VTENTRY 100
|
511 |
#define R_ARM_GNU_VTINHERIT 101
|
|
512 |
#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ |
|
513 |
#define R_ARM_THM_PC9 103 /* thumb conditional branch */ |
|
514 |
#define R_ARM_RXPC25 249
|
|
515 |
#define R_ARM_RSBREL32 250
|
|
516 |
#define R_ARM_THM_RPC22 251
|
|
517 |
#define R_ARM_RREL32 252
|
|
518 |
#define R_ARM_RABS22 253
|
|
519 |
#define R_ARM_RPC24 254
|
|
520 |
#define R_ARM_RBASE 255
|
|
521 |
/* Keep this the last entry. */
|
|
522 |
#define R_ARM_NUM 256
|
|
523 |
||
524 |
/* s390 relocations defined by the ABIs */
|
|
525 |
#define R_390_NONE 0 /* No reloc. */ |
|
526 |
#define R_390_8 1 /* Direct 8 bit. */ |
|
527 |
#define R_390_12 2 /* Direct 12 bit. */ |
|
528 |
#define R_390_16 3 /* Direct 16 bit. */ |
|
529 |
#define R_390_32 4 /* Direct 32 bit. */ |
|
530 |
#define R_390_PC32 5 /* PC relative 32 bit. */ |
|
531 |
#define R_390_GOT12 6 /* 12 bit GOT offset. */ |
|
532 |
#define R_390_GOT32 7 /* 32 bit GOT offset. */ |
|
533 |
#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ |
|
534 |
#define R_390_COPY 9 /* Copy symbol at runtime. */ |
|
535 |
#define R_390_GLOB_DAT 10 /* Create GOT entry. */ |
|
536 |
#define R_390_JMP_SLOT 11 /* Create PLT entry. */ |
|
537 |
#define R_390_RELATIVE 12 /* Adjust by program base. */ |
|
538 |
#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ |
|
539 |
#define R_390_GOTPC 14 /* 32 bit PC rel. offset to GOT. */ |
|
540 |
#define R_390_GOT16 15 /* 16 bit GOT offset. */ |
|
541 |
#define R_390_PC16 16 /* PC relative 16 bit. */ |
|
542 |
#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ |
|
543 |
#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ |
|
544 |
#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ |
|
545 |
#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ |
|
546 |
#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ |
|
547 |
#define R_390_64 22 /* Direct 64 bit. */ |
|
548 |
#define R_390_PC64 23 /* PC relative 64 bit. */ |
|
549 |
#define R_390_GOT64 24 /* 64 bit GOT offset. */ |
|
550 |
#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ |
|
551 |
#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ |
|
552 |
#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ |
|
553 |
#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ |
|
554 |
#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ |
|
555 |
#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ |
|
556 |
#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ |
|
557 |
#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ |
|
558 |
#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ |
|
559 |
#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ |
|
560 |
#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ |
|
561 |
#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ |
|
562 |
#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ |
|
563 |
#define R_390_TLS_GDCALL 38 /* Tag for function call in general |
|
564 |
dynamic TLS code. */
|
|
565 |
#define R_390_TLS_LDCALL 39 /* Tag for function call in local |
|
566 |
dynamic TLS code. */
|
|
567 |
#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic |
|
568 |
thread local data. */
|
|
569 |
#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic |
|
570 |
thread local data. */
|
|
571 |
#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS |
|
572 |
block offset. */
|
|
573 |
#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS |
|
574 |
block offset. */
|
|
575 |
#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS |
|
576 |
block offset. */
|
|
577 |
#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic |
|
578 |
thread local data in LD code. */
|
|
579 |
#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic |
|
580 |
thread local data in LD code. */
|
|
581 |
#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for |
|
582 |
negated static TLS block offset. */
|
|
583 |
#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for |
|
584 |
negated static TLS block offset. */
|
|
585 |
#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for |
|
586 |
negated static TLS block offset. */
|
|
587 |
#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to |
|
588 |
static TLS block. */
|
|
589 |
#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to |
|
590 |
static TLS block. */
|
|
591 |
#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS |
|
592 |
block. */
|
|
593 |
#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS |
|
594 |
block. */
|
|
595 |
#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ |
|
596 |
#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ |
|
597 |
#define R_390_TLS_TPOFF 56 /* Negate offset in static TLS |
|
598 |
block. */
|
|
599 |
/* Keep this the last entry. */
|
|
600 |
#define R_390_NUM 57
|
|
601 |
||
602 |
/* x86-64 relocation types */
|
|
603 |
#define R_X86_64_NONE 0 /* No reloc */ |
|
604 |
#define R_X86_64_64 1 /* Direct 64 bit */ |
|
605 |
#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ |
|
606 |
#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ |
|
607 |
#define R_X86_64_PLT32 4 /* 32 bit PLT address */ |
|
608 |
#define R_X86_64_COPY 5 /* Copy symbol at runtime */ |
|
609 |
#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ |
|
610 |
#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ |
|
611 |
#define R_X86_64_RELATIVE 8 /* Adjust by program base */ |
|
612 |
#define R_X86_64_GOTPCREL 9 /* 32 bit signed pc relative |
|
613 |
offset to GOT */
|
|
614 |
#define R_X86_64_32 10 /* Direct 32 bit zero extended */ |
|
615 |
#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ |
|
616 |
#define R_X86_64_16 12 /* Direct 16 bit zero extended */ |
|
617 |
#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ |
|
618 |
#define R_X86_64_8 14 /* Direct 8 bit sign extended */ |
|
619 |
#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ |
|
620 |
||
621 |
#define R_X86_64_NUM 16
|
|
622 |
||
623 |
/* Legal values for e_flags field of Elf64_Ehdr. */
|
|
624 |
||
625 |
#define EF_ALPHA_32BIT 1 /* All addresses are below 2GB */ |
|
626 |
||
627 |
/* HPPA specific definitions. */
|
|
628 |
||
629 |
/* Legal values for e_flags field of Elf32_Ehdr. */
|
|
630 |
||
631 |
#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ |
|
632 |
#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ |
|
633 |
#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ |
|
634 |
#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ |
|
635 |
#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch |
|
636 |
prediction. */
|
|
637 |
#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ |
|
638 |
#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ |
|
639 |
||
640 |
/* Defined values for `e_flags & EF_PARISC_ARCH' are: */
|
|
641 |
||
642 |
#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ |
|
643 |
#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ |
|
644 |
#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ |
|
645 |
||
646 |
/* Additional section indeces. */
|
|
647 |
||
648 |
#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared |
|
649 |
symbols in ANSI C. */
|
|
650 |
#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ |
|
651 |
||
652 |
/* Legal values for sh_type field of Elf32_Shdr. */
|
|
653 |
||
654 |
#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ |
|
655 |
#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ |
|
656 |
#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ |
|
657 |
||
658 |
/* Legal values for sh_flags field of Elf32_Shdr. */
|
|
659 |
||
660 |
#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ |
|
661 |
#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ |
|
662 |
#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ |
|
663 |
||
664 |
/* Legal values for ST_TYPE subfield of st_info (symbol type). */
|
|
665 |
||
666 |
#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ |
|
667 |
||
668 |
#define STT_HP_OPAQUE (STT_LOOS + 0x1)
|
|
669 |
#define STT_HP_STUB (STT_LOOS + 0x2)
|
|
670 |
||
671 |
/* HPPA relocs. */
|
|
672 |
||
673 |
#define R_PARISC_NONE 0 /* No reloc. */ |
|
674 |
#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ |
|
675 |
#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ |
|
676 |
#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ |
|
677 |
#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ |
|
678 |
#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ |
|
679 |
#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ |
|
680 |
#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ |
|
681 |
#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ |
|
682 |
#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ |
|
683 |
#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ |
|
684 |
#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ |
|
685 |
#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ |
|
686 |
#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ |
|
687 |
#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ |
|
688 |
#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ |
|
689 |
#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ |
|
690 |
#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ |
|
691 |
#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ |
|
692 |
#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ |
|
693 |
#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ |
|
694 |
#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ |
|
695 |
#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ |
|
696 |
#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ |
|
697 |
#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ |
|
698 |
#define R_PARISC_FPTR64 64 /* 64 bits function address. */ |
|
699 |
#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ |
|
700 |
#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ |
|
701 |
#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ |
|
702 |
#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ |
|
703 |
#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ |
|
704 |
#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ |
|
705 |
#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ |
|
706 |
#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ |
|
707 |
#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ |
|
708 |
#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ |
|
709 |
#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ |
|
710 |
#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ |
|
711 |
#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ |
|
712 |
#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ |
|
713 |
#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ |
|
714 |
#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ |
|
715 |
#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ |
|
716 |
#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ |
|
717 |
#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ |
|
718 |
#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ |
|
719 |
#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ |
|
720 |
#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ |
|
721 |
#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ |
|
722 |
#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ |
|
723 |
#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ |
|
724 |
#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ |
|
725 |
#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ |
|
726 |
#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ |
|
727 |
#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ |
|
728 |
#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ |
|
729 |
#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ |
|
730 |
#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ |
|
731 |
#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ |
|
732 |
#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ |
|
733 |
#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ |
|
734 |
#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ |
|
735 |
#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ |
|
736 |
#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ |
|
737 |
#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ |
|
738 |
#define R_PARISC_LORESERVE 128
|
|
739 |
#define R_PARISC_COPY 128 /* Copy relocation. */ |
|
740 |
#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ |
|
741 |
#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ |
|
742 |
#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ |
|
743 |
#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ |
|
744 |
#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ |
|
745 |
#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ |
|
746 |
#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ |
|
747 |
#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ |
|
748 |
#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ |
|
749 |
#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ |
|
750 |
#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ |
|
751 |
#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ |
|
752 |
#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ |
|
753 |
#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ |
|
754 |
#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ |
|
755 |
#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ |
|
756 |
#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ |
|
757 |
#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ |
|
758 |
#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ |
|
759 |
#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ |
|
760 |
#define R_PARISC_HIRESERVE 255
|
|
761 |
||
762 |
/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */
|
|
763 |
||
764 |
#define PT_HP_TLS (PT_LOOS + 0x0)
|
|
765 |
#define PT_HP_CORE_NONE (PT_LOOS + 0x1)
|
|
766 |
#define PT_HP_CORE_VERSION (PT_LOOS + 0x2)
|
|
767 |
#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3)
|
|
768 |
#define PT_HP_CORE_COMM (PT_LOOS + 0x4)
|
|
769 |
#define PT_HP_CORE_PROC (PT_LOOS + 0x5)
|
|
770 |
#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6)
|
|
771 |
#define PT_HP_CORE_STACK (PT_LOOS + 0x7)
|
|
772 |
#define PT_HP_CORE_SHM (PT_LOOS + 0x8)
|
|
773 |
#define PT_HP_CORE_MMF (PT_LOOS + 0x9)
|
|
774 |
#define PT_HP_PARALLEL (PT_LOOS + 0x10)
|
|
775 |
#define PT_HP_FASTBIND (PT_LOOS + 0x11)
|
|
776 |
#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12)
|
|
777 |
#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13)
|
|
778 |
#define PT_HP_STACK (PT_LOOS + 0x14)
|
|
779 |
||
780 |
#define PT_PARISC_ARCHEXT 0x70000000
|
|
781 |
#define PT_PARISC_UNWIND 0x70000001
|
|
782 |
||
783 |
/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */
|
|
784 |
||
785 |
#define PF_PARISC_SBP 0x08000000
|
|
786 |
||
787 |
#define PF_HP_PAGE_SIZE 0x00100000
|
|
788 |
#define PF_HP_FAR_SHARED 0x00200000
|
|
789 |
#define PF_HP_NEAR_SHARED 0x00400000
|
|
790 |
#define PF_HP_CODE 0x01000000
|
|
791 |
#define PF_HP_MODIFY 0x02000000
|
|
792 |
#define PF_HP_LAZYSWAP 0x04000000
|
|
793 |
#define PF_HP_SBP 0x08000000
|
|
794 |
||
113
by bellard
ia64 support |
795 |
/* IA-64 specific declarations. */
|
796 |
||
797 |
/* Processor specific flags for the Ehdr e_flags field. */
|
|
798 |
#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ |
|
799 |
#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ |
|
800 |
#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ |
|
801 |
||
802 |
/* Processor specific values for the Phdr p_type field. */
|
|
803 |
#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ |
|
804 |
#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ |
|
805 |
||
806 |
/* Processor specific flags for the Phdr p_flags field. */
|
|
807 |
#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ |
|
808 |
||
809 |
/* Processor specific values for the Shdr sh_type field. */
|
|
810 |
#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ |
|
811 |
#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ |
|
812 |
||
813 |
/* Processor specific flags for the Shdr sh_flags field. */
|
|
814 |
#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ |
|
815 |
#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ |
|
816 |
||
817 |
/* Processor specific values for the Dyn d_tag field. */
|
|
818 |
#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0)
|
|
819 |
#define DT_IA_64_NUM 1
|
|
820 |
||
821 |
/* IA-64 relocations. */
|
|
822 |
#define R_IA64_NONE 0x00 /* none */ |
|
823 |
#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ |
|
824 |
#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ |
|
825 |
#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ |
|
826 |
#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ |
|
827 |
#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ |
|
828 |
#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ |
|
829 |
#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ |
|
830 |
#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ |
|
831 |
#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ |
|
832 |
#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ |
|
833 |
#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ |
|
834 |
#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ |
|
835 |
#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ |
|
836 |
#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ |
|
837 |
#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ |
|
838 |
#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ |
|
839 |
#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ |
|
840 |
#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ |
|
841 |
#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ |
|
842 |
#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ |
|
843 |
#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ |
|
844 |
#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ |
|
845 |
#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ |
|
846 |
#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ |
|
847 |
#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ |
|
848 |
#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ |
|
849 |
#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ |
|
850 |
#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ |
|
851 |
#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ |
|
852 |
#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ |
|
853 |
#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ |
|
854 |
#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ |
|
855 |
#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ |
|
856 |
#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ |
|
857 |
#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ |
|
858 |
#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ |
|
859 |
#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ |
|
860 |
#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ |
|
861 |
#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ |
|
862 |
#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ |
|
863 |
#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ |
|
864 |
#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ |
|
865 |
#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ |
|
866 |
#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ |
|
867 |
#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ |
|
868 |
#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ |
|
869 |
#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ |
|
870 |
#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ |
|
871 |
#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ |
|
872 |
#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ |
|
873 |
#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ |
|
874 |
#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ |
|
875 |
#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ |
|
876 |
#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ |
|
877 |
#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ |
|
878 |
#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ |
|
879 |
#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ |
|
880 |
#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ |
|
881 |
#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ |
|
882 |
#define R_IA64_COPY 0x84 /* copy relocation */ |
|
883 |
#define R_IA64_SUB 0x85 /* Addend and symbol difference */ |
|
884 |
#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ |
|
885 |
#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ |
|
886 |
#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ |
|
887 |
#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ |
|
888 |
#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ |
|
889 |
#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ |
|
890 |
#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ |
|
891 |
#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ |
|
892 |
#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ |
|
893 |
#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ |
|
894 |
#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ |
|
895 |
#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ |
|
896 |
#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ |
|
897 |
#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ |
|
898 |
#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ |
|
899 |
#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ |
|
900 |
#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ |
|
901 |
#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ |
|
902 |
#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ |
|
75
by bellard
more cpu support |
903 |
|
2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
904 |
typedef struct elf32_rel { |
905 |
Elf32_Addr r_offset; |
|
906 |
Elf32_Word r_info; |
|
907 |
} Elf32_Rel; |
|
908 |
||
909 |
typedef struct elf64_rel { |
|
75
by bellard
more cpu support |
910 |
Elf64_Addr r_offset; /* Location at which to apply the action */ |
911 |
Elf64_Xword r_info; /* index and type of relocation */ |
|
2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
912 |
} Elf64_Rel; |
913 |
||
914 |
typedef struct elf32_rela{ |
|
915 |
Elf32_Addr r_offset; |
|
916 |
Elf32_Word r_info; |
|
917 |
Elf32_Sword r_addend; |
|
918 |
} Elf32_Rela; |
|
919 |
||
920 |
typedef struct elf64_rela { |
|
75
by bellard
more cpu support |
921 |
Elf64_Addr r_offset; /* Location at which to apply the action */ |
922 |
Elf64_Xword r_info; /* index and type of relocation */ |
|
923 |
Elf64_Sxword r_addend; /* Constant addend used to compute value */ |
|
2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
924 |
} Elf64_Rela; |
925 |
||
926 |
typedef struct elf32_sym{ |
|
927 |
Elf32_Word st_name; |
|
928 |
Elf32_Addr st_value; |
|
929 |
Elf32_Word st_size; |
|
930 |
unsigned char st_info; |
|
931 |
unsigned char st_other; |
|
932 |
Elf32_Half st_shndx; |
|
933 |
} Elf32_Sym; |
|
934 |
||
935 |
typedef struct elf64_sym { |
|
75
by bellard
more cpu support |
936 |
Elf64_Word st_name; /* Symbol name, index in string tbl */ |
937 |
unsigned char st_info; /* Type and binding attributes */ |
|
938 |
unsigned char st_other; /* No defined meaning, 0 */ |
|
939 |
Elf64_Half st_shndx; /* Associated section index */ |
|
940 |
Elf64_Addr st_value; /* Value of the symbol */ |
|
941 |
Elf64_Xword st_size; /* Associated symbol size */ |
|
2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
942 |
} Elf64_Sym; |
943 |
||
944 |
||
945 |
#define EI_NIDENT 16
|
|
946 |
||
947 |
typedef struct elf32_hdr{ |
|
948 |
unsigned char e_ident[EI_NIDENT]; |
|
949 |
Elf32_Half e_type; |
|
950 |
Elf32_Half e_machine; |
|
951 |
Elf32_Word e_version; |
|
952 |
Elf32_Addr e_entry; /* Entry point */ |
|
953 |
Elf32_Off e_phoff; |
|
954 |
Elf32_Off e_shoff; |
|
955 |
Elf32_Word e_flags; |
|
956 |
Elf32_Half e_ehsize; |
|
957 |
Elf32_Half e_phentsize; |
|
958 |
Elf32_Half e_phnum; |
|
959 |
Elf32_Half e_shentsize; |
|
960 |
Elf32_Half e_shnum; |
|
961 |
Elf32_Half e_shstrndx; |
|
962 |
} Elf32_Ehdr; |
|
963 |
||
964 |
typedef struct elf64_hdr { |
|
965 |
unsigned char e_ident[16]; /* ELF "magic number" */ |
|
75
by bellard
more cpu support |
966 |
Elf64_Half e_type; |
967 |
Elf64_Half e_machine; |
|
968 |
Elf64_Word e_version; |
|
969 |
Elf64_Addr e_entry; /* Entry point virtual address */ |
|
970 |
Elf64_Off e_phoff; /* Program header table file offset */ |
|
971 |
Elf64_Off e_shoff; /* Section header table file offset */ |
|
972 |
Elf64_Word e_flags; |
|
973 |
Elf64_Half e_ehsize; |
|
974 |
Elf64_Half e_phentsize; |
|
975 |
Elf64_Half e_phnum; |
|
976 |
Elf64_Half e_shentsize; |
|
977 |
Elf64_Half e_shnum; |
|
978 |
Elf64_Half e_shstrndx; |
|
2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
979 |
} Elf64_Ehdr; |
980 |
||
981 |
/* These constants define the permissions on sections in the program
|
|
982 |
header, p_flags. */
|
|
983 |
#define PF_R 0x4
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|
984 |
#define PF_W 0x2
|
|
985 |
#define PF_X 0x1
|
|
986 |
||
987 |
typedef struct elf32_phdr{ |
|
988 |
Elf32_Word p_type; |
|
989 |
Elf32_Off p_offset; |
|
990 |
Elf32_Addr p_vaddr; |
|
991 |
Elf32_Addr p_paddr; |
|
992 |
Elf32_Word p_filesz; |
|
993 |
Elf32_Word p_memsz; |
|
994 |
Elf32_Word p_flags; |
|
995 |
Elf32_Word p_align; |
|
996 |
} Elf32_Phdr; |
|
997 |
||
998 |
typedef struct elf64_phdr { |
|
75
by bellard
more cpu support |
999 |
Elf64_Word p_type; |
1000 |
Elf64_Word p_flags; |
|
1001 |
Elf64_Off p_offset; /* Segment file offset */ |
|
1002 |
Elf64_Addr p_vaddr; /* Segment virtual address */ |
|
1003 |
Elf64_Addr p_paddr; /* Segment physical address */ |
|
1004 |
Elf64_Xword p_filesz; /* Segment size in file */ |
|
1005 |
Elf64_Xword p_memsz; /* Segment size in memory */ |
|
1006 |
Elf64_Xword p_align; /* Segment alignment, file & memory */ |
|
2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
1007 |
} Elf64_Phdr; |
1008 |
||
1009 |
/* sh_type */
|
|
1010 |
#define SHT_NULL 0
|
|
1011 |
#define SHT_PROGBITS 1
|
|
1012 |
#define SHT_SYMTAB 2
|
|
1013 |
#define SHT_STRTAB 3
|
|
1014 |
#define SHT_RELA 4
|
|
1015 |
#define SHT_HASH 5
|
|
1016 |
#define SHT_DYNAMIC 6
|
|
1017 |
#define SHT_NOTE 7
|
|
1018 |
#define SHT_NOBITS 8
|
|
1019 |
#define SHT_REL 9
|
|
1020 |
#define SHT_SHLIB 10
|
|
1021 |
#define SHT_DYNSYM 11
|
|
1022 |
#define SHT_NUM 12
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|
1023 |
#define SHT_LOPROC 0x70000000
|
|
1024 |
#define SHT_HIPROC 0x7fffffff
|
|
1025 |
#define SHT_LOUSER 0x80000000
|
|
1026 |
#define SHT_HIUSER 0xffffffff
|
|
75
by bellard
more cpu support |
1027 |
#define SHT_MIPS_LIST 0x70000000
|
1028 |
#define SHT_MIPS_CONFLICT 0x70000002
|
|
1029 |
#define SHT_MIPS_GPTAB 0x70000003
|
|
1030 |
#define SHT_MIPS_UCODE 0x70000004
|
|
2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
1031 |
|
1032 |
/* sh_flags */
|
|
1033 |
#define SHF_WRITE 0x1
|
|
1034 |
#define SHF_ALLOC 0x2
|
|
1035 |
#define SHF_EXECINSTR 0x4
|
|
1036 |
#define SHF_MASKPROC 0xf0000000
|
|
75
by bellard
more cpu support |
1037 |
#define SHF_MIPS_GPREL 0x10000000
|
2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
1038 |
|
1039 |
/* special section indexes */
|
|
1040 |
#define SHN_UNDEF 0
|
|
1041 |
#define SHN_LORESERVE 0xff00
|
|
1042 |
#define SHN_LOPROC 0xff00
|
|
1043 |
#define SHN_HIPROC 0xff1f
|
|
1044 |
#define SHN_ABS 0xfff1
|
|
1045 |
#define SHN_COMMON 0xfff2
|
|
1046 |
#define SHN_HIRESERVE 0xffff
|
|
75
by bellard
more cpu support |
1047 |
#define SHN_MIPS_ACCOMON 0xff00
|
3163
by ths
find -type f | xargs sed -i 's/[\t ]$//g' # on most files |
1048 |
|
75
by bellard
more cpu support |
1049 |
typedef struct elf32_shdr { |
2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
1050 |
Elf32_Word sh_name; |
1051 |
Elf32_Word sh_type; |
|
1052 |
Elf32_Word sh_flags; |
|
1053 |
Elf32_Addr sh_addr; |
|
1054 |
Elf32_Off sh_offset; |
|
1055 |
Elf32_Word sh_size; |
|
1056 |
Elf32_Word sh_link; |
|
1057 |
Elf32_Word sh_info; |
|
1058 |
Elf32_Word sh_addralign; |
|
1059 |
Elf32_Word sh_entsize; |
|
1060 |
} Elf32_Shdr; |
|
1061 |
||
1062 |
typedef struct elf64_shdr { |
|
75
by bellard
more cpu support |
1063 |
Elf64_Word sh_name; /* Section name, index in string tbl */ |
1064 |
Elf64_Word sh_type; /* Type of section */ |
|
1065 |
Elf64_Xword sh_flags; /* Miscellaneous section attributes */ |
|
1066 |
Elf64_Addr sh_addr; /* Section virtual addr at execution */ |
|
1067 |
Elf64_Off sh_offset; /* Section file offset */ |
|
1068 |
Elf64_Xword sh_size; /* Size of section in bytes */ |
|
1069 |
Elf64_Word sh_link; /* Index of another section */ |
|
1070 |
Elf64_Word sh_info; /* Additional section information */ |
|
1071 |
Elf64_Xword sh_addralign; /* Section alignment */ |
|
1072 |
Elf64_Xword sh_entsize; /* Entry size if section holds table */ |
|
2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
1073 |
} Elf64_Shdr; |
1074 |
||
1075 |
#define EI_MAG0 0 /* e_ident[] indexes */ |
|
1076 |
#define EI_MAG1 1
|
|
1077 |
#define EI_MAG2 2
|
|
1078 |
#define EI_MAG3 3
|
|
1079 |
#define EI_CLASS 4
|
|
1080 |
#define EI_DATA 5
|
|
1081 |
#define EI_VERSION 6
|
|
1082 |
#define EI_PAD 7
|
|
1083 |
||
1084 |
#define ELFMAG0 0x7f /* EI_MAG */ |
|
1085 |
#define ELFMAG1 'E'
|
|
1086 |
#define ELFMAG2 'L'
|
|
1087 |
#define ELFMAG3 'F'
|
|
1088 |
#define ELFMAG "\177ELF"
|
|
1089 |
#define SELFMAG 4
|
|
1090 |
||
1091 |
#define ELFCLASSNONE 0 /* EI_CLASS */ |
|
1092 |
#define ELFCLASS32 1
|
|
1093 |
#define ELFCLASS64 2
|
|
1094 |
#define ELFCLASSNUM 3
|
|
1095 |
||
1096 |
#define ELFDATANONE 0 /* e_ident[EI_DATA] */ |
|
1097 |
#define ELFDATA2LSB 1
|
|
1098 |
#define ELFDATA2MSB 2
|
|
1099 |
||
1100 |
#define EV_NONE 0 /* e_version, EI_VERSION */ |
|
1101 |
#define EV_CURRENT 1
|
|
1102 |
#define EV_NUM 2
|
|
1103 |
||
1104 |
/* Notes used in ET_CORE */
|
|
1105 |
#define NT_PRSTATUS 1
|
|
1106 |
#define NT_PRFPREG 2
|
|
1107 |
#define NT_PRPSINFO 3
|
|
1108 |
#define NT_TASKSTRUCT 4
|
|
75
by bellard
more cpu support |
1109 |
#define NT_PRXFPREG 0x46e62b7f /* copied from gdb5.1/include/elf/common.h */ |
1110 |
||
2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
1111 |
|
1112 |
/* Note header in a PT_NOTE section */
|
|
1113 |
typedef struct elf32_note { |
|
1114 |
Elf32_Word n_namesz; /* Name size */ |
|
1115 |
Elf32_Word n_descsz; /* Content size */ |
|
1116 |
Elf32_Word n_type; /* Content type */ |
|
1117 |
} Elf32_Nhdr; |
|
1118 |
||
1119 |
/* Note header in a PT_NOTE section */
|
|
1120 |
typedef struct elf64_note { |
|
75
by bellard
more cpu support |
1121 |
Elf64_Word n_namesz; /* Name size */ |
1122 |
Elf64_Word n_descsz; /* Content size */ |
|
1123 |
Elf64_Word n_type; /* Content type */ |
|
2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
1124 |
} Elf64_Nhdr; |
1125 |
||
1126 |
#if ELF_CLASS == ELFCLASS32
|
|
1127 |
||
1128 |
#define elfhdr elf32_hdr
|
|
1129 |
#define elf_phdr elf32_phdr
|
|
1130 |
#define elf_note elf32_note
|
|
75
by bellard
more cpu support |
1131 |
#define elf_shdr elf32_shdr
|
101
by bellard
symbol fix |
1132 |
#define elf_sym elf32_sym
|
75
by bellard
more cpu support |
1133 |
|
1134 |
#ifdef ELF_USES_RELOCA
|
|
1135 |
# define ELF_RELOC Elf32_Rela
|
|
1136 |
#else
|
|
1137 |
# define ELF_RELOC Elf32_Rel
|
|
1138 |
#endif
|
|
1139 |
||
1140 |
#else
|
|
1141 |
||
2
by bellard
This commit was generated by cvs2svn to compensate for changes in r2, |
1142 |
#define elfhdr elf64_hdr
|
1143 |
#define elf_phdr elf64_phdr
|
|
1144 |
#define elf_note elf64_note
|
|
75
by bellard
more cpu support |
1145 |
#define elf_shdr elf64_shdr
|
101
by bellard
symbol fix |
1146 |
#define elf_sym elf64_sym
|
75
by bellard
more cpu support |
1147 |
|
1148 |
#ifdef ELF_USES_RELOCA
|
|
1149 |
# define ELF_RELOC Elf64_Rela
|
|
1150 |
#else
|
|
1151 |
# define ELF_RELOC Elf64_Rel
|
|
1152 |
#endif
|
|
1153 |
||
1154 |
#endif /* ELF_CLASS */ |
|
1155 |
||
1156 |
#ifndef ElfW
|
|
1157 |
# if ELF_CLASS == ELFCLASS32
|
|
1158 |
# define ElfW(x) Elf32_ ## x
|
|
1159 |
# define ELFW(x) ELF32_ ## x
|
|
1160 |
# else
|
|
1161 |
# define ElfW(x) Elf64_ ## x
|
|
1162 |
# define ELFW(x) ELF64_ ## x
|
|
1163 |
# endif
|
|
1164 |
#endif
|
|
1165 |
||
1166 |
||
101
by bellard
symbol fix |
1167 |
#endif /* _QEMU_ELF_H */ |