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- Committer: bellard
- Date: 2007-02-05 20:46:55 UTC
- Revision ID: git-v1:7b9c30c5eecdbfc08ce18e4d386a5486289f0f78
update
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2394 c046a42c-6fe2-441c-8c8c-71466251a162
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2394 c046a42c-6fe2-441c-8c8c-71466251a162
- files added:
- .cvsignore
- target-arm/nwfpe
- files removed:
- .gitignore
- bsd-user
- bsd-user/freebsd
- bsd-user/netbsd
- bsd-user/openbsd
- bsd-user/sparc
- bsd-user/sparc64
- gdb-xml
- linux-user/alpha
- linux-user/arm/nwfpe
- linux-user/cris
- linux-user/mips64
- linux-user/mipsn32
- linux-user/x86_64
- target-alpha
- target-cris
- tcg
- tcg/arm
- tcg/hppa
- tcg/i386
- tcg/ppc
- tcg/ppc64
- tcg/sparc
- tcg/x86_64
- tests/alpha
- tests/cris
- files modified:
- COPYING
added
removed
target-i386/translate.c
1
1
/*
2
2
* i386 translation
3
*
3
*
4
4
* Copyright (c) 2003 Fabrice Bellard
5
5
*
6
6
* This library is free software; you can redistribute it and/or
28
28
#include "cpu.h"
29
29
#include "exec-all.h"
30
30
#include "disas.h"
31
#include "helper.h"
32
#include "tcg-op.h"
31
32
/* XXX: move that elsewhere */
33
static uint16_t *gen_opc_ptr;
34
static uint32_t *gen_opparam_ptr;
33
35
34
36
#define PREFIX_REPZ 0x01
35
37
#define PREFIX_REPNZ 0x02
55
57
#define REX_B(s) 0
56
58
#endif
57
59
58
//#define MACRO_TEST 1
59
60
/* global register indexes */
61
static TCGv cpu_env, cpu_A0, cpu_cc_op, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
62
/* local temps */
63
static TCGv cpu_T[2], cpu_T3;
64
/* local register indexes (only used inside old micro ops) */
65
static TCGv cpu_tmp0, cpu_tmp1_i64, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp4, cpu_ptr0, cpu_ptr1;
66
static TCGv cpu_tmp5, cpu_tmp6;
67
68
#include "gen-icount.h"
69
70
60
#ifdef TARGET_X86_64
71
61
static int x86_64_hregs;
72
62
#endif
73
63
64
#ifdef USE_DIRECT_JUMP
65
#define TBPARAM(x)
66
#else
67
#define TBPARAM(x) (long)(x)
68
#endif
69
74
70
typedef struct DisasContext {
75
71
/* current insn context */
76
72
int override; /* -1 if no override */
99
95
int singlestep_enabled; /* "hardware" single step enabled */
100
96
int jmp_opt; /* use direct block chaining for direct jumps */
101
97
int mem_index; /* select memory access functions */
102
uint64_t flags; /* all execution flags */
98
int flags; /* all execution flags */
103
99
struct TranslationBlock *tb;
104
100
int popl_esp_hack; /* for correct popl with esp base handling */
105
101
int rip_offset; /* only used in x86_64, but left for simplicity */
106
102
int cpuid_features;
107
103
int cpuid_ext_features;
108
int cpuid_ext2_features;
109
int cpuid_ext3_features;
110
104
} DisasContext;
111
105
112
106
static void gen_eob(DisasContext *s);
115
109
116
110
/* i386 arith/logic operations */
117
111
enum {
118
OP_ADDL,
119
OP_ORL,
120
OP_ADCL,
112
OP_ADDL,
113
OP_ORL,
114
OP_ADCL,
121
115
OP_SBBL,
122
OP_ANDL,
123
OP_SUBL,
124
OP_XORL,
116
OP_ANDL,
117
OP_SUBL,
118
OP_XORL,
125
119
OP_CMPL,
126
120
};
127
121
128
122
/* i386 shift ops */
129
123
enum {
130
OP_ROL,
131
OP_ROR,
132
OP_RCL,
133
OP_RCR,
134
OP_SHL,
135
OP_SHR,
124
OP_ROL,
125
OP_ROR,
126
OP_RCL,
127
OP_RCR,
128
OP_SHL,
129
OP_SHR,
136
130
OP_SHL1, /* undocumented */
137
131
OP_SAR = 7,
138
132
};
139
133
140
134
enum {
141
JCC_O,
142
JCC_B,
143
JCC_Z,
144
JCC_BE,
145
JCC_S,
146
JCC_P,
147
JCC_L,
148
JCC_LE,
135
#define DEF(s, n, copy_size) INDEX_op_ ## s,
136
#include "opc.h"
137
#undef DEF
138
NB_OPS,
149
139
};
150
140
141
#include "gen-op.h"
142
151
143
/* operand size */
152
144
enum {
153
145
OT_BYTE = 0,
154
146
OT_WORD,
155
OT_LONG,
147
OT_LONG,
156
148
OT_QUAD,
157
149
};
158
150
172
164
OR_A0, /* temporary register used when doing address evaluation */
173
165
};
174
166
175
static inline void gen_op_movl_T0_0(void)
176
{
177
tcg_gen_movi_tl(cpu_T[0], 0);
178
}
179
180
static inline void gen_op_movl_T0_im(int32_t val)
181
{
182
tcg_gen_movi_tl(cpu_T[0], val);
183
}
184
185
static inline void gen_op_movl_T0_imu(uint32_t val)
186
{
187
tcg_gen_movi_tl(cpu_T[0], val);
188
}
189
190
static inline void gen_op_movl_T1_im(int32_t val)
191
{
192
tcg_gen_movi_tl(cpu_T[1], val);
193
}
194
195
static inline void gen_op_movl_T1_imu(uint32_t val)
196
{
197
tcg_gen_movi_tl(cpu_T[1], val);
198
}
199
200
static inline void gen_op_movl_A0_im(uint32_t val)
201
{
202
tcg_gen_movi_tl(cpu_A0, val);
203
}
204
205
#ifdef TARGET_X86_64
206
static inline void gen_op_movq_A0_im(int64_t val)
207
{
208
tcg_gen_movi_tl(cpu_A0, val);
209
}
210
#endif
211
212
static inline void gen_movtl_T0_im(target_ulong val)
213
{
214
tcg_gen_movi_tl(cpu_T[0], val);
215
}
216
217
static inline void gen_movtl_T1_im(target_ulong val)
218
{
219
tcg_gen_movi_tl(cpu_T[1], val);
220
}
221
222
static inline void gen_op_andl_T0_ffff(void)
223
{
224
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
225
}
226
227
static inline void gen_op_andl_T0_im(uint32_t val)
228
{
229
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
230
}
231
232
static inline void gen_op_movl_T0_T1(void)
233
{
234
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
235
}
236
237
static inline void gen_op_andl_A0_ffff(void)
238
{
239
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
240
}
241
242
167
#ifdef TARGET_X86_64
243
168
244
169
#define NB_OP_SIZES 4
245
170
171
#define DEF_REGS(prefix, suffix) \
172
prefix ## EAX ## suffix,\
173
prefix ## ECX ## suffix,\
174
prefix ## EDX ## suffix,\
175
prefix ## EBX ## suffix,\
176
prefix ## ESP ## suffix,\
177
prefix ## EBP ## suffix,\
178
prefix ## ESI ## suffix,\
179
prefix ## EDI ## suffix,\
180
prefix ## R8 ## suffix,\
181
prefix ## R9 ## suffix,\
182
prefix ## R10 ## suffix,\
183
prefix ## R11 ## suffix,\
184
prefix ## R12 ## suffix,\
185
prefix ## R13 ## suffix,\
186
prefix ## R14 ## suffix,\
187
prefix ## R15 ## suffix,
188
189
#define DEF_BREGS(prefixb, prefixh, suffix) \
190
\
191
static void prefixb ## ESP ## suffix ## _wrapper(void) \
192
{ \
193
if (x86_64_hregs) \
194
prefixb ## ESP ## suffix (); \
195
else \
196
prefixh ## EAX ## suffix (); \
197
} \
198
\
199
static void prefixb ## EBP ## suffix ## _wrapper(void) \
200
{ \
201
if (x86_64_hregs) \
202
prefixb ## EBP ## suffix (); \
203
else \
204
prefixh ## ECX ## suffix (); \
205
} \
206
\
207
static void prefixb ## ESI ## suffix ## _wrapper(void) \
208
{ \
209
if (x86_64_hregs) \
210
prefixb ## ESI ## suffix (); \
211
else \
212
prefixh ## EDX ## suffix (); \
213
} \
214
\
215
static void prefixb ## EDI ## suffix ## _wrapper(void) \
216
{ \
217
if (x86_64_hregs) \
218
prefixb ## EDI ## suffix (); \
219
else \
220
prefixh ## EBX ## suffix (); \
221
}
222
223
DEF_BREGS(gen_op_movb_, gen_op_movh_, _T0)
224
DEF_BREGS(gen_op_movb_, gen_op_movh_, _T1)
225
DEF_BREGS(gen_op_movl_T0_, gen_op_movh_T0_, )
226
DEF_BREGS(gen_op_movl_T1_, gen_op_movh_T1_, )
227
246
228
#else /* !TARGET_X86_64 */
247
229
248
230
#define NB_OP_SIZES 3
249
231
232
#define DEF_REGS(prefix, suffix) \
233
prefix ## EAX ## suffix,\
234
prefix ## ECX ## suffix,\
235
prefix ## EDX ## suffix,\
236
prefix ## EBX ## suffix,\
237
prefix ## ESP ## suffix,\
238
prefix ## EBP ## suffix,\
239
prefix ## ESI ## suffix,\
240
prefix ## EDI ## suffix,
241
250
242
#endif /* !TARGET_X86_64 */
251
243
252
#if defined(WORDS_BIGENDIAN)
253
#define REG_B_OFFSET (sizeof(target_ulong) - 1)
254
#define REG_H_OFFSET (sizeof(target_ulong) - 2)
255
#define REG_W_OFFSET (sizeof(target_ulong) - 2)
256
#define REG_L_OFFSET (sizeof(target_ulong) - 4)
257
#define REG_LH_OFFSET (sizeof(target_ulong) - 8)
258
#else
259
#define REG_B_OFFSET 0
260
#define REG_H_OFFSET 1
261
#define REG_W_OFFSET 0
262
#define REG_L_OFFSET 0
263
#define REG_LH_OFFSET 4
264
#endif
265
266
static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
267
{
268
switch(ot) {
269
case OT_BYTE:
270
if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
271
tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);
272
} else {
273
tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
274
}
275
break;
276
case OT_WORD:
277
tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
278
break;
279
#ifdef TARGET_X86_64
280
case OT_LONG:
281
tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
282
/* high part of register set to zero */
283
tcg_gen_movi_tl(cpu_tmp0, 0);
284
tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
285
break;
286
default:
287
case OT_QUAD:
288
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
289
break;
290
#else
291
default:
292
case OT_LONG:
293
tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
294
break;
295
#endif
296
}
297
}
298
299
static inline void gen_op_mov_reg_T0(int ot, int reg)
300
{
301
gen_op_mov_reg_v(ot, reg, cpu_T[0]);
302
}
303
304
static inline void gen_op_mov_reg_T1(int ot, int reg)
305
{
306
gen_op_mov_reg_v(ot, reg, cpu_T[1]);
307
}
308
309
static inline void gen_op_mov_reg_A0(int size, int reg)
310
{
311
switch(size) {
312
case 0:
313
tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
314
break;
315
#ifdef TARGET_X86_64
316
case 1:
317
tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
318
/* high part of register set to zero */
319
tcg_gen_movi_tl(cpu_tmp0, 0);
320
tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
321
break;
322
default:
323
case 2:
324
tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
325
break;
326
#else
327
default:
328
case 1:
329
tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
330
break;
331
#endif
332
}
333
}
334
335
static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
336
{
337
switch(ot) {
338
case OT_BYTE:
339
if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
340
goto std_case;
341
} else {
342
tcg_gen_ld8u_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
343
}
344
break;
345
default:
346
std_case:
347
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
348
break;
349
}
350
}
351
352
static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
353
{
354
gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
355
}
356
357
static inline void gen_op_movl_A0_reg(int reg)
358
{
359
tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
360
}
361
362
static inline void gen_op_addl_A0_im(int32_t val)
363
{
364
tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
365
#ifdef TARGET_X86_64
366
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
367
#endif
368
}
369
370
#ifdef TARGET_X86_64
371
static inline void gen_op_addq_A0_im(int64_t val)
372
{
373
tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
374
}
375
#endif
376
377
static void gen_add_A0_im(DisasContext *s, int val)
378
{
379
#ifdef TARGET_X86_64
380
if (CODE64(s))
381
gen_op_addq_A0_im(val);
382
else
383
#endif
384
gen_op_addl_A0_im(val);
385
}
386
387
static inline void gen_op_addl_T0_T1(void)
388
{
389
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
390
}
391
392
static inline void gen_op_jmp_T0(void)
393
{
394
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
395
}
396
397
static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
398
{
399
switch(size) {
400
case 0:
401
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
402
tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
403
tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
404
break;
405
case 1:
406
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
407
tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
408
#ifdef TARGET_X86_64
409
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
410
#endif
411
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
412
break;
413
#ifdef TARGET_X86_64
414
case 2:
415
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
416
tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
417
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
418
break;
419
#endif
420
}
421
}
422
423
static inline void gen_op_add_reg_T0(int size, int reg)
424
{
425
switch(size) {
426
case 0:
427
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
428
tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
429
tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
430
break;
431
case 1:
432
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
433
tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
434
#ifdef TARGET_X86_64
435
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
436
#endif
437
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
438
break;
439
#ifdef TARGET_X86_64
440
case 2:
441
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
442
tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
443
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
444
break;
445
#endif
446
}
447
}
448
449
static inline void gen_op_set_cc_op(int32_t val)
450
{
451
tcg_gen_movi_i32(cpu_cc_op, val);
452
}
453
454
static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
455
{
456
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
457
if (shift != 0)
458
tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
459
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
460
#ifdef TARGET_X86_64
461
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
462
#endif
463
}
464
465
static inline void gen_op_movl_A0_seg(int reg)
466
{
467
tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
468
}
469
470
static inline void gen_op_addl_A0_seg(int reg)
471
{
472
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
473
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
474
#ifdef TARGET_X86_64
475
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
476
#endif
477
}
478
479
#ifdef TARGET_X86_64
480
static inline void gen_op_movq_A0_seg(int reg)
481
{
482
tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
483
}
484
485
static inline void gen_op_addq_A0_seg(int reg)
486
{
487
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
488
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
489
}
490
491
static inline void gen_op_movq_A0_reg(int reg)
492
{
493
tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
494
}
495
496
static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
497
{
498
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
499
if (shift != 0)
500
tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
501
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
502
}
503
#endif
504
505
static inline void gen_op_lds_T0_A0(int idx)
506
{
507
int mem_index = (idx >> 2) - 1;
508
switch(idx & 3) {
509
case 0:
510
tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
511
break;
512
case 1:
513
tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
514
break;
515
default:
516
case 2:
517
tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
518
break;
519
}
520
}
521
522
static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
523
{
524
int mem_index = (idx >> 2) - 1;
525
switch(idx & 3) {
526
case 0:
527
tcg_gen_qemu_ld8u(t0, a0, mem_index);
528
break;
529
case 1:
530
tcg_gen_qemu_ld16u(t0, a0, mem_index);
531
break;
532
case 2:
533
tcg_gen_qemu_ld32u(t0, a0, mem_index);
534
break;
535
default:
536
case 3:
537
tcg_gen_qemu_ld64(t0, a0, mem_index);
538
break;
539
}
540
}
541
542
/* XXX: always use ldu or lds */
543
static inline void gen_op_ld_T0_A0(int idx)
544
{
545
gen_op_ld_v(idx, cpu_T[0], cpu_A0);
546
}
547
548
static inline void gen_op_ldu_T0_A0(int idx)
549
{
550
gen_op_ld_v(idx, cpu_T[0], cpu_A0);
551
}
552
553
static inline void gen_op_ld_T1_A0(int idx)
554
{
555
gen_op_ld_v(idx, cpu_T[1], cpu_A0);
556
}
557
558
static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
559
{
560
int mem_index = (idx >> 2) - 1;
561
switch(idx & 3) {
562
case 0:
563
tcg_gen_qemu_st8(t0, a0, mem_index);
564
break;
565
case 1:
566
tcg_gen_qemu_st16(t0, a0, mem_index);
567
break;
568
case 2:
569
tcg_gen_qemu_st32(t0, a0, mem_index);
570
break;
571
default:
572
case 3:
573
tcg_gen_qemu_st64(t0, a0, mem_index);
574
break;
575
}
576
}
577
578
static inline void gen_op_st_T0_A0(int idx)
579
{
580
gen_op_st_v(idx, cpu_T[0], cpu_A0);
581
}
582
583
static inline void gen_op_st_T1_A0(int idx)
584
{
585
gen_op_st_v(idx, cpu_T[1], cpu_A0);
586
}
244
static GenOpFunc *gen_op_mov_reg_T0[NB_OP_SIZES][CPU_NB_REGS] = {
245
[OT_BYTE] = {
246
gen_op_movb_EAX_T0,
247
gen_op_movb_ECX_T0,
248
gen_op_movb_EDX_T0,
249
gen_op_movb_EBX_T0,
250
#ifdef TARGET_X86_64
251
gen_op_movb_ESP_T0_wrapper,
252
gen_op_movb_EBP_T0_wrapper,
253
gen_op_movb_ESI_T0_wrapper,
254
gen_op_movb_EDI_T0_wrapper,
255
gen_op_movb_R8_T0,
256
gen_op_movb_R9_T0,
257
gen_op_movb_R10_T0,
258
gen_op_movb_R11_T0,
259
gen_op_movb_R12_T0,
260
gen_op_movb_R13_T0,
261
gen_op_movb_R14_T0,
262
gen_op_movb_R15_T0,
263
#else
264
gen_op_movh_EAX_T0,
265
gen_op_movh_ECX_T0,
266
gen_op_movh_EDX_T0,
267
gen_op_movh_EBX_T0,
268
#endif
269
},
270
[OT_WORD] = {
271
DEF_REGS(gen_op_movw_, _T0)
272
},
273
[OT_LONG] = {
274
DEF_REGS(gen_op_movl_, _T0)
275
},
276
#ifdef TARGET_X86_64
277
[OT_QUAD] = {
278
DEF_REGS(gen_op_movq_, _T0)
279
},
280
#endif
281
};
282
283
static GenOpFunc *gen_op_mov_reg_T1[NB_OP_SIZES][CPU_NB_REGS] = {
284
[OT_BYTE] = {
285
gen_op_movb_EAX_T1,
286
gen_op_movb_ECX_T1,
287
gen_op_movb_EDX_T1,
288
gen_op_movb_EBX_T1,
289
#ifdef TARGET_X86_64
290
gen_op_movb_ESP_T1_wrapper,
291
gen_op_movb_EBP_T1_wrapper,
292
gen_op_movb_ESI_T1_wrapper,
293
gen_op_movb_EDI_T1_wrapper,
294
gen_op_movb_R8_T1,
295
gen_op_movb_R9_T1,
296
gen_op_movb_R10_T1,
297
gen_op_movb_R11_T1,
298
gen_op_movb_R12_T1,
299
gen_op_movb_R13_T1,
300
gen_op_movb_R14_T1,
301
gen_op_movb_R15_T1,
302
#else
303
gen_op_movh_EAX_T1,
304
gen_op_movh_ECX_T1,
305
gen_op_movh_EDX_T1,
306
gen_op_movh_EBX_T1,
307
#endif
308
},
309
[OT_WORD] = {
310
DEF_REGS(gen_op_movw_, _T1)
311
},
312
[OT_LONG] = {
313
DEF_REGS(gen_op_movl_, _T1)
314
},
315
#ifdef TARGET_X86_64
316
[OT_QUAD] = {
317
DEF_REGS(gen_op_movq_, _T1)
318
},
319
#endif
320
};
321
322
static GenOpFunc *gen_op_mov_reg_A0[NB_OP_SIZES - 1][CPU_NB_REGS] = {
323
[0] = {
324
DEF_REGS(gen_op_movw_, _A0)
325
},
326
[1] = {
327
DEF_REGS(gen_op_movl_, _A0)
328
},
329
#ifdef TARGET_X86_64
330
[2] = {
331
DEF_REGS(gen_op_movq_, _A0)
332
},
333
#endif
334
};
335
336
static GenOpFunc *gen_op_mov_TN_reg[NB_OP_SIZES][2][CPU_NB_REGS] =
337
{
338
[OT_BYTE] = {
339
{
340
gen_op_movl_T0_EAX,
341
gen_op_movl_T0_ECX,
342
gen_op_movl_T0_EDX,
343
gen_op_movl_T0_EBX,
344
#ifdef TARGET_X86_64
345
gen_op_movl_T0_ESP_wrapper,
346
gen_op_movl_T0_EBP_wrapper,
347
gen_op_movl_T0_ESI_wrapper,
348
gen_op_movl_T0_EDI_wrapper,
349
gen_op_movl_T0_R8,
350
gen_op_movl_T0_R9,
351
gen_op_movl_T0_R10,
352
gen_op_movl_T0_R11,
353
gen_op_movl_T0_R12,
354
gen_op_movl_T0_R13,
355
gen_op_movl_T0_R14,
356
gen_op_movl_T0_R15,
357
#else
358
gen_op_movh_T0_EAX,
359
gen_op_movh_T0_ECX,
360
gen_op_movh_T0_EDX,
361
gen_op_movh_T0_EBX,
362
#endif
363
},
364
{
365
gen_op_movl_T1_EAX,
366
gen_op_movl_T1_ECX,
367
gen_op_movl_T1_EDX,
368
gen_op_movl_T1_EBX,
369
#ifdef TARGET_X86_64
370
gen_op_movl_T1_ESP_wrapper,
371
gen_op_movl_T1_EBP_wrapper,
372
gen_op_movl_T1_ESI_wrapper,
373
gen_op_movl_T1_EDI_wrapper,
374
gen_op_movl_T1_R8,
375
gen_op_movl_T1_R9,
376
gen_op_movl_T1_R10,
377
gen_op_movl_T1_R11,
378
gen_op_movl_T1_R12,
379
gen_op_movl_T1_R13,
380
gen_op_movl_T1_R14,
381
gen_op_movl_T1_R15,
382
#else
383
gen_op_movh_T1_EAX,
384
gen_op_movh_T1_ECX,
385
gen_op_movh_T1_EDX,
386
gen_op_movh_T1_EBX,
387
#endif
388
},
389
},
390
[OT_WORD] = {
391
{
392
DEF_REGS(gen_op_movl_T0_, )
393
},
394
{
395
DEF_REGS(gen_op_movl_T1_, )
396
},
397
},
398
[OT_LONG] = {
399
{
400
DEF_REGS(gen_op_movl_T0_, )
401
},
402
{
403
DEF_REGS(gen_op_movl_T1_, )
404
},
405
},
406
#ifdef TARGET_X86_64
407
[OT_QUAD] = {
408
{
409
DEF_REGS(gen_op_movl_T0_, )
410
},
411
{
412
DEF_REGS(gen_op_movl_T1_, )
413
},
414
},
415
#endif
416
};
417
418
static GenOpFunc *gen_op_movl_A0_reg[CPU_NB_REGS] = {
419
DEF_REGS(gen_op_movl_A0_, )
420
};
421
422
static GenOpFunc *gen_op_addl_A0_reg_sN[4][CPU_NB_REGS] = {
423
[0] = {
424
DEF_REGS(gen_op_addl_A0_, )
425
},
426
[1] = {
427
DEF_REGS(gen_op_addl_A0_, _s1)
428
},
429
[2] = {
430
DEF_REGS(gen_op_addl_A0_, _s2)
431
},
432
[3] = {
433
DEF_REGS(gen_op_addl_A0_, _s3)
434
},
435
};
436
437
#ifdef TARGET_X86_64
438
static GenOpFunc *gen_op_movq_A0_reg[CPU_NB_REGS] = {
439
DEF_REGS(gen_op_movq_A0_, )
440
};
441
442
static GenOpFunc *gen_op_addq_A0_reg_sN[4][CPU_NB_REGS] = {
443
[0] = {
444
DEF_REGS(gen_op_addq_A0_, )
445
},
446
[1] = {
447
DEF_REGS(gen_op_addq_A0_, _s1)
448
},
449
[2] = {
450
DEF_REGS(gen_op_addq_A0_, _s2)
451
},
452
[3] = {
453
DEF_REGS(gen_op_addq_A0_, _s3)
454
},
455
};
456
#endif
457
458
static GenOpFunc *gen_op_cmov_reg_T1_T0[NB_OP_SIZES - 1][CPU_NB_REGS] = {
459
[0] = {
460
DEF_REGS(gen_op_cmovw_, _T1_T0)
461
},
462
[1] = {
463
DEF_REGS(gen_op_cmovl_, _T1_T0)
464
},
465
#ifdef TARGET_X86_64
466
[2] = {
467
DEF_REGS(gen_op_cmovq_, _T1_T0)
468
},
469
#endif
470
};
471
472
static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
473
NULL,
474
gen_op_orl_T0_T1,
475
NULL,
476
NULL,
477
gen_op_andl_T0_T1,
478
NULL,
479
gen_op_xorl_T0_T1,
480
NULL,
481
};
482
483
#define DEF_ARITHC(SUFFIX)\
484
{\
485
gen_op_adcb ## SUFFIX ## _T0_T1_cc,\
486
gen_op_sbbb ## SUFFIX ## _T0_T1_cc,\
487
},\
488
{\
489
gen_op_adcw ## SUFFIX ## _T0_T1_cc,\
490
gen_op_sbbw ## SUFFIX ## _T0_T1_cc,\
491
},\
492
{\
493
gen_op_adcl ## SUFFIX ## _T0_T1_cc,\
494
gen_op_sbbl ## SUFFIX ## _T0_T1_cc,\
495
},\
496
{\
497
X86_64_ONLY(gen_op_adcq ## SUFFIX ## _T0_T1_cc),\
498
X86_64_ONLY(gen_op_sbbq ## SUFFIX ## _T0_T1_cc),\
499
},
500
501
static GenOpFunc *gen_op_arithc_T0_T1_cc[4][2] = {
502
DEF_ARITHC( )
503
};
504
505
static GenOpFunc *gen_op_arithc_mem_T0_T1_cc[3 * 4][2] = {
506
DEF_ARITHC(_raw)
507
#ifndef CONFIG_USER_ONLY
508
DEF_ARITHC(_kernel)
509
DEF_ARITHC(_user)
510
#endif
511
};
512
513
static const int cc_op_arithb[8] = {
514
CC_OP_ADDB,
515
CC_OP_LOGICB,
516
CC_OP_ADDB,
517
CC_OP_SUBB,
518
CC_OP_LOGICB,
519
CC_OP_SUBB,
520
CC_OP_LOGICB,
521
CC_OP_SUBB,
522
};
523
524
#define DEF_CMPXCHG(SUFFIX)\
525
gen_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc,\
526
gen_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc,\
527
gen_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc,\
528
X86_64_ONLY(gen_op_cmpxchgq ## SUFFIX ## _T0_T1_EAX_cc),
529
530
static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[4] = {
531
DEF_CMPXCHG( )
532
};
533
534
static GenOpFunc *gen_op_cmpxchg_mem_T0_T1_EAX_cc[3 * 4] = {
535
DEF_CMPXCHG(_raw)
536
#ifndef CONFIG_USER_ONLY
537
DEF_CMPXCHG(_kernel)
538
DEF_CMPXCHG(_user)
539
#endif
540
};
541
542
#define DEF_SHIFT(SUFFIX)\
543
{\
544
gen_op_rolb ## SUFFIX ## _T0_T1_cc,\
545
gen_op_rorb ## SUFFIX ## _T0_T1_cc,\
546
gen_op_rclb ## SUFFIX ## _T0_T1_cc,\
547
gen_op_rcrb ## SUFFIX ## _T0_T1_cc,\
548
gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
549
gen_op_shrb ## SUFFIX ## _T0_T1_cc,\
550
gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
551
gen_op_sarb ## SUFFIX ## _T0_T1_cc,\
552
},\
553
{\
554
gen_op_rolw ## SUFFIX ## _T0_T1_cc,\
555
gen_op_rorw ## SUFFIX ## _T0_T1_cc,\
556
gen_op_rclw ## SUFFIX ## _T0_T1_cc,\
557
gen_op_rcrw ## SUFFIX ## _T0_T1_cc,\
558
gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
559
gen_op_shrw ## SUFFIX ## _T0_T1_cc,\
560
gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
561
gen_op_sarw ## SUFFIX ## _T0_T1_cc,\
562
},\
563
{\
564
gen_op_roll ## SUFFIX ## _T0_T1_cc,\
565
gen_op_rorl ## SUFFIX ## _T0_T1_cc,\
566
gen_op_rcll ## SUFFIX ## _T0_T1_cc,\
567
gen_op_rcrl ## SUFFIX ## _T0_T1_cc,\
568
gen_op_shll ## SUFFIX ## _T0_T1_cc,\
569
gen_op_shrl ## SUFFIX ## _T0_T1_cc,\
570
gen_op_shll ## SUFFIX ## _T0_T1_cc,\
571
gen_op_sarl ## SUFFIX ## _T0_T1_cc,\
572
},\
573
{\
574
X86_64_ONLY(gen_op_rolq ## SUFFIX ## _T0_T1_cc),\
575
X86_64_ONLY(gen_op_rorq ## SUFFIX ## _T0_T1_cc),\
576
X86_64_ONLY(gen_op_rclq ## SUFFIX ## _T0_T1_cc),\
577
X86_64_ONLY(gen_op_rcrq ## SUFFIX ## _T0_T1_cc),\
578
X86_64_ONLY(gen_op_shlq ## SUFFIX ## _T0_T1_cc),\
579
X86_64_ONLY(gen_op_shrq ## SUFFIX ## _T0_T1_cc),\
580
X86_64_ONLY(gen_op_shlq ## SUFFIX ## _T0_T1_cc),\
581
X86_64_ONLY(gen_op_sarq ## SUFFIX ## _T0_T1_cc),\
582
},
583
584
static GenOpFunc *gen_op_shift_T0_T1_cc[4][8] = {
585
DEF_SHIFT( )
586
};
587
588
static GenOpFunc *gen_op_shift_mem_T0_T1_cc[3 * 4][8] = {
589
DEF_SHIFT(_raw)
590
#ifndef CONFIG_USER_ONLY
591
DEF_SHIFT(_kernel)
592
DEF_SHIFT(_user)
593
#endif
594
};
595
596
#define DEF_SHIFTD(SUFFIX, op)\
597
{\
598
NULL,\
599
NULL,\
600
},\
601
{\
602
gen_op_shldw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
603
gen_op_shrdw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
604
},\
605
{\
606
gen_op_shldl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
607
gen_op_shrdl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
608
},\
609
{\
610
X86_64_DEF(gen_op_shldq ## SUFFIX ## _T0_T1_ ## op ## _cc,\
611
gen_op_shrdq ## SUFFIX ## _T0_T1_ ## op ## _cc,)\
612
},
613
614
static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[4][2] = {
615
DEF_SHIFTD(, im)
616
};
617
618
static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[4][2] = {
619
DEF_SHIFTD(, ECX)
620
};
621
622
static GenOpFunc1 *gen_op_shiftd_mem_T0_T1_im_cc[3 * 4][2] = {
623
DEF_SHIFTD(_raw, im)
624
#ifndef CONFIG_USER_ONLY
625
DEF_SHIFTD(_kernel, im)
626
DEF_SHIFTD(_user, im)
627
#endif
628
};
629
630
static GenOpFunc *gen_op_shiftd_mem_T0_T1_ECX_cc[3 * 4][2] = {
631
DEF_SHIFTD(_raw, ECX)
632
#ifndef CONFIG_USER_ONLY
633
DEF_SHIFTD(_kernel, ECX)
634
DEF_SHIFTD(_user, ECX)
635
#endif
636
};
637
638
static GenOpFunc *gen_op_btx_T0_T1_cc[3][4] = {
639
[0] = {
640
gen_op_btw_T0_T1_cc,
641
gen_op_btsw_T0_T1_cc,
642
gen_op_btrw_T0_T1_cc,
643
gen_op_btcw_T0_T1_cc,
644
},
645
[1] = {
646
gen_op_btl_T0_T1_cc,
647
gen_op_btsl_T0_T1_cc,
648
gen_op_btrl_T0_T1_cc,
649
gen_op_btcl_T0_T1_cc,
650
},
651
#ifdef TARGET_X86_64
652
[2] = {
653
gen_op_btq_T0_T1_cc,
654
gen_op_btsq_T0_T1_cc,
655
gen_op_btrq_T0_T1_cc,
656
gen_op_btcq_T0_T1_cc,
657
},
658
#endif
659
};
660
661
static GenOpFunc *gen_op_add_bit_A0_T1[3] = {
662
gen_op_add_bitw_A0_T1,
663
gen_op_add_bitl_A0_T1,
664
X86_64_ONLY(gen_op_add_bitq_A0_T1),
665
};
666
667
static GenOpFunc *gen_op_bsx_T0_cc[3][2] = {
668
[0] = {
669
gen_op_bsfw_T0_cc,
670
gen_op_bsrw_T0_cc,
671
},
672
[1] = {
673
gen_op_bsfl_T0_cc,
674
gen_op_bsrl_T0_cc,
675
},
676
#ifdef TARGET_X86_64
677
[2] = {
678
gen_op_bsfq_T0_cc,
679
gen_op_bsrq_T0_cc,
680
},
681
#endif
682
};
683
684
static GenOpFunc *gen_op_lds_T0_A0[3 * 4] = {
685
gen_op_ldsb_raw_T0_A0,
686
gen_op_ldsw_raw_T0_A0,
687
X86_64_ONLY(gen_op_ldsl_raw_T0_A0),
688
NULL,
689
#ifndef CONFIG_USER_ONLY
690
gen_op_ldsb_kernel_T0_A0,
691
gen_op_ldsw_kernel_T0_A0,
692
X86_64_ONLY(gen_op_ldsl_kernel_T0_A0),
693
NULL,
694
695
gen_op_ldsb_user_T0_A0,
696
gen_op_ldsw_user_T0_A0,
697
X86_64_ONLY(gen_op_ldsl_user_T0_A0),
698
NULL,
699
#endif
700
};
701
702
static GenOpFunc *gen_op_ldu_T0_A0[3 * 4] = {
703
gen_op_ldub_raw_T0_A0,
704
gen_op_lduw_raw_T0_A0,
705
NULL,
706
NULL,
707
708
#ifndef CONFIG_USER_ONLY
709
gen_op_ldub_kernel_T0_A0,
710
gen_op_lduw_kernel_T0_A0,
711
NULL,
712
NULL,
713
714
gen_op_ldub_user_T0_A0,
715
gen_op_lduw_user_T0_A0,
716
NULL,
717
NULL,
718
#endif
719
};
720
721
/* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
722
static GenOpFunc *gen_op_ld_T0_A0[3 * 4] = {
723
gen_op_ldub_raw_T0_A0,
724
gen_op_lduw_raw_T0_A0,
725
gen_op_ldl_raw_T0_A0,
726
X86_64_ONLY(gen_op_ldq_raw_T0_A0),
727
728
#ifndef CONFIG_USER_ONLY
729
gen_op_ldub_kernel_T0_A0,
730
gen_op_lduw_kernel_T0_A0,
731
gen_op_ldl_kernel_T0_A0,
732
X86_64_ONLY(gen_op_ldq_kernel_T0_A0),
733
734
gen_op_ldub_user_T0_A0,
735
gen_op_lduw_user_T0_A0,
736
gen_op_ldl_user_T0_A0,
737
X86_64_ONLY(gen_op_ldq_user_T0_A0),
738
#endif
739
};
740
741
static GenOpFunc *gen_op_ld_T1_A0[3 * 4] = {
742
gen_op_ldub_raw_T1_A0,
743
gen_op_lduw_raw_T1_A0,
744
gen_op_ldl_raw_T1_A0,
745
X86_64_ONLY(gen_op_ldq_raw_T1_A0),
746
747
#ifndef CONFIG_USER_ONLY
748
gen_op_ldub_kernel_T1_A0,
749
gen_op_lduw_kernel_T1_A0,
750
gen_op_ldl_kernel_T1_A0,
751
X86_64_ONLY(gen_op_ldq_kernel_T1_A0),
752
753
gen_op_ldub_user_T1_A0,
754
gen_op_lduw_user_T1_A0,
755
gen_op_ldl_user_T1_A0,
756
X86_64_ONLY(gen_op_ldq_user_T1_A0),
757
#endif
758
};
759
760
static GenOpFunc *gen_op_st_T0_A0[3 * 4] = {
761
gen_op_stb_raw_T0_A0,
762
gen_op_stw_raw_T0_A0,
763
gen_op_stl_raw_T0_A0,
764
X86_64_ONLY(gen_op_stq_raw_T0_A0),
765
766
#ifndef CONFIG_USER_ONLY
767
gen_op_stb_kernel_T0_A0,
768
gen_op_stw_kernel_T0_A0,
769
gen_op_stl_kernel_T0_A0,
770
X86_64_ONLY(gen_op_stq_kernel_T0_A0),
771
772
gen_op_stb_user_T0_A0,
773
gen_op_stw_user_T0_A0,
774
gen_op_stl_user_T0_A0,
775
X86_64_ONLY(gen_op_stq_user_T0_A0),
776
#endif
777
};
778
779
static GenOpFunc *gen_op_st_T1_A0[3 * 4] = {
780
NULL,
781
gen_op_stw_raw_T1_A0,
782
gen_op_stl_raw_T1_A0,
783
X86_64_ONLY(gen_op_stq_raw_T1_A0),
784
785
#ifndef CONFIG_USER_ONLY
786
NULL,
787
gen_op_stw_kernel_T1_A0,
788
gen_op_stl_kernel_T1_A0,
789
X86_64_ONLY(gen_op_stq_kernel_T1_A0),
790
791
NULL,
792
gen_op_stw_user_T1_A0,
793
gen_op_stl_user_T1_A0,
794
X86_64_ONLY(gen_op_stq_user_T1_A0),
795
#endif
796
};
587
797
588
798
static inline void gen_jmp_im(target_ulong pc)
589
799
{
590
tcg_gen_movi_tl(cpu_tmp0, pc);
591
tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
800
#ifdef TARGET_X86_64
801
if (pc == (uint32_t)pc) {
802
gen_op_movl_eip_im(pc);
803
} else if (pc == (int32_t)pc) {
804
gen_op_movq_eip_im(pc);
805
} else {
806
gen_op_movq_eip_im64(pc >> 32, pc);
807
}
808
#else
809
gen_op_movl_eip_im(pc);
810
#endif
592
811
}
593
812
594
813
static inline void gen_string_movl_A0_ESI(DisasContext *s)
599
818
#ifdef TARGET_X86_64
600
819
if (s->aflag == 2) {
601
820
if (override >= 0) {
602
gen_op_movq_A0_seg(override);
603
gen_op_addq_A0_reg_sN(0, R_ESI);
821
gen_op_movq_A0_seg(offsetof(CPUX86State,segs[override].base));
822
gen_op_addq_A0_reg_sN[0][R_ESI]();
604
823
} else {
605
gen_op_movq_A0_reg(R_ESI);
824
gen_op_movq_A0_reg[R_ESI]();
606
825
}
607
826
} else
608
827
#endif
611
830
if (s->addseg && override < 0)
612
831
override = R_DS;
613
832
if (override >= 0) {
614
gen_op_movl_A0_seg(override);
615
gen_op_addl_A0_reg_sN(0, R_ESI);
833
gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
834
gen_op_addl_A0_reg_sN[0][R_ESI]();
616
835
} else {
617
gen_op_movl_A0_reg(R_ESI);
836
gen_op_movl_A0_reg[R_ESI]();
618
837
}
619
838
} else {
620
839
/* 16 address, always override */
621
840
if (override < 0)
622
841
override = R_DS;
623
gen_op_movl_A0_reg(R_ESI);
842
gen_op_movl_A0_reg[R_ESI]();
624
843
gen_op_andl_A0_ffff();
625
gen_op_addl_A0_seg(override);
844
gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
626
845
}
627
846
}
628
847
630
849
{
631
850
#ifdef TARGET_X86_64
632
851
if (s->aflag == 2) {
633
gen_op_movq_A0_reg(R_EDI);
852
gen_op_movq_A0_reg[R_EDI]();
634
853
} else
635
854
#endif
636
855
if (s->aflag) {
637
856
if (s->addseg) {
638
gen_op_movl_A0_seg(R_ES);
639
gen_op_addl_A0_reg_sN(0, R_EDI);
857
gen_op_movl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
858
gen_op_addl_A0_reg_sN[0][R_EDI]();
640
859
} else {
641
gen_op_movl_A0_reg(R_EDI);
860
gen_op_movl_A0_reg[R_EDI]();
642
861
}
643
862
} else {
644
gen_op_movl_A0_reg(R_EDI);
863
gen_op_movl_A0_reg[R_EDI]();
645
864
gen_op_andl_A0_ffff();
646
gen_op_addl_A0_seg(R_ES);
647
}
648
}
649
650
static inline void gen_op_movl_T0_Dshift(int ot)
651
{
652
tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
653
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
654
};
655
656
static void gen_extu(int ot, TCGv reg)
657
{
658
switch(ot) {
659
case OT_BYTE:
660
tcg_gen_ext8u_tl(reg, reg);
661
break;
662
case OT_WORD:
663
tcg_gen_ext16u_tl(reg, reg);
664
break;
665
case OT_LONG:
666
tcg_gen_ext32u_tl(reg, reg);
667
break;
668
default:
669
break;
670
}
671
}
672
673
static void gen_exts(int ot, TCGv reg)
674
{
675
switch(ot) {
676
case OT_BYTE:
677
tcg_gen_ext8s_tl(reg, reg);
678
break;
679
case OT_WORD:
680
tcg_gen_ext16s_tl(reg, reg);
681
break;
682
case OT_LONG:
683
tcg_gen_ext32s_tl(reg, reg);
684
break;
685
default:
686
break;
687
}
688
}
689
690
static inline void gen_op_jnz_ecx(int size, int label1)
691
{
692
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
693
gen_extu(size + 1, cpu_tmp0);
694
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
695
}
696
697
static inline void gen_op_jz_ecx(int size, int label1)
698
{
699
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
700
gen_extu(size + 1, cpu_tmp0);
701
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
702
}
703
704
static void *helper_in_func[3] = {
705
helper_inb,
706
helper_inw,
707
helper_inl,
708
};
709
710
static void *helper_out_func[3] = {
711
helper_outb,
712
helper_outw,
713
helper_outl,
714
};
715
716
static void *gen_check_io_func[3] = {
717
helper_check_iob,
718
helper_check_iow,
719
helper_check_iol,
720
};
721
722
static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
723
uint32_t svm_flags)
724
{
725
int state_saved;
726
target_ulong next_eip;
727
728
state_saved = 0;
865
gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
866
}
867
}
868
869
static GenOpFunc *gen_op_movl_T0_Dshift[4] = {
870
gen_op_movl_T0_Dshiftb,
871
gen_op_movl_T0_Dshiftw,
872
gen_op_movl_T0_Dshiftl,
873
X86_64_ONLY(gen_op_movl_T0_Dshiftq),
874
};
875
876
static GenOpFunc1 *gen_op_jnz_ecx[3] = {
877
gen_op_jnz_ecxw,
878
gen_op_jnz_ecxl,
879
X86_64_ONLY(gen_op_jnz_ecxq),
880
};
881
882
static GenOpFunc1 *gen_op_jz_ecx[3] = {
883
gen_op_jz_ecxw,
884
gen_op_jz_ecxl,
885
X86_64_ONLY(gen_op_jz_ecxq),
886
};
887
888
static GenOpFunc *gen_op_dec_ECX[3] = {
889
gen_op_decw_ECX,
890
gen_op_decl_ECX,
891
X86_64_ONLY(gen_op_decq_ECX),
892
};
893
894
static GenOpFunc1 *gen_op_string_jnz_sub[2][4] = {
895
{
896
gen_op_jnz_subb,
897
gen_op_jnz_subw,
898
gen_op_jnz_subl,
899
X86_64_ONLY(gen_op_jnz_subq),
900
},
901
{
902
gen_op_jz_subb,
903
gen_op_jz_subw,
904
gen_op_jz_subl,
905
X86_64_ONLY(gen_op_jz_subq),
906
},
907
};
908
909
static GenOpFunc *gen_op_in_DX_T0[3] = {
910
gen_op_inb_DX_T0,
911
gen_op_inw_DX_T0,
912
gen_op_inl_DX_T0,
913
};
914
915
static GenOpFunc *gen_op_out_DX_T0[3] = {
916
gen_op_outb_DX_T0,
917
gen_op_outw_DX_T0,
918
gen_op_outl_DX_T0,
919
};
920
921
static GenOpFunc *gen_op_in[3] = {
922
gen_op_inb_T0_T1,
923
gen_op_inw_T0_T1,
924
gen_op_inl_T0_T1,
925
};
926
927
static GenOpFunc *gen_op_out[3] = {
928
gen_op_outb_T0_T1,
929
gen_op_outw_T0_T1,
930
gen_op_outl_T0_T1,
931
};
932
933
static GenOpFunc *gen_check_io_T0[3] = {
934
gen_op_check_iob_T0,
935
gen_op_check_iow_T0,
936
gen_op_check_iol_T0,
937
};
938
939
static GenOpFunc *gen_check_io_DX[3] = {
940
gen_op_check_iob_DX,
941
gen_op_check_iow_DX,
942
gen_op_check_iol_DX,
943
};
944
945
static void gen_check_io(DisasContext *s, int ot, int use_dx, target_ulong cur_eip)
946
{
729
947
if (s->pe && (s->cpl > s->iopl || s->vm86)) {
730
948
if (s->cc_op != CC_OP_DYNAMIC)
731
949
gen_op_set_cc_op(s->cc_op);
732
950
gen_jmp_im(cur_eip);
733
state_saved = 1;
734
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
735
tcg_gen_helper_0_1(gen_check_io_func[ot],
736
cpu_tmp2_i32);
737
}
738
if(s->flags & HF_SVMI_MASK) {
739
if (!state_saved) {
740
if (s->cc_op != CC_OP_DYNAMIC)
741
gen_op_set_cc_op(s->cc_op);
742
gen_jmp_im(cur_eip);
743
state_saved = 1;
744
}
745
svm_flags |= (1 << (4 + ot));
746
next_eip = s->pc - s->cs_base;
747
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
748
tcg_gen_helper_0_3(helper_svm_check_io,
749
cpu_tmp2_i32,
750
tcg_const_i32(svm_flags),
751
tcg_const_i32(next_eip - cur_eip));
951
if (use_dx)
952
gen_check_io_DX[ot]();
953
else
954
gen_check_io_T0[ot]();
752
955
}
753
956
}
754
957
755
958
static inline void gen_movs(DisasContext *s, int ot)
756
959
{
757
960
gen_string_movl_A0_ESI(s);
758
gen_op_ld_T0_A0(ot + s->mem_index);
961
gen_op_ld_T0_A0[ot + s->mem_index]();
759
962
gen_string_movl_A0_EDI(s);
760
gen_op_st_T0_A0(ot + s->mem_index);
761
gen_op_movl_T0_Dshift(ot);
762
gen_op_add_reg_T0(s->aflag, R_ESI);
763
gen_op_add_reg_T0(s->aflag, R_EDI);
963
gen_op_st_T0_A0[ot + s->mem_index]();
964
gen_op_movl_T0_Dshift[ot]();
965
#ifdef TARGET_X86_64
966
if (s->aflag == 2) {
967
gen_op_addq_ESI_T0();
968
gen_op_addq_EDI_T0();
969
} else
970
#endif
971
if (s->aflag) {
972
gen_op_addl_ESI_T0();
973
gen_op_addl_EDI_T0();
974
} else {
975
gen_op_addw_ESI_T0();
976
gen_op_addw_EDI_T0();
977
}
764
978
}
765
979
766
980
static inline void gen_update_cc_op(DisasContext *s)
771
985
}
772
986
}
773
987
774
static void gen_op_update1_cc(void)
775
{
776
tcg_gen_discard_tl(cpu_cc_src);
777
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
778
}
779
780
static void gen_op_update2_cc(void)
781
{
782
tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
783
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
784
}
785
786
static inline void gen_op_cmpl_T0_T1_cc(void)
787
{
788
tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
789
tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
790
}
791
792
static inline void gen_op_testl_T0_T1_cc(void)
793
{
794
tcg_gen_discard_tl(cpu_cc_src);
795
tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
796
}
797
798
static void gen_op_update_neg_cc(void)
799
{
800
tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
801
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
802
}
803
804
/* compute eflags.C to reg */
805
static void gen_compute_eflags_c(TCGv reg)
806
{
807
#if TCG_TARGET_REG_BITS == 32
808
tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
809
tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,
810
(long)cc_table + offsetof(CCTable, compute_c));
811
tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
812
tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,
813
1, &cpu_tmp2_i32, 0, NULL);
814
#else
815
tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);
816
tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
817
tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,
818
(long)cc_table + offsetof(CCTable, compute_c));
819
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
820
tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,
821
1, &cpu_tmp2_i32, 0, NULL);
822
#endif
823
tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
824
}
825
826
/* compute all eflags to cc_src */
827
static void gen_compute_eflags(TCGv reg)
828
{
829
#if TCG_TARGET_REG_BITS == 32
830
tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
831
tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,
832
(long)cc_table + offsetof(CCTable, compute_all));
833
tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
834
tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,
835
1, &cpu_tmp2_i32, 0, NULL);
836
#else
837
tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);
838
tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
839
tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,
840
(long)cc_table + offsetof(CCTable, compute_all));
841
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
842
tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,
843
1, &cpu_tmp2_i32, 0, NULL);
844
#endif
845
tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
846
}
847
848
static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
849
{
850
if (s->cc_op != CC_OP_DYNAMIC)
851
gen_op_set_cc_op(s->cc_op);
852
switch(jcc_op) {
853
case JCC_O:
854
gen_compute_eflags(cpu_T[0]);
855
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
856
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
857
break;
858
case JCC_B:
859
gen_compute_eflags_c(cpu_T[0]);
860
break;
861
case JCC_Z:
862
gen_compute_eflags(cpu_T[0]);
863
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
864
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
865
break;
866
case JCC_BE:
867
gen_compute_eflags(cpu_tmp0);
868
tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
869
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
870
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
871
break;
872
case JCC_S:
873
gen_compute_eflags(cpu_T[0]);
874
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
875
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
876
break;
877
case JCC_P:
878
gen_compute_eflags(cpu_T[0]);
879
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
880
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
881
break;
882
case JCC_L:
883
gen_compute_eflags(cpu_tmp0);
884
tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
885
tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
886
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
887
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
888
break;
889
default:
890
case JCC_LE:
891
gen_compute_eflags(cpu_tmp0);
892
tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
893
tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
894
tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
895
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
896
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
897
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
898
break;
899
}
900
}
901
902
/* return true if setcc_slow is not needed (WARNING: must be kept in
903
sync with gen_jcc1) */
904
static int is_fast_jcc_case(DisasContext *s, int b)
905
{
906
int jcc_op;
907
jcc_op = (b >> 1) & 7;
908
switch(s->cc_op) {
909
/* we optimize the cmp/jcc case */
910
case CC_OP_SUBB:
911
case CC_OP_SUBW:
912
case CC_OP_SUBL:
913
case CC_OP_SUBQ:
914
if (jcc_op == JCC_O || jcc_op == JCC_P)
915
goto slow_jcc;
916
break;
917
918
/* some jumps are easy to compute */
919
case CC_OP_ADDB:
920
case CC_OP_ADDW:
921
case CC_OP_ADDL:
922
case CC_OP_ADDQ:
923
924
case CC_OP_LOGICB:
925
case CC_OP_LOGICW:
926
case CC_OP_LOGICL:
927
case CC_OP_LOGICQ:
928
929
case CC_OP_INCB:
930
case CC_OP_INCW:
931
case CC_OP_INCL:
932
case CC_OP_INCQ:
933
934
case CC_OP_DECB:
935
case CC_OP_DECW:
936
case CC_OP_DECL:
937
case CC_OP_DECQ:
938
939
case CC_OP_SHLB:
940
case CC_OP_SHLW:
941
case CC_OP_SHLL:
942
case CC_OP_SHLQ:
943
if (jcc_op != JCC_Z && jcc_op != JCC_S)
944
goto slow_jcc;
945
break;
946
default:
947
slow_jcc:
948
return 0;
949
}
950
return 1;
951
}
952
953
/* generate a conditional jump to label 'l1' according to jump opcode
954
value 'b'. In the fast case, T0 is guaranted not to be used. */
955
static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
956
{
957
int inv, jcc_op, size, cond;
958
TCGv t0;
959
960
inv = b & 1;
961
jcc_op = (b >> 1) & 7;
962
963
switch(cc_op) {
964
/* we optimize the cmp/jcc case */
965
case CC_OP_SUBB:
966
case CC_OP_SUBW:
967
case CC_OP_SUBL:
968
case CC_OP_SUBQ:
969
970
size = cc_op - CC_OP_SUBB;
971
switch(jcc_op) {
972
case JCC_Z:
973
fast_jcc_z:
974
switch(size) {
975
case 0:
976
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
977
t0 = cpu_tmp0;
978
break;
979
case 1:
980
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
981
t0 = cpu_tmp0;
982
break;
983
#ifdef TARGET_X86_64
984
case 2:
985
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
986
t0 = cpu_tmp0;
987
break;
988
#endif
989
default:
990
t0 = cpu_cc_dst;
991
break;
992
}
993
tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
994
break;
995
case JCC_S:
996
fast_jcc_s:
997
switch(size) {
998
case 0:
999
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
1000
tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1001
0, l1);
1002
break;
1003
case 1:
1004
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
1005
tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1006
0, l1);
1007
break;
1008
#ifdef TARGET_X86_64
1009
case 2:
1010
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
1011
tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1012
0, l1);
1013
break;
1014
#endif
1015
default:
1016
tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
1017
0, l1);
1018
break;
1019
}
1020
break;
1021
1022
case JCC_B:
1023
cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1024
goto fast_jcc_b;
1025
case JCC_BE:
1026
cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1027
fast_jcc_b:
1028
tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1029
switch(size) {
1030
case 0:
1031
t0 = cpu_tmp0;
1032
tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1033
tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1034
break;
1035
case 1:
1036
t0 = cpu_tmp0;
1037
tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1038
tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1039
break;
1040
#ifdef TARGET_X86_64
1041
case 2:
1042
t0 = cpu_tmp0;
1043
tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1044
tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1045
break;
1046
#endif
1047
default:
1048
t0 = cpu_cc_src;
1049
break;
1050
}
1051
tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1052
break;
1053
1054
case JCC_L:
1055
cond = inv ? TCG_COND_GE : TCG_COND_LT;
1056
goto fast_jcc_l;
1057
case JCC_LE:
1058
cond = inv ? TCG_COND_GT : TCG_COND_LE;
1059
fast_jcc_l:
1060
tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1061
switch(size) {
1062
case 0:
1063
t0 = cpu_tmp0;
1064
tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1065
tcg_gen_ext8s_tl(t0, cpu_cc_src);
1066
break;
1067
case 1:
1068
t0 = cpu_tmp0;
1069
tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1070
tcg_gen_ext16s_tl(t0, cpu_cc_src);
1071
break;
1072
#ifdef TARGET_X86_64
1073
case 2:
1074
t0 = cpu_tmp0;
1075
tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1076
tcg_gen_ext32s_tl(t0, cpu_cc_src);
1077
break;
1078
#endif
1079
default:
1080
t0 = cpu_cc_src;
1081
break;
1082
}
1083
tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1084
break;
1085
1086
default:
1087
goto slow_jcc;
1088
}
1089
break;
1090
1091
/* some jumps are easy to compute */
1092
case CC_OP_ADDB:
1093
case CC_OP_ADDW:
1094
case CC_OP_ADDL:
1095
case CC_OP_ADDQ:
1096
1097
case CC_OP_ADCB:
1098
case CC_OP_ADCW:
1099
case CC_OP_ADCL:
1100
case CC_OP_ADCQ:
1101
1102
case CC_OP_SBBB:
1103
case CC_OP_SBBW:
1104
case CC_OP_SBBL:
1105
case CC_OP_SBBQ:
1106
1107
case CC_OP_LOGICB:
1108
case CC_OP_LOGICW:
1109
case CC_OP_LOGICL:
1110
case CC_OP_LOGICQ:
1111
1112
case CC_OP_INCB:
1113
case CC_OP_INCW:
1114
case CC_OP_INCL:
1115
case CC_OP_INCQ:
1116
1117
case CC_OP_DECB:
1118
case CC_OP_DECW:
1119
case CC_OP_DECL:
1120
case CC_OP_DECQ:
1121
1122
case CC_OP_SHLB:
1123
case CC_OP_SHLW:
1124
case CC_OP_SHLL:
1125
case CC_OP_SHLQ:
1126
1127
case CC_OP_SARB:
1128
case CC_OP_SARW:
1129
case CC_OP_SARL:
1130
case CC_OP_SARQ:
1131
switch(jcc_op) {
1132
case JCC_Z:
1133
size = (cc_op - CC_OP_ADDB) & 3;
1134
goto fast_jcc_z;
1135
case JCC_S:
1136
size = (cc_op - CC_OP_ADDB) & 3;
1137
goto fast_jcc_s;
1138
default:
1139
goto slow_jcc;
1140
}
1141
break;
1142
default:
1143
slow_jcc:
1144
gen_setcc_slow_T0(s, jcc_op);
1145
tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1146
cpu_T[0], 0, l1);
1147
break;
1148
}
1149
}
1150
1151
988
/* XXX: does not work with gdbstub "ice" single step - not a
1152
989
serious problem */
1153
990
static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1156
993
1157
994
l1 = gen_new_label();
1158
995
l2 = gen_new_label();
1159
gen_op_jnz_ecx(s->aflag, l1);
996
gen_op_jnz_ecx[s->aflag](l1);
1160
997
gen_set_label(l2);
1161
998
gen_jmp_tb(s, next_eip, 1);
1162
999
gen_set_label(l1);
1165
1002
1166
1003
static inline void gen_stos(DisasContext *s, int ot)
1167
1004
{
1168
gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1005
gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
1169
1006
gen_string_movl_A0_EDI(s);
1170
gen_op_st_T0_A0(ot + s->mem_index);
1171
gen_op_movl_T0_Dshift(ot);
1172
gen_op_add_reg_T0(s->aflag, R_EDI);
1007
gen_op_st_T0_A0[ot + s->mem_index]();
1008
gen_op_movl_T0_Dshift[ot]();
1009
#ifdef TARGET_X86_64
1010
if (s->aflag == 2) {
1011
gen_op_addq_EDI_T0();
1012
} else
1013
#endif
1014
if (s->aflag) {
1015
gen_op_addl_EDI_T0();
1016
} else {
1017
gen_op_addw_EDI_T0();
1018
}
1173
1019
}
1174
1020
1175
1021
static inline void gen_lods(DisasContext *s, int ot)
1176
1022
{
1177
1023
gen_string_movl_A0_ESI(s);
1178
gen_op_ld_T0_A0(ot + s->mem_index);
1179
gen_op_mov_reg_T0(ot, R_EAX);
1180
gen_op_movl_T0_Dshift(ot);
1181
gen_op_add_reg_T0(s->aflag, R_ESI);
1024
gen_op_ld_T0_A0[ot + s->mem_index]();
1025
gen_op_mov_reg_T0[ot][R_EAX]();
1026
gen_op_movl_T0_Dshift[ot]();
1027
#ifdef TARGET_X86_64
1028
if (s->aflag == 2) {
1029
gen_op_addq_ESI_T0();
1030
} else
1031
#endif
1032
if (s->aflag) {
1033
gen_op_addl_ESI_T0();
1034
} else {
1035
gen_op_addw_ESI_T0();
1036
}
1182
1037
}
1183
1038
1184
1039
static inline void gen_scas(DisasContext *s, int ot)
1185
1040
{
1186
gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1041
gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
1187
1042
gen_string_movl_A0_EDI(s);
1188
gen_op_ld_T1_A0(ot + s->mem_index);
1043
gen_op_ld_T1_A0[ot + s->mem_index]();
1189
1044
gen_op_cmpl_T0_T1_cc();
1190
gen_op_movl_T0_Dshift(ot);
1191
gen_op_add_reg_T0(s->aflag, R_EDI);
1045
gen_op_movl_T0_Dshift[ot]();
1046
#ifdef TARGET_X86_64
1047
if (s->aflag == 2) {
1048
gen_op_addq_EDI_T0();
1049
} else
1050
#endif
1051
if (s->aflag) {
1052
gen_op_addl_EDI_T0();
1053
} else {
1054
gen_op_addw_EDI_T0();
1055
}
1192
1056
}
1193
1057
1194
1058
static inline void gen_cmps(DisasContext *s, int ot)
1195
1059
{
1196
1060
gen_string_movl_A0_ESI(s);
1197
gen_op_ld_T0_A0(ot + s->mem_index);
1061
gen_op_ld_T0_A0[ot + s->mem_index]();
1198
1062
gen_string_movl_A0_EDI(s);
1199
gen_op_ld_T1_A0(ot + s->mem_index);
1063
gen_op_ld_T1_A0[ot + s->mem_index]();
1200
1064
gen_op_cmpl_T0_T1_cc();
1201
gen_op_movl_T0_Dshift(ot);
1202
gen_op_add_reg_T0(s->aflag, R_ESI);
1203
gen_op_add_reg_T0(s->aflag, R_EDI);
1065
gen_op_movl_T0_Dshift[ot]();
1066
#ifdef TARGET_X86_64
1067
if (s->aflag == 2) {
1068
gen_op_addq_ESI_T0();
1069
gen_op_addq_EDI_T0();
1070
} else
1071
#endif
1072
if (s->aflag) {
1073
gen_op_addl_ESI_T0();
1074
gen_op_addl_EDI_T0();
1075
} else {
1076
gen_op_addw_ESI_T0();
1077
gen_op_addw_EDI_T0();
1078
}
1204
1079
}
1205
1080
1206
1081
static inline void gen_ins(DisasContext *s, int ot)
1207
1082
{
1208
if (use_icount)
1209
gen_io_start();
1210
1083
gen_string_movl_A0_EDI(s);
1211
/* Note: we must do this dummy write first to be restartable in
1212
case of page fault. */
1213
1084
gen_op_movl_T0_0();
1214
gen_op_st_T0_A0(ot + s->mem_index);
1215
gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1216
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1217
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1218
tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[0], cpu_tmp2_i32);
1219
gen_op_st_T0_A0(ot + s->mem_index);
1220
gen_op_movl_T0_Dshift(ot);
1221
gen_op_add_reg_T0(s->aflag, R_EDI);
1222
if (use_icount)
1223
gen_io_end();
1085
gen_op_st_T0_A0[ot + s->mem_index]();
1086
gen_op_in_DX_T0[ot]();
1087
gen_op_st_T0_A0[ot + s->mem_index]();
1088
gen_op_movl_T0_Dshift[ot]();
1089
#ifdef TARGET_X86_64
1090
if (s->aflag == 2) {
1091
gen_op_addq_EDI_T0();
1092
} else
1093
#endif
1094
if (s->aflag) {
1095
gen_op_addl_EDI_T0();
1096
} else {
1097
gen_op_addw_EDI_T0();
1098
}
1224
1099
}
1225
1100
1226
1101
static inline void gen_outs(DisasContext *s, int ot)
1227
1102
{
1228
if (use_icount)
1229
gen_io_start();
1230
1103
gen_string_movl_A0_ESI(s);
1231
gen_op_ld_T0_A0(ot + s->mem_index);
1232
1233
gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1234
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1235
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1236
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1237
tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
1238
1239
gen_op_movl_T0_Dshift(ot);
1240
gen_op_add_reg_T0(s->aflag, R_ESI);
1241
if (use_icount)
1242
gen_io_end();
1104
gen_op_ld_T0_A0[ot + s->mem_index]();
1105
gen_op_out_DX_T0[ot]();
1106
gen_op_movl_T0_Dshift[ot]();
1107
#ifdef TARGET_X86_64
1108
if (s->aflag == 2) {
1109
gen_op_addq_ESI_T0();
1110
} else
1111
#endif
1112
if (s->aflag) {
1113
gen_op_addl_ESI_T0();
1114
} else {
1115
gen_op_addw_ESI_T0();
1116
}
1243
1117
}
1244
1118
1245
1119
/* same method as Valgrind : we generate jumps to current or next
1252
1126
gen_update_cc_op(s); \
1253
1127
l2 = gen_jz_ecx_string(s, next_eip); \
1254
1128
gen_ ## op(s, ot); \
1255
gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1129
gen_op_dec_ECX[s->aflag](); \
1256
1130
/* a loop would cause two single step exceptions if ECX = 1 \
1257
1131
before rep string_insn */ \
1258
1132
if (!s->jmp_opt) \
1259
gen_op_jz_ecx(s->aflag, l2); \
1133
gen_op_jz_ecx[s->aflag](l2); \
1260
1134
gen_jmp(s, cur_eip); \
1261
1135
}
1262
1136
1270
1144
gen_update_cc_op(s); \
1271
1145
l2 = gen_jz_ecx_string(s, next_eip); \
1272
1146
gen_ ## op(s, ot); \
1273
gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1147
gen_op_dec_ECX[s->aflag](); \
1274
1148
gen_op_set_cc_op(CC_OP_SUBB + ot); \
1275
gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1149
gen_op_string_jnz_sub[nz][ot](l2);\
1276
1150
if (!s->jmp_opt) \
1277
gen_op_jz_ecx(s->aflag, l2); \
1151
gen_op_jz_ecx[s->aflag](l2); \
1278
1152
gen_jmp(s, cur_eip); \
1279
1153
}
1280
1154
1286
1160
GEN_REPZ2(scas)
1287
1161
GEN_REPZ2(cmps)
1288
1162
1289
static void *helper_fp_arith_ST0_FT0[8] = {
1290
helper_fadd_ST0_FT0,
1291
helper_fmul_ST0_FT0,
1292
helper_fcom_ST0_FT0,
1293
helper_fcom_ST0_FT0,
1294
helper_fsub_ST0_FT0,
1295
helper_fsubr_ST0_FT0,
1296
helper_fdiv_ST0_FT0,
1297
helper_fdivr_ST0_FT0,
1163
enum {
1164
JCC_O,
1165
JCC_B,
1166
JCC_Z,
1167
JCC_BE,
1168
JCC_S,
1169
JCC_P,
1170
JCC_L,
1171
JCC_LE,
1172
};
1173
1174
static GenOpFunc1 *gen_jcc_sub[4][8] = {
1175
[OT_BYTE] = {
1176
NULL,
1177
gen_op_jb_subb,
1178
gen_op_jz_subb,
1179
gen_op_jbe_subb,
1180
gen_op_js_subb,
1181
NULL,
1182
gen_op_jl_subb,
1183
gen_op_jle_subb,
1184
},
1185
[OT_WORD] = {
1186
NULL,
1187
gen_op_jb_subw,
1188
gen_op_jz_subw,
1189
gen_op_jbe_subw,
1190
gen_op_js_subw,
1191
NULL,
1192
gen_op_jl_subw,
1193
gen_op_jle_subw,
1194
},
1195
[OT_LONG] = {
1196
NULL,
1197
gen_op_jb_subl,
1198
gen_op_jz_subl,
1199
gen_op_jbe_subl,
1200
gen_op_js_subl,
1201
NULL,
1202
gen_op_jl_subl,
1203
gen_op_jle_subl,
1204
},
1205
#ifdef TARGET_X86_64
1206
[OT_QUAD] = {
1207
NULL,
1208
BUGGY_64(gen_op_jb_subq),
1209
gen_op_jz_subq,
1210
BUGGY_64(gen_op_jbe_subq),
1211
gen_op_js_subq,
1212
NULL,
1213
BUGGY_64(gen_op_jl_subq),
1214
BUGGY_64(gen_op_jle_subq),
1215
},
1216
#endif
1217
};
1218
static GenOpFunc1 *gen_op_loop[3][4] = {
1219
[0] = {
1220
gen_op_loopnzw,
1221
gen_op_loopzw,
1222
gen_op_jnz_ecxw,
1223
},
1224
[1] = {
1225
gen_op_loopnzl,
1226
gen_op_loopzl,
1227
gen_op_jnz_ecxl,
1228
},
1229
#ifdef TARGET_X86_64
1230
[2] = {
1231
gen_op_loopnzq,
1232
gen_op_loopzq,
1233
gen_op_jnz_ecxq,
1234
},
1235
#endif
1236
};
1237
1238
static GenOpFunc *gen_setcc_slow[8] = {
1239
gen_op_seto_T0_cc,
1240
gen_op_setb_T0_cc,
1241
gen_op_setz_T0_cc,
1242
gen_op_setbe_T0_cc,
1243
gen_op_sets_T0_cc,
1244
gen_op_setp_T0_cc,
1245
gen_op_setl_T0_cc,
1246
gen_op_setle_T0_cc,
1247
};
1248
1249
static GenOpFunc *gen_setcc_sub[4][8] = {
1250
[OT_BYTE] = {
1251
NULL,
1252
gen_op_setb_T0_subb,
1253
gen_op_setz_T0_subb,
1254
gen_op_setbe_T0_subb,
1255
gen_op_sets_T0_subb,
1256
NULL,
1257
gen_op_setl_T0_subb,
1258
gen_op_setle_T0_subb,
1259
},
1260
[OT_WORD] = {
1261
NULL,
1262
gen_op_setb_T0_subw,
1263
gen_op_setz_T0_subw,
1264
gen_op_setbe_T0_subw,
1265
gen_op_sets_T0_subw,
1266
NULL,
1267
gen_op_setl_T0_subw,
1268
gen_op_setle_T0_subw,
1269
},
1270
[OT_LONG] = {
1271
NULL,
1272
gen_op_setb_T0_subl,
1273
gen_op_setz_T0_subl,
1274
gen_op_setbe_T0_subl,
1275
gen_op_sets_T0_subl,
1276
NULL,
1277
gen_op_setl_T0_subl,
1278
gen_op_setle_T0_subl,
1279
},
1280
#ifdef TARGET_X86_64
1281
[OT_QUAD] = {
1282
NULL,
1283
gen_op_setb_T0_subq,
1284
gen_op_setz_T0_subq,
1285
gen_op_setbe_T0_subq,
1286
gen_op_sets_T0_subq,
1287
NULL,
1288
gen_op_setl_T0_subq,
1289
gen_op_setle_T0_subq,
1290
},
1291
#endif
1292
};
1293
1294
static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
1295
gen_op_fadd_ST0_FT0,
1296
gen_op_fmul_ST0_FT0,
1297
gen_op_fcom_ST0_FT0,
1298
gen_op_fcom_ST0_FT0,
1299
gen_op_fsub_ST0_FT0,
1300
gen_op_fsubr_ST0_FT0,
1301
gen_op_fdiv_ST0_FT0,
1302
gen_op_fdivr_ST0_FT0,
1298
1303
};
1299
1304
1300
1305
/* NOTE the exception in "r" op ordering */
1301
static void *helper_fp_arith_STN_ST0[8] = {
1302
helper_fadd_STN_ST0,
1303
helper_fmul_STN_ST0,
1304
NULL,
1305
NULL,
1306
helper_fsubr_STN_ST0,
1307
helper_fsub_STN_ST0,
1308
helper_fdivr_STN_ST0,
1309
helper_fdiv_STN_ST0,
1306
static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
1307
gen_op_fadd_STN_ST0,
1308
gen_op_fmul_STN_ST0,
1309
NULL,
1310
NULL,
1311
gen_op_fsubr_STN_ST0,
1312
gen_op_fsub_STN_ST0,
1313
gen_op_fdivr_STN_ST0,
1314
gen_op_fdiv_STN_ST0,
1310
1315
};
1311
1316
1312
1317
/* if d == OR_TMP0, it means memory operand (address in A0) */
1313
1318
static void gen_op(DisasContext *s1, int op, int ot, int d)
1314
1319
{
1320
GenOpFunc *gen_update_cc;
1321
1315
1322
if (d != OR_TMP0) {
1316
gen_op_mov_TN_reg(ot, 0, d);
1323
gen_op_mov_TN_reg[ot][0][d]();
1317
1324
} else {
1318
gen_op_ld_T0_A0(ot + s1->mem_index);
1325
gen_op_ld_T0_A0[ot + s1->mem_index]();
1319
1326
}
1320
1327
switch(op) {
1321
1328
case OP_ADCL:
1322
if (s1->cc_op != CC_OP_DYNAMIC)
1323
gen_op_set_cc_op(s1->cc_op);
1324
gen_compute_eflags_c(cpu_tmp4);
1325
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1326
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1327
if (d != OR_TMP0)
1328
gen_op_mov_reg_T0(ot, d);
1329
else
1330
gen_op_st_T0_A0(ot + s1->mem_index);
1331
tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1332
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1333
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1334
tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1335
tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1336
s1->cc_op = CC_OP_DYNAMIC;
1337
break;
1338
1329
case OP_SBBL:
1339
1330
if (s1->cc_op != CC_OP_DYNAMIC)
1340
1331
gen_op_set_cc_op(s1->cc_op);
1341
gen_compute_eflags_c(cpu_tmp4);
1342
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1343
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1344
if (d != OR_TMP0)
1345
gen_op_mov_reg_T0(ot, d);
1346
else
1347
gen_op_st_T0_A0(ot + s1->mem_index);
1348
tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1349
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1350
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1351
tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1352
tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1332
if (d != OR_TMP0) {
1333
gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
1334
gen_op_mov_reg_T0[ot][d]();
1335
} else {
1336
gen_op_arithc_mem_T0_T1_cc[ot + s1->mem_index][op - OP_ADCL]();
1337
}
1353
1338
s1->cc_op = CC_OP_DYNAMIC;
1354
break;
1339
goto the_end;
1355
1340
case OP_ADDL:
1356
1341
gen_op_addl_T0_T1();
1357
if (d != OR_TMP0)
1358
gen_op_mov_reg_T0(ot, d);
1359
else
1360
gen_op_st_T0_A0(ot + s1->mem_index);
1361
gen_op_update2_cc();
1362
1342
s1->cc_op = CC_OP_ADDB + ot;
1343
gen_update_cc = gen_op_update2_cc;
1363
1344
break;
1364
1345
case OP_SUBL:
1365
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1366
if (d != OR_TMP0)
1367
gen_op_mov_reg_T0(ot, d);
1368
else
1369
gen_op_st_T0_A0(ot + s1->mem_index);
1370
gen_op_update2_cc();
1346
gen_op_subl_T0_T1();
1371
1347
s1->cc_op = CC_OP_SUBB + ot;
1348
gen_update_cc = gen_op_update2_cc;
1372
1349
break;
1373
1350
default:
1374
1351
case OP_ANDL:
1375
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1376
if (d != OR_TMP0)
1377
gen_op_mov_reg_T0(ot, d);
1378
else
1379
gen_op_st_T0_A0(ot + s1->mem_index);
1380
gen_op_update1_cc();
1381
s1->cc_op = CC_OP_LOGICB + ot;
1382
break;
1383
1352
case OP_ORL:
1384
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1385
if (d != OR_TMP0)
1386
gen_op_mov_reg_T0(ot, d);
1387
else
1388
gen_op_st_T0_A0(ot + s1->mem_index);
1389
gen_op_update1_cc();
1390
s1->cc_op = CC_OP_LOGICB + ot;
1391
break;
1392
1353
case OP_XORL:
1393
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1394
if (d != OR_TMP0)
1395
gen_op_mov_reg_T0(ot, d);
1396
else
1397
gen_op_st_T0_A0(ot + s1->mem_index);
1398
gen_op_update1_cc();
1354
gen_op_arith_T0_T1_cc[op]();
1399
1355
s1->cc_op = CC_OP_LOGICB + ot;
1356
gen_update_cc = gen_op_update1_cc;
1400
1357
break;
1401
1358
case OP_CMPL:
1402
1359
gen_op_cmpl_T0_T1_cc();
1403
1360
s1->cc_op = CC_OP_SUBB + ot;
1361
gen_update_cc = NULL;
1404
1362
break;
1405
1363
}
1364
if (op != OP_CMPL) {
1365
if (d != OR_TMP0)
1366
gen_op_mov_reg_T0[ot][d]();
1367
else
1368
gen_op_st_T0_A0[ot + s1->mem_index]();
1369
}
1370
/* the flags update must happen after the memory write (precise
1371
exception support) */
1372
if (gen_update_cc)
1373
gen_update_cc();
1374
the_end: ;
1406
1375
}
1407
1376
1408
1377
/* if d == OR_TMP0, it means memory operand (address in A0) */
1409
1378
static void gen_inc(DisasContext *s1, int ot, int d, int c)
1410
1379
{
1411
1380
if (d != OR_TMP0)
1412
gen_op_mov_TN_reg(ot, 0, d);
1381
gen_op_mov_TN_reg[ot][0][d]();
1413
1382
else
1414
gen_op_ld_T0_A0(ot + s1->mem_index);
1383
gen_op_ld_T0_A0[ot + s1->mem_index]();
1415
1384
if (s1->cc_op != CC_OP_DYNAMIC)
1416
1385
gen_op_set_cc_op(s1->cc_op);
1417
1386
if (c > 0) {
1418
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1387
gen_op_incl_T0();
1419
1388
s1->cc_op = CC_OP_INCB + ot;
1420
1389
} else {
1421
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1390
gen_op_decl_T0();
1422
1391
s1->cc_op = CC_OP_DECB + ot;
1423
1392
}
1424
1393
if (d != OR_TMP0)
1425
gen_op_mov_reg_T0(ot, d);
1426
else
1427
gen_op_st_T0_A0(ot + s1->mem_index);
1428
gen_compute_eflags_c(cpu_cc_src);
1429
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1430
}
1431
1432
static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1433
int is_right, int is_arith)
1434
{
1435
target_ulong mask;
1436
int shift_label;
1437
TCGv t0, t1;
1438
1439
if (ot == OT_QUAD)
1440
mask = 0x3f;
1441
else
1442
mask = 0x1f;
1443
1444
/* load */
1445
if (op1 == OR_TMP0)
1446
gen_op_ld_T0_A0(ot + s->mem_index);
1447
else
1448
gen_op_mov_TN_reg(ot, 0, op1);
1449
1450
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1451
1452
tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1);
1453
1454
if (is_right) {
1455
if (is_arith) {
1456
gen_exts(ot, cpu_T[0]);
1457
tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1458
tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1459
} else {
1460
gen_extu(ot, cpu_T[0]);
1461
tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1462
tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1463
}
1464
} else {
1465
tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1466
tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1467
}
1468
1469
/* store */
1470
if (op1 == OR_TMP0)
1471
gen_op_st_T0_A0(ot + s->mem_index);
1472
else
1473
gen_op_mov_reg_T0(ot, op1);
1474
1475
/* update eflags if non zero shift */
1476
if (s->cc_op != CC_OP_DYNAMIC)
1477
gen_op_set_cc_op(s->cc_op);
1478
1479
/* XXX: inefficient */
1480
t0 = tcg_temp_local_new(TCG_TYPE_TL);
1481
t1 = tcg_temp_local_new(TCG_TYPE_TL);
1482
1483
tcg_gen_mov_tl(t0, cpu_T[0]);
1484
tcg_gen_mov_tl(t1, cpu_T3);
1485
1486
shift_label = gen_new_label();
1487
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label);
1488
1489
tcg_gen_mov_tl(cpu_cc_src, t1);
1490
tcg_gen_mov_tl(cpu_cc_dst, t0);
1491
if (is_right)
1492
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1493
else
1494
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1495
1496
gen_set_label(shift_label);
1497
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1498
1499
tcg_temp_free(t0);
1500
tcg_temp_free(t1);
1501
}
1502
1503
static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1504
int is_right, int is_arith)
1505
{
1506
int mask;
1507
1508
if (ot == OT_QUAD)
1509
mask = 0x3f;
1510
else
1511
mask = 0x1f;
1512
1513
/* load */
1514
if (op1 == OR_TMP0)
1515
gen_op_ld_T0_A0(ot + s->mem_index);
1516
else
1517
gen_op_mov_TN_reg(ot, 0, op1);
1518
1519
op2 &= mask;
1520
if (op2 != 0) {
1521
if (is_right) {
1522
if (is_arith) {
1523
gen_exts(ot, cpu_T[0]);
1524
tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1525
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1526
} else {
1527
gen_extu(ot, cpu_T[0]);
1528
tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1529
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1530
}
1531
} else {
1532
tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1533
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1534
}
1535
}
1536
1537
/* store */
1538
if (op1 == OR_TMP0)
1539
gen_op_st_T0_A0(ot + s->mem_index);
1540
else
1541
gen_op_mov_reg_T0(ot, op1);
1542
1543
/* update eflags if non zero shift */
1544
if (op2 != 0) {
1545
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1546
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1547
if (is_right)
1548
s->cc_op = CC_OP_SARB + ot;
1549
else
1550
s->cc_op = CC_OP_SHLB + ot;
1551
}
1552
}
1553
1554
static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1555
{
1556
if (arg2 >= 0)
1557
tcg_gen_shli_tl(ret, arg1, arg2);
1558
else
1559
tcg_gen_shri_tl(ret, arg1, -arg2);
1560
}
1561
1562
/* XXX: add faster immediate case */
1563
static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1564
int is_right)
1565
{
1566
target_ulong mask;
1567
int label1, label2, data_bits;
1568
TCGv t0, t1, t2, a0;
1569
1570
/* XXX: inefficient, but we must use local temps */
1571
t0 = tcg_temp_local_new(TCG_TYPE_TL);
1572
t1 = tcg_temp_local_new(TCG_TYPE_TL);
1573
t2 = tcg_temp_local_new(TCG_TYPE_TL);
1574
a0 = tcg_temp_local_new(TCG_TYPE_TL);
1575
1576
if (ot == OT_QUAD)
1577
mask = 0x3f;
1578
else
1579
mask = 0x1f;
1580
1581
/* load */
1582
if (op1 == OR_TMP0) {
1583
tcg_gen_mov_tl(a0, cpu_A0);
1584
gen_op_ld_v(ot + s->mem_index, t0, a0);
1585
} else {
1586
gen_op_mov_v_reg(ot, t0, op1);
1587
}
1588
1589
tcg_gen_mov_tl(t1, cpu_T[1]);
1590
1591
tcg_gen_andi_tl(t1, t1, mask);
1592
1593
/* Must test zero case to avoid using undefined behaviour in TCG
1594
shifts. */
1595
label1 = gen_new_label();
1596
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1597
1598
if (ot <= OT_WORD)
1599
tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1600
else
1601
tcg_gen_mov_tl(cpu_tmp0, t1);
1602
1603
gen_extu(ot, t0);
1604
tcg_gen_mov_tl(t2, t0);
1605
1606
data_bits = 8 << ot;
1607
/* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1608
fix TCG definition) */
1609
if (is_right) {
1610
tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1611
tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1612
tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1613
} else {
1614
tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1615
tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1616
tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1617
}
1618
tcg_gen_or_tl(t0, t0, cpu_tmp4);
1619
1620
gen_set_label(label1);
1621
/* store */
1622
if (op1 == OR_TMP0) {
1623
gen_op_st_v(ot + s->mem_index, t0, a0);
1624
} else {
1625
gen_op_mov_reg_v(ot, op1, t0);
1626
}
1627
1628
/* update eflags */
1629
if (s->cc_op != CC_OP_DYNAMIC)
1630
gen_op_set_cc_op(s->cc_op);
1631
1632
label2 = gen_new_label();
1633
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1634
1635
gen_compute_eflags(cpu_cc_src);
1636
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1637
tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1638
tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1639
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1640
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1641
if (is_right) {
1642
tcg_gen_shri_tl(t0, t0, data_bits - 1);
1643
}
1644
tcg_gen_andi_tl(t0, t0, CC_C);
1645
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1646
1647
tcg_gen_discard_tl(cpu_cc_dst);
1648
tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1649
1650
gen_set_label(label2);
1651
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1652
1653
tcg_temp_free(t0);
1654
tcg_temp_free(t1);
1655
tcg_temp_free(t2);
1656
tcg_temp_free(a0);
1657
}
1658
1659
static void *helper_rotc[8] = {
1660
helper_rclb,
1661
helper_rclw,
1662
helper_rcll,
1663
X86_64_ONLY(helper_rclq),
1664
helper_rcrb,
1665
helper_rcrw,
1666
helper_rcrl,
1667
X86_64_ONLY(helper_rcrq),
1668
};
1669
1670
/* XXX: add faster immediate = 1 case */
1671
static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1672
int is_right)
1673
{
1674
int label1;
1675
1676
if (s->cc_op != CC_OP_DYNAMIC)
1677
gen_op_set_cc_op(s->cc_op);
1678
1679
/* load */
1680
if (op1 == OR_TMP0)
1681
gen_op_ld_T0_A0(ot + s->mem_index);
1682
else
1683
gen_op_mov_TN_reg(ot, 0, op1);
1684
1685
tcg_gen_helper_1_2(helper_rotc[ot + (is_right * 4)],
1686
cpu_T[0], cpu_T[0], cpu_T[1]);
1687
/* store */
1688
if (op1 == OR_TMP0)
1689
gen_op_st_T0_A0(ot + s->mem_index);
1690
else
1691
gen_op_mov_reg_T0(ot, op1);
1692
1693
/* update eflags */
1694
label1 = gen_new_label();
1695
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
1696
1697
tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
1698
tcg_gen_discard_tl(cpu_cc_dst);
1699
tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1700
1701
gen_set_label(label1);
1702
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1703
}
1704
1705
/* XXX: add faster immediate case */
1706
static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1707
int is_right)
1708
{
1709
int label1, label2, data_bits;
1710
target_ulong mask;
1711
TCGv t0, t1, t2, a0;
1712
1713
t0 = tcg_temp_local_new(TCG_TYPE_TL);
1714
t1 = tcg_temp_local_new(TCG_TYPE_TL);
1715
t2 = tcg_temp_local_new(TCG_TYPE_TL);
1716
a0 = tcg_temp_local_new(TCG_TYPE_TL);
1717
1718
if (ot == OT_QUAD)
1719
mask = 0x3f;
1720
else
1721
mask = 0x1f;
1722
1723
/* load */
1724
if (op1 == OR_TMP0) {
1725
tcg_gen_mov_tl(a0, cpu_A0);
1726
gen_op_ld_v(ot + s->mem_index, t0, a0);
1727
} else {
1728
gen_op_mov_v_reg(ot, t0, op1);
1729
}
1730
1731
tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1732
1733
tcg_gen_mov_tl(t1, cpu_T[1]);
1734
tcg_gen_mov_tl(t2, cpu_T3);
1735
1736
/* Must test zero case to avoid using undefined behaviour in TCG
1737
shifts. */
1738
label1 = gen_new_label();
1739
tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1740
1741
tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1742
if (ot == OT_WORD) {
1743
/* Note: we implement the Intel behaviour for shift count > 16 */
1744
if (is_right) {
1745
tcg_gen_andi_tl(t0, t0, 0xffff);
1746
tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1747
tcg_gen_or_tl(t0, t0, cpu_tmp0);
1748
tcg_gen_ext32u_tl(t0, t0);
1749
1750
tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1751
1752
/* only needed if count > 16, but a test would complicate */
1753
tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2);
1754
tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1755
1756
tcg_gen_shr_tl(t0, t0, t2);
1757
1758
tcg_gen_or_tl(t0, t0, cpu_tmp0);
1759
} else {
1760
/* XXX: not optimal */
1761
tcg_gen_andi_tl(t0, t0, 0xffff);
1762
tcg_gen_shli_tl(t1, t1, 16);
1763
tcg_gen_or_tl(t1, t1, t0);
1764
tcg_gen_ext32u_tl(t1, t1);
1765
1766
tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1767
tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5);
1768
tcg_gen_shr_tl(cpu_tmp6, t1, cpu_tmp0);
1769
tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp6);
1770
1771
tcg_gen_shl_tl(t0, t0, t2);
1772
tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2);
1773
tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1774
tcg_gen_or_tl(t0, t0, t1);
1775
}
1776
} else {
1777
data_bits = 8 << ot;
1778
if (is_right) {
1779
if (ot == OT_LONG)
1780
tcg_gen_ext32u_tl(t0, t0);
1781
1782
tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1783
1784
tcg_gen_shr_tl(t0, t0, t2);
1785
tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2);
1786
tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1787
tcg_gen_or_tl(t0, t0, t1);
1788
1789
} else {
1790
if (ot == OT_LONG)
1791
tcg_gen_ext32u_tl(t1, t1);
1792
1793
tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1794
1795
tcg_gen_shl_tl(t0, t0, t2);
1796
tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2);
1797
tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1798
tcg_gen_or_tl(t0, t0, t1);
1799
}
1800
}
1801
tcg_gen_mov_tl(t1, cpu_tmp4);
1802
1803
gen_set_label(label1);
1804
/* store */
1805
if (op1 == OR_TMP0) {
1806
gen_op_st_v(ot + s->mem_index, t0, a0);
1807
} else {
1808
gen_op_mov_reg_v(ot, op1, t0);
1809
}
1810
1811
/* update eflags */
1812
if (s->cc_op != CC_OP_DYNAMIC)
1813
gen_op_set_cc_op(s->cc_op);
1814
1815
label2 = gen_new_label();
1816
tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
1817
1818
tcg_gen_mov_tl(cpu_cc_src, t1);
1819
tcg_gen_mov_tl(cpu_cc_dst, t0);
1820
if (is_right) {
1821
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1822
} else {
1823
tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1824
}
1825
gen_set_label(label2);
1826
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1827
1828
tcg_temp_free(t0);
1829
tcg_temp_free(t1);
1830
tcg_temp_free(t2);
1831
tcg_temp_free(a0);
1394
gen_op_mov_reg_T0[ot][d]();
1395
else
1396
gen_op_st_T0_A0[ot + s1->mem_index]();
1397
gen_op_update_inc_cc();
1832
1398
}
1833
1399
1834
1400
static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1835
1401
{
1402
if (d != OR_TMP0)
1403
gen_op_mov_TN_reg[ot][0][d]();
1404
else
1405
gen_op_ld_T0_A0[ot + s1->mem_index]();
1836
1406
if (s != OR_TMP1)
1837
gen_op_mov_TN_reg(ot, 1, s);
1838
switch(op) {
1839
case OP_ROL:
1840
gen_rot_rm_T1(s1, ot, d, 0);
1841
break;
1842
case OP_ROR:
1843
gen_rot_rm_T1(s1, ot, d, 1);
1844
break;
1845
case OP_SHL:
1846
case OP_SHL1:
1847
gen_shift_rm_T1(s1, ot, d, 0, 0);
1848
break;
1849
case OP_SHR:
1850
gen_shift_rm_T1(s1, ot, d, 1, 0);
1851
break;
1852
case OP_SAR:
1853
gen_shift_rm_T1(s1, ot, d, 1, 1);
1854
break;
1855
case OP_RCL:
1856
gen_rotc_rm_T1(s1, ot, d, 0);
1857
break;
1858
case OP_RCR:
1859
gen_rotc_rm_T1(s1, ot, d, 1);
1860
break;
1861
}
1407
gen_op_mov_TN_reg[ot][1][s]();
1408
/* for zero counts, flags are not updated, so must do it dynamically */
1409
if (s1->cc_op != CC_OP_DYNAMIC)
1410
gen_op_set_cc_op(s1->cc_op);
1411
1412
if (d != OR_TMP0)
1413
gen_op_shift_T0_T1_cc[ot][op]();
1414
else
1415
gen_op_shift_mem_T0_T1_cc[ot + s1->mem_index][op]();
1416
if (d != OR_TMP0)
1417
gen_op_mov_reg_T0[ot][d]();
1418
s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1862
1419
}
1863
1420
1864
1421
static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1865
1422
{
1866
switch(op) {
1867
case OP_SHL:
1868
case OP_SHL1:
1869
gen_shift_rm_im(s1, ot, d, c, 0, 0);
1870
break;
1871
case OP_SHR:
1872
gen_shift_rm_im(s1, ot, d, c, 1, 0);
1873
break;
1874
case OP_SAR:
1875
gen_shift_rm_im(s1, ot, d, c, 1, 1);
1876
break;
1877
default:
1878
/* currently not optimized */
1879
gen_op_movl_T1_im(c);
1880
gen_shift(s1, op, ot, d, OR_TMP1);
1881
break;
1882
}
1423
/* currently not optimized */
1424
gen_op_movl_T1_im(c);
1425
gen_shift(s1, op, ot, d, OR_TMP1);
1883
1426
}
1884
1427
1885
1428
static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1905
1448
base = rm;
1906
1449
index = 0;
1907
1450
scale = 0;
1908
1451
1909
1452
if (base == 4) {
1910
1453
havesib = 1;
1911
1454
code = ldub_code(s->pc++);
1937
1480
s->pc += 4;
1938
1481
break;
1939
1482
}
1940
1483
1941
1484
if (base >= 0) {
1942
1485
/* for correct popl handling with esp */
1943
1486
if (base == 4 && s->popl_esp_hack)
1944
1487
disp += s->popl_esp_hack;
1945
1488
#ifdef TARGET_X86_64
1946
1489
if (s->aflag == 2) {
1947
gen_op_movq_A0_reg(base);
1490
gen_op_movq_A0_reg[base]();
1948
1491
if (disp != 0) {
1949
gen_op_addq_A0_im(disp);
1492
if ((int32_t)disp == disp)
1493
gen_op_addq_A0_im(disp);
1494
else
1495
gen_op_addq_A0_im64(disp >> 32, disp);
1950
1496
}
1951
} else
1497
} else
1952
1498
#endif
1953
1499
{
1954
gen_op_movl_A0_reg(base);
1500
gen_op_movl_A0_reg[base]();
1955
1501
if (disp != 0)
1956
1502
gen_op_addl_A0_im(disp);
1957
1503
}
1958
1504
} else {
1959
1505
#ifdef TARGET_X86_64
1960
1506
if (s->aflag == 2) {
1961
gen_op_movq_A0_im(disp);
1962
} else
1507
if ((int32_t)disp == disp)
1508
gen_op_movq_A0_im(disp);
1509
else
1510
gen_op_movq_A0_im64(disp >> 32, disp);
1511
} else
1963
1512
#endif
1964
1513
{
1965
1514
gen_op_movl_A0_im(disp);
1969
1518
if (havesib && (index != 4 || scale != 0)) {
1970
1519
#ifdef TARGET_X86_64
1971
1520
if (s->aflag == 2) {
1972
gen_op_addq_A0_reg_sN(scale, index);
1973
} else
1521
gen_op_addq_A0_reg_sN[scale][index]();
1522
} else
1974
1523
#endif
1975
1524
{
1976
gen_op_addl_A0_reg_sN(scale, index);
1525
gen_op_addl_A0_reg_sN[scale][index]();
1977
1526
}
1978
1527
}
1979
1528
if (must_add_seg) {
1985
1534
}
1986
1535
#ifdef TARGET_X86_64
1987
1536
if (s->aflag == 2) {
1988
gen_op_addq_A0_seg(override);
1989
} else
1537
gen_op_addq_A0_seg(offsetof(CPUX86State,segs[override].base));
1538
} else
1990
1539
#endif
1991
1540
{
1992
gen_op_addl_A0_seg(override);
1541
gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1993
1542
}
1994
1543
}
1995
1544
} else {
2016
1565
}
2017
1566
switch(rm) {
2018
1567
case 0:
2019
gen_op_movl_A0_reg(R_EBX);
2020
gen_op_addl_A0_reg_sN(0, R_ESI);
1568
gen_op_movl_A0_reg[R_EBX]();
1569
gen_op_addl_A0_reg_sN[0][R_ESI]();
2021
1570
break;
2022
1571
case 1:
2023
gen_op_movl_A0_reg(R_EBX);
2024
gen_op_addl_A0_reg_sN(0, R_EDI);
1572
gen_op_movl_A0_reg[R_EBX]();
1573
gen_op_addl_A0_reg_sN[0][R_EDI]();
2025
1574
break;
2026
1575
case 2:
2027
gen_op_movl_A0_reg(R_EBP);
2028
gen_op_addl_A0_reg_sN(0, R_ESI);
1576
gen_op_movl_A0_reg[R_EBP]();
1577
gen_op_addl_A0_reg_sN[0][R_ESI]();
2029
1578
break;
2030
1579
case 3:
2031
gen_op_movl_A0_reg(R_EBP);
2032
gen_op_addl_A0_reg_sN(0, R_EDI);
1580
gen_op_movl_A0_reg[R_EBP]();
1581
gen_op_addl_A0_reg_sN[0][R_EDI]();
2033
1582
break;
2034
1583
case 4:
2035
gen_op_movl_A0_reg(R_ESI);
1584
gen_op_movl_A0_reg[R_ESI]();
2036
1585
break;
2037
1586
case 5:
2038
gen_op_movl_A0_reg(R_EDI);
1587
gen_op_movl_A0_reg[R_EDI]();
2039
1588
break;
2040
1589
case 6:
2041
gen_op_movl_A0_reg(R_EBP);
1590
gen_op_movl_A0_reg[R_EBP]();
2042
1591
break;
2043
1592
default:
2044
1593
case 7:
2045
gen_op_movl_A0_reg(R_EBX);
1594
gen_op_movl_A0_reg[R_EBX]();
2046
1595
break;
2047
1596
}
2048
1597
if (disp != 0)
2056
1605
else
2057
1606
override = R_DS;
2058
1607
}
2059
gen_op_addl_A0_seg(override);
1608
gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2060
1609
}
2061
1610
}
2062
1611
2078
1627
if (s->aflag) {
2079
1628
2080
1629
base = rm;
2081
1630
2082
1631
if (base == 4) {
2083
1632
code = ldub_code(s->pc++);
2084
1633
base = (code & 7);
2085
1634
}
2086
1635
2087
1636
switch (mod) {
2088
1637
case 0:
2089
1638
if (base == 5) {
2131
1680
if (must_add_seg) {
2132
1681
#ifdef TARGET_X86_64
2133
1682
if (CODE64(s)) {
2134
gen_op_addq_A0_seg(override);
2135
} else
1683
gen_op_addq_A0_seg(offsetof(CPUX86State,segs[override].base));
1684
} else
2136
1685
#endif
2137
1686
{
2138
gen_op_addl_A0_seg(override);
1687
gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2139
1688
}
2140
1689
}
2141
1690
}
2142
1691
2143
/* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
1692
/* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
2144
1693
OR_TMP0 */
2145
1694
static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2146
1695
{
2151
1700
if (mod == 3) {
2152
1701
if (is_store) {
2153
1702
if (reg != OR_TMP0)
2154
gen_op_mov_TN_reg(ot, 0, reg);
2155
gen_op_mov_reg_T0(ot, rm);
1703
gen_op_mov_TN_reg[ot][0][reg]();
1704
gen_op_mov_reg_T0[ot][rm]();
2156
1705
} else {
2157
gen_op_mov_TN_reg(ot, 0, rm);
1706
gen_op_mov_TN_reg[ot][0][rm]();
2158
1707
if (reg != OR_TMP0)
2159
gen_op_mov_reg_T0(ot, reg);
1708
gen_op_mov_reg_T0[ot][reg]();
2160
1709
}
2161
1710
} else {
2162
1711
gen_lea_modrm(s, modrm, &opreg, &disp);
2163
1712
if (is_store) {
2164
1713
if (reg != OR_TMP0)
2165
gen_op_mov_TN_reg(ot, 0, reg);
2166
gen_op_st_T0_A0(ot + s->mem_index);
1714
gen_op_mov_TN_reg[ot][0][reg]();
1715
gen_op_st_T0_A0[ot + s->mem_index]();
2167
1716
} else {
2168
gen_op_ld_T0_A0(ot + s->mem_index);
1717
gen_op_ld_T0_A0[ot + s->mem_index]();
2169
1718
if (reg != OR_TMP0)
2170
gen_op_mov_reg_T0(ot, reg);
1719
gen_op_mov_reg_T0[ot][reg]();
2171
1720
}
2172
1721
}
2173
1722
}
2213
1762
if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2214
1763
(pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2215
1764
/* jump to same page: we can use a direct jump */
2216
tcg_gen_goto_tb(tb_num);
1765
if (tb_num == 0)
1766
gen_op_goto_tb0(TBPARAM(tb));
1767
else
1768
gen_op_goto_tb1(TBPARAM(tb));
2217
1769
gen_jmp_im(eip);
2218
tcg_gen_exit_tb((long)tb + tb_num);
1770
gen_op_movl_T0_im((long)tb + tb_num);
1771
gen_op_exit_tb();
2219
1772
} else {
2220
1773
/* jump to another page: currently not optimized */
2221
1774
gen_jmp_im(eip);
2223
1776
}
2224
1777
}
2225
1778
2226
static inline void gen_jcc(DisasContext *s, int b,
1779
static inline void gen_jcc(DisasContext *s, int b,
2227
1780
target_ulong val, target_ulong next_eip)
2228
1781
{
2229
int l1, l2, cc_op;
1782
TranslationBlock *tb;
1783
int inv, jcc_op;
1784
GenOpFunc1 *func;
1785
target_ulong tmp;
1786
int l1, l2;
2230
1787
2231
cc_op = s->cc_op;
2232
if (s->cc_op != CC_OP_DYNAMIC) {
2233
gen_op_set_cc_op(s->cc_op);
2234
s->cc_op = CC_OP_DYNAMIC;
2235
}
1788
inv = b & 1;
1789
jcc_op = (b >> 1) & 7;
1790
2236
1791
if (s->jmp_opt) {
1792
switch(s->cc_op) {
1793
/* we optimize the cmp/jcc case */
1794
case CC_OP_SUBB:
1795
case CC_OP_SUBW:
1796
case CC_OP_SUBL:
1797
case CC_OP_SUBQ:
1798
func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1799
break;
1800
1801
/* some jumps are easy to compute */
1802
case CC_OP_ADDB:
1803
case CC_OP_ADDW:
1804
case CC_OP_ADDL:
1805
case CC_OP_ADDQ:
1806
1807
case CC_OP_ADCB:
1808
case CC_OP_ADCW:
1809
case CC_OP_ADCL:
1810
case CC_OP_ADCQ:
1811
1812
case CC_OP_SBBB:
1813
case CC_OP_SBBW:
1814
case CC_OP_SBBL:
1815
case CC_OP_SBBQ:
1816
1817
case CC_OP_LOGICB:
1818
case CC_OP_LOGICW:
1819
case CC_OP_LOGICL:
1820
case CC_OP_LOGICQ:
1821
1822
case CC_OP_INCB:
1823
case CC_OP_INCW:
1824
case CC_OP_INCL:
1825
case CC_OP_INCQ:
1826
1827
case CC_OP_DECB:
1828
case CC_OP_DECW:
1829
case CC_OP_DECL:
1830
case CC_OP_DECQ:
1831
1832
case CC_OP_SHLB:
1833
case CC_OP_SHLW:
1834
case CC_OP_SHLL:
1835
case CC_OP_SHLQ:
1836
1837
case CC_OP_SARB:
1838
case CC_OP_SARW:
1839
case CC_OP_SARL:
1840
case CC_OP_SARQ:
1841
switch(jcc_op) {
1842
case JCC_Z:
1843
func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1844
break;
1845
case JCC_S:
1846
func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1847
break;
1848
default:
1849
func = NULL;
1850
break;
1851
}
1852
break;
1853
default:
1854
func = NULL;
1855
break;
1856
}
1857
1858
if (s->cc_op != CC_OP_DYNAMIC) {
1859
gen_op_set_cc_op(s->cc_op);
1860
s->cc_op = CC_OP_DYNAMIC;
1861
}
1862
1863
if (!func) {
1864
gen_setcc_slow[jcc_op]();
1865
func = gen_op_jnz_T0_label;
1866
}
1867
1868
if (inv) {
1869
tmp = val;
1870
val = next_eip;
1871
next_eip = tmp;
1872
}
1873
tb = s->tb;
1874
2237
1875
l1 = gen_new_label();
2238
gen_jcc1(s, cc_op, b, l1);
2239
1876
func(l1);
1877
2240
1878
gen_goto_tb(s, 0, next_eip);
2241
1879
2242
1880
gen_set_label(l1);
2243
1881
gen_goto_tb(s, 1, val);
1882
2244
1883
s->is_jmp = 3;
2245
1884
} else {
2246
1885
1886
if (s->cc_op != CC_OP_DYNAMIC) {
1887
gen_op_set_cc_op(s->cc_op);
1888
s->cc_op = CC_OP_DYNAMIC;
1889
}
1890
gen_setcc_slow[jcc_op]();
1891
if (inv) {
1892
tmp = val;
1893
val = next_eip;
1894
next_eip = tmp;
1895
}
2247
1896
l1 = gen_new_label();
2248
1897
l2 = gen_new_label();
2249
gen_jcc1(s, cc_op, b, l1);
2250
1898
gen_op_jnz_T0_label(l1);
2251
1899
gen_jmp_im(next_eip);
2252
tcg_gen_br(l2);
2253
1900
gen_op_jmp_label(l2);
2254
1901
gen_set_label(l1);
2255
1902
gen_jmp_im(val);
2256
1903
gen_set_label(l2);
2260
1907
2261
1908
static void gen_setcc(DisasContext *s, int b)
2262
1909
{
2263
int inv, jcc_op, l1;
2264
TCGv t0;
2265
2266
if (is_fast_jcc_case(s, b)) {
2267
/* nominal case: we use a jump */
2268
/* XXX: make it faster by adding new instructions in TCG */
2269
t0 = tcg_temp_local_new(TCG_TYPE_TL);
2270
tcg_gen_movi_tl(t0, 0);
2271
l1 = gen_new_label();
2272
gen_jcc1(s, s->cc_op, b ^ 1, l1);
2273
tcg_gen_movi_tl(t0, 1);
2274
gen_set_label(l1);
2275
tcg_gen_mov_tl(cpu_T[0], t0);
2276
tcg_temp_free(t0);
2277
} else {
2278
/* slow case: it is more efficient not to generate a jump,
2279
although it is questionnable whether this optimization is
2280
worth to */
2281
inv = b & 1;
2282
jcc_op = (b >> 1) & 7;
2283
gen_setcc_slow_T0(s, jcc_op);
2284
if (inv) {
2285
tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
1910
int inv, jcc_op;
1911
GenOpFunc *func;
1912
1913
inv = b & 1;
1914
jcc_op = (b >> 1) & 7;
1915
switch(s->cc_op) {
1916
/* we optimize the cmp/jcc case */
1917
case CC_OP_SUBB:
1918
case CC_OP_SUBW:
1919
case CC_OP_SUBL:
1920
case CC_OP_SUBQ:
1921
func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1922
if (!func)
1923
goto slow_jcc;
1924
break;
1925
1926
/* some jumps are easy to compute */
1927
case CC_OP_ADDB:
1928
case CC_OP_ADDW:
1929
case CC_OP_ADDL:
1930
case CC_OP_ADDQ:
1931
1932
case CC_OP_LOGICB:
1933
case CC_OP_LOGICW:
1934
case CC_OP_LOGICL:
1935
case CC_OP_LOGICQ:
1936
1937
case CC_OP_INCB:
1938
case CC_OP_INCW:
1939
case CC_OP_INCL:
1940
case CC_OP_INCQ:
1941
1942
case CC_OP_DECB:
1943
case CC_OP_DECW:
1944
case CC_OP_DECL:
1945
case CC_OP_DECQ:
1946
1947
case CC_OP_SHLB:
1948
case CC_OP_SHLW:
1949
case CC_OP_SHLL:
1950
case CC_OP_SHLQ:
1951
switch(jcc_op) {
1952
case JCC_Z:
1953
func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1954
break;
1955
case JCC_S:
1956
func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 4][jcc_op];
1957
break;
1958
default:
1959
goto slow_jcc;
2286
1960
}
2287
}
2288
}
2289
2290
static inline void gen_op_movl_T0_seg(int seg_reg)
2291
{
2292
tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2293
offsetof(CPUX86State,segs[seg_reg].selector));
2294
}
2295
2296
static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2297
{
2298
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2299
tcg_gen_st32_tl(cpu_T[0], cpu_env,
2300
offsetof(CPUX86State,segs[seg_reg].selector));
2301
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2302
tcg_gen_st_tl(cpu_T[0], cpu_env,
2303
offsetof(CPUX86State,segs[seg_reg].base));
1961
break;
1962
default:
1963
slow_jcc:
1964
if (s->cc_op != CC_OP_DYNAMIC)
1965
gen_op_set_cc_op(s->cc_op);
1966
func = gen_setcc_slow[jcc_op];
1967
break;
1968
}
1969
func();
1970
if (inv) {
1971
gen_op_xor_T0_1();
1972
}
2304
1973
}
2305
1974
2306
1975
/* move T0 to seg_reg and compute if the CPU state may change. Never
2312
1981
if (s->cc_op != CC_OP_DYNAMIC)
2313
1982
gen_op_set_cc_op(s->cc_op);
2314
1983
gen_jmp_im(cur_eip);
2315
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2316
tcg_gen_helper_0_2(helper_load_seg, tcg_const_i32(seg_reg), cpu_tmp2_i32);
1984
gen_op_movl_seg_T0(seg_reg);
2317
1985
/* abort translation because the addseg value may change or
2318
1986
because ss32 may change. For R_SS, translation must always
2319
1987
stop as a special handling must be done to disable hardware
2321
1989
if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2322
1990
s->is_jmp = 3;
2323
1991
} else {
2324
gen_op_movl_seg_T0_vm(seg_reg);
1992
gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
2325
1993
if (seg_reg == R_SS)
2326
1994
s->is_jmp = 3;
2327
1995
}
2328
1996
}
2329
1997
2330
static inline int svm_is_rep(int prefixes)
2331
{
2332
return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2333
}
2334
2335
static inline void
2336
gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2337
uint32_t type, uint64_t param)
2338
{
2339
/* no SVM activated; fast case */
2340
if (likely(!(s->flags & HF_SVMI_MASK)))
2341
return;
2342
if (s->cc_op != CC_OP_DYNAMIC)
2343
gen_op_set_cc_op(s->cc_op);
2344
gen_jmp_im(pc_start - s->cs_base);
2345
tcg_gen_helper_0_2(helper_svm_check_intercept_param,
2346
tcg_const_i32(type), tcg_const_i64(param));
2347
}
2348
2349
static inline void
2350
gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2351
{
2352
gen_svm_check_intercept_param(s, pc_start, type, 0);
2353
}
2354
2355
1998
static inline void gen_stack_update(DisasContext *s, int addend)
2356
1999
{
2357
2000
#ifdef TARGET_X86_64
2358
2001
if (CODE64(s)) {
2359
gen_op_add_reg_im(2, R_ESP, addend);
2002
if (addend == 8)
2003
gen_op_addq_ESP_8();
2004
else
2005
gen_op_addq_ESP_im(addend);
2360
2006
} else
2361
2007
#endif
2362
2008
if (s->ss32) {
2363
gen_op_add_reg_im(1, R_ESP, addend);
2009
if (addend == 2)
2010
gen_op_addl_ESP_2();
2011
else if (addend == 4)
2012
gen_op_addl_ESP_4();
2013
else
2014
gen_op_addl_ESP_im(addend);
2364
2015
} else {
2365
gen_op_add_reg_im(0, R_ESP, addend);
2016
if (addend == 2)
2017
gen_op_addw_ESP_2();
2018
else if (addend == 4)
2019
gen_op_addw_ESP_4();
2020
else
2021
gen_op_addw_ESP_im(addend);
2366
2022
}
2367
2023
}
2368
2024
2371
2027
{
2372
2028
#ifdef TARGET_X86_64
2373
2029
if (CODE64(s)) {
2374
gen_op_movq_A0_reg(R_ESP);
2030
gen_op_movq_A0_reg[R_ESP]();
2375
2031
if (s->dflag) {
2376
gen_op_addq_A0_im(-8);
2377
gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2032
gen_op_subq_A0_8();
2033
gen_op_st_T0_A0[OT_QUAD + s->mem_index]();
2378
2034
} else {
2379
gen_op_addq_A0_im(-2);
2380
gen_op_st_T0_A0(OT_WORD + s->mem_index);
2035
gen_op_subq_A0_2();
2036
gen_op_st_T0_A0[OT_WORD + s->mem_index]();
2381
2037
}
2382
gen_op_mov_reg_A0(2, R_ESP);
2383
} else
2038
gen_op_movq_ESP_A0();
2039
} else
2384
2040
#endif
2385
2041
{
2386
gen_op_movl_A0_reg(R_ESP);
2042
gen_op_movl_A0_reg[R_ESP]();
2387
2043
if (!s->dflag)
2388
gen_op_addl_A0_im(-2);
2044
gen_op_subl_A0_2();
2389
2045
else
2390
gen_op_addl_A0_im(-4);
2046
gen_op_subl_A0_4();
2391
2047
if (s->ss32) {
2392
2048
if (s->addseg) {
2393
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2394
gen_op_addl_A0_seg(R_SS);
2049
gen_op_movl_T1_A0();
2050
gen_op_addl_A0_SS();
2395
2051
}
2396
2052
} else {
2397
2053
gen_op_andl_A0_ffff();
2398
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2399
gen_op_addl_A0_seg(R_SS);
2054
gen_op_movl_T1_A0();
2055
gen_op_addl_A0_SS();
2400
2056
}
2401
gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2057
gen_op_st_T0_A0[s->dflag + 1 + s->mem_index]();
2402
2058
if (s->ss32 && !s->addseg)
2403
gen_op_mov_reg_A0(1, R_ESP);
2059
gen_op_movl_ESP_A0();
2404
2060
else
2405
gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2061
gen_op_mov_reg_T1[s->ss32 + 1][R_ESP]();
2406
2062
}
2407
2063
}
2408
2064
2412
2068
{
2413
2069
#ifdef TARGET_X86_64
2414
2070
if (CODE64(s)) {
2415
gen_op_movq_A0_reg(R_ESP);
2071
gen_op_movq_A0_reg[R_ESP]();
2416
2072
if (s->dflag) {
2417
gen_op_addq_A0_im(-8);
2418
gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2073
gen_op_subq_A0_8();
2074
gen_op_st_T1_A0[OT_QUAD + s->mem_index]();
2419
2075
} else {
2420
gen_op_addq_A0_im(-2);
2421
gen_op_st_T0_A0(OT_WORD + s->mem_index);
2076
gen_op_subq_A0_2();
2077
gen_op_st_T0_A0[OT_WORD + s->mem_index]();
2422
2078
}
2423
gen_op_mov_reg_A0(2, R_ESP);
2424
} else
2079
gen_op_movq_ESP_A0();
2080
} else
2425
2081
#endif
2426
2082
{
2427
gen_op_movl_A0_reg(R_ESP);
2083
gen_op_movl_A0_reg[R_ESP]();
2428
2084
if (!s->dflag)
2429
gen_op_addl_A0_im(-2);
2085
gen_op_subl_A0_2();
2430
2086
else
2431
gen_op_addl_A0_im(-4);
2087
gen_op_subl_A0_4();
2432
2088
if (s->ss32) {
2433
2089
if (s->addseg) {
2434
gen_op_addl_A0_seg(R_SS);
2090
gen_op_addl_A0_SS();
2435
2091
}
2436
2092
} else {
2437
2093
gen_op_andl_A0_ffff();
2438
gen_op_addl_A0_seg(R_SS);
2094
gen_op_addl_A0_SS();
2439
2095
}
2440
gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2441
2096
gen_op_st_T1_A0[s->dflag + 1 + s->mem_index]();
2097
2442
2098
if (s->ss32 && !s->addseg)
2443
gen_op_mov_reg_A0(1, R_ESP);
2099
gen_op_movl_ESP_A0();
2444
2100
else
2445
2101
gen_stack_update(s, (-2) << s->dflag);
2446
2102
}
2451
2107
{
2452
2108
#ifdef TARGET_X86_64
2453
2109
if (CODE64(s)) {
2454
gen_op_movq_A0_reg(R_ESP);
2455
gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2456
} else
2110
gen_op_movq_A0_reg[R_ESP]();
2111
gen_op_ld_T0_A0[(s->dflag ? OT_QUAD : OT_WORD) + s->mem_index]();
2112
} else
2457
2113
#endif
2458
2114
{
2459
gen_op_movl_A0_reg(R_ESP);
2115
gen_op_movl_A0_reg[R_ESP]();
2460
2116
if (s->ss32) {
2461
2117
if (s->addseg)
2462
gen_op_addl_A0_seg(R_SS);
2118
gen_op_addl_A0_SS();
2463
2119
} else {
2464
2120
gen_op_andl_A0_ffff();
2465
gen_op_addl_A0_seg(R_SS);
2121
gen_op_addl_A0_SS();
2466
2122
}
2467
gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2123
gen_op_ld_T0_A0[s->dflag + 1 + s->mem_index]();
2468
2124
}
2469
2125
}
2470
2126
2482
2138
2483
2139
static void gen_stack_A0(DisasContext *s)
2484
2140
{
2485
gen_op_movl_A0_reg(R_ESP);
2141
gen_op_movl_A0_ESP();
2486
2142
if (!s->ss32)
2487
2143
gen_op_andl_A0_ffff();
2488
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2144
gen_op_movl_T1_A0();
2489
2145
if (s->addseg)
2490
gen_op_addl_A0_seg(R_SS);
2146
gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2491
2147
}
2492
2148
2493
2149
/* NOTE: wrap around in 16 bit not fully handled */
2494
2150
static void gen_pusha(DisasContext *s)
2495
2151
{
2496
2152
int i;
2497
gen_op_movl_A0_reg(R_ESP);
2153
gen_op_movl_A0_ESP();
2498
2154
gen_op_addl_A0_im(-16 << s->dflag);
2499
2155
if (!s->ss32)
2500
2156
gen_op_andl_A0_ffff();
2501
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2157
gen_op_movl_T1_A0();
2502
2158
if (s->addseg)
2503
gen_op_addl_A0_seg(R_SS);
2159
gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2504
2160
for(i = 0;i < 8; i++) {
2505
gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2506
gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2161
gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
2162
gen_op_st_T0_A0[OT_WORD + s->dflag + s->mem_index]();
2507
2163
gen_op_addl_A0_im(2 << s->dflag);
2508
2164
}
2509
gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2165
gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2510
2166
}
2511
2167
2512
2168
/* NOTE: wrap around in 16 bit not fully handled */
2513
2169
static void gen_popa(DisasContext *s)
2514
2170
{
2515
2171
int i;
2516
gen_op_movl_A0_reg(R_ESP);
2172
gen_op_movl_A0_ESP();
2517
2173
if (!s->ss32)
2518
2174
gen_op_andl_A0_ffff();
2519
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2520
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2175
gen_op_movl_T1_A0();
2176
gen_op_addl_T1_im(16 << s->dflag);
2521
2177
if (s->addseg)
2522
gen_op_addl_A0_seg(R_SS);
2178
gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2523
2179
for(i = 0;i < 8; i++) {
2524
2180
/* ESP is not reloaded */
2525
2181
if (i != 3) {
2526
gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2527
gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2182
gen_op_ld_T0_A0[OT_WORD + s->dflag + s->mem_index]();
2183
gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
2528
2184
}
2529
2185
gen_op_addl_A0_im(2 << s->dflag);
2530
2186
}
2531
gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2187
gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2532
2188
}
2533
2189
2534
2190
static void gen_enter(DisasContext *s, int esp_addend, int level)
2540
2196
if (CODE64(s)) {
2541
2197
ot = s->dflag ? OT_QUAD : OT_WORD;
2542
2198
opsize = 1 << ot;
2543
2544
gen_op_movl_A0_reg(R_ESP);
2199
2200
gen_op_movl_A0_ESP();
2545
2201
gen_op_addq_A0_im(-opsize);
2546
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2202
gen_op_movl_T1_A0();
2547
2203
2548
2204
/* push bp */
2549
gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2550
gen_op_st_T0_A0(ot + s->mem_index);
2205
gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2206
gen_op_st_T0_A0[ot + s->mem_index]();
2551
2207
if (level) {
2552
/* XXX: must save state */
2553
tcg_gen_helper_0_3(helper_enter64_level,
2554
tcg_const_i32(level),
2555
tcg_const_i32((ot == OT_QUAD)),
2556
cpu_T[1]);
2208
gen_op_enter64_level(level, (ot == OT_QUAD));
2557
2209
}
2558
gen_op_mov_reg_T1(ot, R_EBP);
2559
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2560
gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2561
} else
2210
gen_op_mov_reg_T1[ot][R_EBP]();
2211
gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
2212
gen_op_mov_reg_T1[OT_QUAD][R_ESP]();
2213
} else
2562
2214
#endif
2563
2215
{
2564
2216
ot = s->dflag + OT_WORD;
2565
2217
opsize = 2 << s->dflag;
2566
2567
gen_op_movl_A0_reg(R_ESP);
2218
2219
gen_op_movl_A0_ESP();
2568
2220
gen_op_addl_A0_im(-opsize);
2569
2221
if (!s->ss32)
2570
2222
gen_op_andl_A0_ffff();
2571
tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2223
gen_op_movl_T1_A0();
2572
2224
if (s->addseg)
2573
gen_op_addl_A0_seg(R_SS);
2225
gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
2574
2226
/* push bp */
2575
gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2576
gen_op_st_T0_A0(ot + s->mem_index);
2227
gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2228
gen_op_st_T0_A0[ot + s->mem_index]();
2577
2229
if (level) {
2578
/* XXX: must save state */
2579
tcg_gen_helper_0_3(helper_enter_level,
2580
tcg_const_i32(level),
2581
tcg_const_i32(s->dflag),
2582
cpu_T[1]);
2230
gen_op_enter_level(level, s->dflag);
2583
2231
}
2584
gen_op_mov_reg_T1(ot, R_EBP);
2585
tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2586
gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2232
gen_op_mov_reg_T1[ot][R_EBP]();
2233
gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
2234
gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2587
2235
}
2588
2236
}
2589
2237
2592
2240
if (s->cc_op != CC_OP_DYNAMIC)
2593
2241
gen_op_set_cc_op(s->cc_op);
2594
2242
gen_jmp_im(cur_eip);
2595
tcg_gen_helper_0_1(helper_raise_exception, tcg_const_i32(trapno));
2243
gen_op_raise_exception(trapno);
2596
2244
s->is_jmp = 3;
2597
2245
}
2598
2246
2599
2247
/* an interrupt is different from an exception because of the
2600
privilege checks */
2601
static void gen_interrupt(DisasContext *s, int intno,
2248
priviledge checks */
2249
static void gen_interrupt(DisasContext *s, int intno,
2602
2250
target_ulong cur_eip, target_ulong next_eip)
2603
2251
{
2604
2252
if (s->cc_op != CC_OP_DYNAMIC)
2605
2253
gen_op_set_cc_op(s->cc_op);
2606
2254
gen_jmp_im(cur_eip);
2607
tcg_gen_helper_0_2(helper_raise_interrupt,
2608
tcg_const_i32(intno),
2609
tcg_const_i32(next_eip - cur_eip));
2255
gen_op_raise_interrupt(intno, (int)(next_eip - cur_eip));
2610
2256
s->is_jmp = 3;
2611
2257
}
2612
2258
2615
2261
if (s->cc_op != CC_OP_DYNAMIC)
2616
2262
gen_op_set_cc_op(s->cc_op);
2617
2263
gen_jmp_im(cur_eip);
2618
tcg_gen_helper_0_0(helper_debug);
2264
gen_op_debug();
2619
2265
s->is_jmp = 3;
2620
2266
}
2621
2267
2626
2272
if (s->cc_op != CC_OP_DYNAMIC)
2627
2273
gen_op_set_cc_op(s->cc_op);
2628
2274
if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2629
tcg_gen_helper_0_0(helper_reset_inhibit_irq);
2275
gen_op_reset_inhibit_irq();
2630
2276
}
2631
2277
if (s->singlestep_enabled) {
2632
tcg_gen_helper_0_0(helper_debug);
2278
gen_op_debug();
2633
2279
} else if (s->tf) {
2634
tcg_gen_helper_0_0(helper_single_step);
2280
gen_op_raise_exception(EXCP01_SSTP);
2635
2281
} else {
2636
tcg_gen_exit_tb(0);
2282
gen_op_movl_T0_0();
2283
gen_op_exit_tb();
2637
2284
}
2638
2285
s->is_jmp = 3;
2639
2286
}
2660
2307
gen_jmp_tb(s, eip, 0);
2661
2308
}
2662
2309
2663
static inline void gen_ldq_env_A0(int idx, int offset)
2664
{
2665
int mem_index = (idx >> 2) - 1;
2666
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2667
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2668
}
2669
2670
static inline void gen_stq_env_A0(int idx, int offset)
2671
{
2672
int mem_index = (idx >> 2) - 1;
2673
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2674
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2675
}
2676
2677
static inline void gen_ldo_env_A0(int idx, int offset)
2678
{
2679
int mem_index = (idx >> 2) - 1;
2680
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2681
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2682
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2683
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2684
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2685
}
2686
2687
static inline void gen_sto_env_A0(int idx, int offset)
2688
{
2689
int mem_index = (idx >> 2) - 1;
2690
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2691
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2692
tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2693
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2694
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2695
}
2696
2697
static inline void gen_op_movo(int d_offset, int s_offset)
2698
{
2699
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2700
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2701
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2702
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2703
}
2704
2705
static inline void gen_op_movq(int d_offset, int s_offset)
2706
{
2707
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2708
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2709
}
2710
2711
static inline void gen_op_movl(int d_offset, int s_offset)
2712
{
2713
tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2714
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2715
}
2716
2717
static inline void gen_op_movq_env_0(int d_offset)
2718
{
2719
tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2720
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2721
}
2722
2723
#define SSE_SPECIAL ((void *)1)
2724
#define SSE_DUMMY ((void *)2)
2725
2726
#define MMX_OP2(x) { helper_ ## x ## _mmx, helper_ ## x ## _xmm }
2727
#define SSE_FOP(x) { helper_ ## x ## ps, helper_ ## x ## pd, \
2728
helper_ ## x ## ss, helper_ ## x ## sd, }
2729
2730
static void *sse_op_table1[256][4] = {
2731
/* 3DNow! extensions */
2732
[0x0e] = { SSE_DUMMY }, /* femms */
2733
[0x0f] = { SSE_DUMMY }, /* pf... */
2310
static void gen_movtl_T0_im(target_ulong val)
2311
{
2312
#ifdef TARGET_X86_64
2313
if ((int32_t)val == val) {
2314
gen_op_movl_T0_im(val);
2315
} else {
2316
gen_op_movq_T0_im64(val >> 32, val);
2317
}
2318
#else
2319
gen_op_movl_T0_im(val);
2320
#endif
2321
}
2322
2323
static void gen_movtl_T1_im(target_ulong val)
2324
{
2325
#ifdef TARGET_X86_64
2326
if ((int32_t)val == val) {
2327
gen_op_movl_T1_im(val);
2328
} else {
2329
gen_op_movq_T1_im64(val >> 32, val);
2330
}
2331
#else
2332
gen_op_movl_T1_im(val);
2333
#endif
2334
}
2335
2336
static void gen_add_A0_im(DisasContext *s, int val)
2337
{
2338
#ifdef TARGET_X86_64
2339
if (CODE64(s))
2340
gen_op_addq_A0_im(val);
2341
else
2342
#endif
2343
gen_op_addl_A0_im(val);
2344
}
2345
2346
static GenOpFunc1 *gen_ldq_env_A0[3] = {
2347
gen_op_ldq_raw_env_A0,
2348
#ifndef CONFIG_USER_ONLY
2349
gen_op_ldq_kernel_env_A0,
2350
gen_op_ldq_user_env_A0,
2351
#endif
2352
};
2353
2354
static GenOpFunc1 *gen_stq_env_A0[3] = {
2355
gen_op_stq_raw_env_A0,
2356
#ifndef CONFIG_USER_ONLY
2357
gen_op_stq_kernel_env_A0,
2358
gen_op_stq_user_env_A0,
2359
#endif
2360
};
2361
2362
static GenOpFunc1 *gen_ldo_env_A0[3] = {
2363
gen_op_ldo_raw_env_A0,
2364
#ifndef CONFIG_USER_ONLY
2365
gen_op_ldo_kernel_env_A0,
2366
gen_op_ldo_user_env_A0,
2367
#endif
2368
};
2369
2370
static GenOpFunc1 *gen_sto_env_A0[3] = {
2371
gen_op_sto_raw_env_A0,
2372
#ifndef CONFIG_USER_ONLY
2373
gen_op_sto_kernel_env_A0,
2374
gen_op_sto_user_env_A0,
2375
#endif
2376
};
2377
2378
#define SSE_SPECIAL ((GenOpFunc2 *)1)
2379
2380
#define MMX_OP2(x) { gen_op_ ## x ## _mmx, gen_op_ ## x ## _xmm }
2381
#define SSE_FOP(x) { gen_op_ ## x ## ps, gen_op_ ## x ## pd, \
2382
gen_op_ ## x ## ss, gen_op_ ## x ## sd, }
2383
2384
static GenOpFunc2 *sse_op_table1[256][4] = {
2734
2385
/* pure SSE operations */
2735
2386
[0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2736
2387
[0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2737
2388
[0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2738
2389
[0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2739
[0x14] = { helper_punpckldq_xmm, helper_punpcklqdq_xmm },
2740
[0x15] = { helper_punpckhdq_xmm, helper_punpckhqdq_xmm },
2390
[0x14] = { gen_op_punpckldq_xmm, gen_op_punpcklqdq_xmm },
2391
[0x15] = { gen_op_punpckhdq_xmm, gen_op_punpckhqdq_xmm },
2741
2392
[0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2742
2393
[0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2743
2394
2747
2398
[0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */
2748
2399
[0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2749
2400
[0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2750
[0x2e] = { helper_ucomiss, helper_ucomisd },
2751
[0x2f] = { helper_comiss, helper_comisd },
2401
[0x2e] = { gen_op_ucomiss, gen_op_ucomisd },
2402
[0x2f] = { gen_op_comiss, gen_op_comisd },
2752
2403
[0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2753
2404
[0x51] = SSE_FOP(sqrt),
2754
[0x52] = { helper_rsqrtps, NULL, helper_rsqrtss, NULL },
2755
[0x53] = { helper_rcpps, NULL, helper_rcpss, NULL },
2756
[0x54] = { helper_pand_xmm, helper_pand_xmm }, /* andps, andpd */
2757
[0x55] = { helper_pandn_xmm, helper_pandn_xmm }, /* andnps, andnpd */
2758
[0x56] = { helper_por_xmm, helper_por_xmm }, /* orps, orpd */
2759
[0x57] = { helper_pxor_xmm, helper_pxor_xmm }, /* xorps, xorpd */
2405
[0x52] = { gen_op_rsqrtps, NULL, gen_op_rsqrtss, NULL },
2406
[0x53] = { gen_op_rcpps, NULL, gen_op_rcpss, NULL },
2407
[0x54] = { gen_op_pand_xmm, gen_op_pand_xmm }, /* andps, andpd */
2408
[0x55] = { gen_op_pandn_xmm, gen_op_pandn_xmm }, /* andnps, andnpd */
2409
[0x56] = { gen_op_por_xmm, gen_op_por_xmm }, /* orps, orpd */
2410
[0x57] = { gen_op_pxor_xmm, gen_op_pxor_xmm }, /* xorps, xorpd */
2760
2411
[0x58] = SSE_FOP(add),
2761
2412
[0x59] = SSE_FOP(mul),
2762
[0x5a] = { helper_cvtps2pd, helper_cvtpd2ps,
2763
helper_cvtss2sd, helper_cvtsd2ss },
2764
[0x5b] = { helper_cvtdq2ps, helper_cvtps2dq, helper_cvttps2dq },
2413
[0x5a] = { gen_op_cvtps2pd, gen_op_cvtpd2ps,
2414
gen_op_cvtss2sd, gen_op_cvtsd2ss },
2415
[0x5b] = { gen_op_cvtdq2ps, gen_op_cvtps2dq, gen_op_cvttps2dq },
2765
2416
[0x5c] = SSE_FOP(sub),
2766
2417
[0x5d] = SSE_FOP(min),
2767
2418
[0x5e] = SSE_FOP(div),
2768
2419
[0x5f] = SSE_FOP(max),
2769
2420
2770
2421
[0xc2] = SSE_FOP(cmpeq),
2771
[0xc6] = { helper_shufps, helper_shufpd },
2772
2773
[0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2774
[0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2422
[0xc6] = { (GenOpFunc2 *)gen_op_shufps, (GenOpFunc2 *)gen_op_shufpd },
2775
2423
2776
2424
/* MMX ops and their SSE extensions */
2777
2425
[0x60] = MMX_OP2(punpcklbw),
2786
2434
[0x69] = MMX_OP2(punpckhwd),
2787
2435
[0x6a] = MMX_OP2(punpckhdq),
2788
2436
[0x6b] = MMX_OP2(packssdw),
2789
[0x6c] = { NULL, helper_punpcklqdq_xmm },
2790
[0x6d] = { NULL, helper_punpckhqdq_xmm },
2437
[0x6c] = { NULL, gen_op_punpcklqdq_xmm },
2438
[0x6d] = { NULL, gen_op_punpckhqdq_xmm },
2791
2439
[0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2792
2440
[0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2793
[0x70] = { helper_pshufw_mmx,
2794
helper_pshufd_xmm,
2795
helper_pshufhw_xmm,
2796
helper_pshuflw_xmm },
2441
[0x70] = { (GenOpFunc2 *)gen_op_pshufw_mmx,
2442
(GenOpFunc2 *)gen_op_pshufd_xmm,
2443
(GenOpFunc2 *)gen_op_pshufhw_xmm,
2444
(GenOpFunc2 *)gen_op_pshuflw_xmm },
2797
2445
[0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2798
2446
[0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2799
2447
[0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2800
2448
[0x74] = MMX_OP2(pcmpeqb),
2801
2449
[0x75] = MMX_OP2(pcmpeqw),
2802
2450
[0x76] = MMX_OP2(pcmpeql),
2803
[0x77] = { SSE_DUMMY }, /* emms */
2804
[0x7c] = { NULL, helper_haddpd, NULL, helper_haddps },
2805
[0x7d] = { NULL, helper_hsubpd, NULL, helper_hsubps },
2451
[0x77] = { SSE_SPECIAL }, /* emms */
2452
[0x7c] = { NULL, gen_op_haddpd, NULL, gen_op_haddps },
2453
[0x7d] = { NULL, gen_op_hsubpd, NULL, gen_op_hsubps },
2806
2454
[0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2807
2455
[0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2808
2456
[0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2809
2457
[0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2810
[0xd0] = { NULL, helper_addsubpd, NULL, helper_addsubps },
2458
[0xd0] = { NULL, gen_op_addsubpd, NULL, gen_op_addsubps },
2811
2459
[0xd1] = MMX_OP2(psrlw),
2812
2460
[0xd2] = MMX_OP2(psrld),
2813
2461
[0xd3] = MMX_OP2(psrlq),
2829
2477
[0xe3] = MMX_OP2(pavgw),
2830
2478
[0xe4] = MMX_OP2(pmulhuw),
2831
2479
[0xe5] = MMX_OP2(pmulhw),
2832
[0xe6] = { NULL, helper_cvttpd2dq, helper_cvtdq2pd, helper_cvtpd2dq },
2480
[0xe6] = { NULL, gen_op_cvttpd2dq, gen_op_cvtdq2pd, gen_op_cvtpd2dq },
2833
2481
[0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2834
2482
[0xe8] = MMX_OP2(psubsb),
2835
2483
[0xe9] = MMX_OP2(psubsw),
2856
2504
[0xfe] = MMX_OP2(paddl),
2857
2505
};
2858
2506
2859
static void *sse_op_table2[3 * 8][2] = {
2507
static GenOpFunc2 *sse_op_table2[3 * 8][2] = {
2860
2508
[0 + 2] = MMX_OP2(psrlw),
2861
2509
[0 + 4] = MMX_OP2(psraw),
2862
2510
[0 + 6] = MMX_OP2(psllw),
2864
2512
[8 + 4] = MMX_OP2(psrad),
2865
2513
[8 + 6] = MMX_OP2(pslld),
2866
2514
[16 + 2] = MMX_OP2(psrlq),
2867
[16 + 3] = { NULL, helper_psrldq_xmm },
2515
[16 + 3] = { NULL, gen_op_psrldq_xmm },
2868
2516
[16 + 6] = MMX_OP2(psllq),
2869
[16 + 7] = { NULL, helper_pslldq_xmm },
2870
};
2871
2872
static void *sse_op_table3[4 * 3] = {
2873
helper_cvtsi2ss,
2874
helper_cvtsi2sd,
2875
X86_64_ONLY(helper_cvtsq2ss),
2876
X86_64_ONLY(helper_cvtsq2sd),
2877
2878
helper_cvttss2si,
2879
helper_cvttsd2si,
2880
X86_64_ONLY(helper_cvttss2sq),
2881
X86_64_ONLY(helper_cvttsd2sq),
2882
2883
helper_cvtss2si,
2884
helper_cvtsd2si,
2885
X86_64_ONLY(helper_cvtss2sq),
2886
X86_64_ONLY(helper_cvtsd2sq),
2887
};
2888
2889
static void *sse_op_table4[8][4] = {
2517
[16 + 7] = { NULL, gen_op_pslldq_xmm },
2518
};
2519
2520
static GenOpFunc1 *sse_op_table3[4 * 3] = {
2521
gen_op_cvtsi2ss,
2522
gen_op_cvtsi2sd,
2523
X86_64_ONLY(gen_op_cvtsq2ss),
2524
X86_64_ONLY(gen_op_cvtsq2sd),
2525
2526
gen_op_cvttss2si,
2527
gen_op_cvttsd2si,
2528
X86_64_ONLY(gen_op_cvttss2sq),
2529
X86_64_ONLY(gen_op_cvttsd2sq),
2530
2531
gen_op_cvtss2si,
2532
gen_op_cvtsd2si,
2533
X86_64_ONLY(gen_op_cvtss2sq),
2534
X86_64_ONLY(gen_op_cvtsd2sq),
2535
};
2536
2537
static GenOpFunc2 *sse_op_table4[8][4] = {
2890
2538
SSE_FOP(cmpeq),
2891
2539
SSE_FOP(cmplt),
2892
2540
SSE_FOP(cmple),
2896
2544
SSE_FOP(cmpnle),
2897
2545
SSE_FOP(cmpord),
2898
2546
};
2899
2900
static void *sse_op_table5[256] = {
2901
[0x0c] = helper_pi2fw,
2902
[0x0d] = helper_pi2fd,
2903
[0x1c] = helper_pf2iw,
2904
[0x1d] = helper_pf2id,
2905
[0x8a] = helper_pfnacc,
2906
[0x8e] = helper_pfpnacc,
2907
[0x90] = helper_pfcmpge,
2908
[0x94] = helper_pfmin,
2909
[0x96] = helper_pfrcp,
2910
[0x97] = helper_pfrsqrt,
2911
[0x9a] = helper_pfsub,
2912
[0x9e] = helper_pfadd,
2913
[0xa0] = helper_pfcmpgt,
2914
[0xa4] = helper_pfmax,
2915
[0xa6] = helper_movq, /* pfrcpit1; no need to actually increase precision */
2916
[0xa7] = helper_movq, /* pfrsqit1 */
2917
[0xaa] = helper_pfsubr,
2918
[0xae] = helper_pfacc,
2919
[0xb0] = helper_pfcmpeq,
2920
[0xb4] = helper_pfmul,
2921
[0xb6] = helper_movq, /* pfrcpit2 */
2922
[0xb7] = helper_pmulhrw_mmx,
2923
[0xbb] = helper_pswapd,
2924
[0xbf] = helper_pavgb_mmx /* pavgusb */
2925
};
2926
2927
struct sse_op_helper_s {
2928
void *op[2]; uint32_t ext_mask;
2929
};
2930
#define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
2931
#define SSE41_OP(x) { { NULL, helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
2932
#define SSE42_OP(x) { { NULL, helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
2933
#define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
2934
static struct sse_op_helper_s sse_op_table6[256] = {
2935
[0x00] = SSSE3_OP(pshufb),
2936
[0x01] = SSSE3_OP(phaddw),
2937
[0x02] = SSSE3_OP(phaddd),
2938
[0x03] = SSSE3_OP(phaddsw),
2939
[0x04] = SSSE3_OP(pmaddubsw),
2940
[0x05] = SSSE3_OP(phsubw),
2941
[0x06] = SSSE3_OP(phsubd),
2942
[0x07] = SSSE3_OP(phsubsw),
2943
[0x08] = SSSE3_OP(psignb),
2944
[0x09] = SSSE3_OP(psignw),
2945
[0x0a] = SSSE3_OP(psignd),
2946
[0x0b] = SSSE3_OP(pmulhrsw),
2947
[0x10] = SSE41_OP(pblendvb),
2948
[0x14] = SSE41_OP(blendvps),
2949
[0x15] = SSE41_OP(blendvpd),
2950
[0x17] = SSE41_OP(ptest),
2951
[0x1c] = SSSE3_OP(pabsb),
2952
[0x1d] = SSSE3_OP(pabsw),
2953
[0x1e] = SSSE3_OP(pabsd),
2954
[0x20] = SSE41_OP(pmovsxbw),
2955
[0x21] = SSE41_OP(pmovsxbd),
2956
[0x22] = SSE41_OP(pmovsxbq),
2957
[0x23] = SSE41_OP(pmovsxwd),
2958
[0x24] = SSE41_OP(pmovsxwq),
2959
[0x25] = SSE41_OP(pmovsxdq),
2960
[0x28] = SSE41_OP(pmuldq),
2961
[0x29] = SSE41_OP(pcmpeqq),
2962
[0x2a] = SSE41_SPECIAL, /* movntqda */
2963
[0x2b] = SSE41_OP(packusdw),
2964
[0x30] = SSE41_OP(pmovzxbw),
2965
[0x31] = SSE41_OP(pmovzxbd),
2966
[0x32] = SSE41_OP(pmovzxbq),
2967
[0x33] = SSE41_OP(pmovzxwd),
2968
[0x34] = SSE41_OP(pmovzxwq),
2969
[0x35] = SSE41_OP(pmovzxdq),
2970
[0x37] = SSE42_OP(pcmpgtq),
2971
[0x38] = SSE41_OP(pminsb),
2972
[0x39] = SSE41_OP(pminsd),
2973
[0x3a] = SSE41_OP(pminuw),
2974
[0x3b] = SSE41_OP(pminud),
2975
[0x3c] = SSE41_OP(pmaxsb),
2976
[0x3d] = SSE41_OP(pmaxsd),
2977
[0x3e] = SSE41_OP(pmaxuw),
2978
[0x3f] = SSE41_OP(pmaxud),
2979
[0x40] = SSE41_OP(pmulld),
2980
[0x41] = SSE41_OP(phminposuw),
2981
};
2982
2983
static struct sse_op_helper_s sse_op_table7[256] = {
2984
[0x08] = SSE41_OP(roundps),
2985
[0x09] = SSE41_OP(roundpd),
2986
[0x0a] = SSE41_OP(roundss),
2987
[0x0b] = SSE41_OP(roundsd),
2988
[0x0c] = SSE41_OP(blendps),
2989
[0x0d] = SSE41_OP(blendpd),
2990
[0x0e] = SSE41_OP(pblendw),
2991
[0x0f] = SSSE3_OP(palignr),
2992
[0x14] = SSE41_SPECIAL, /* pextrb */
2993
[0x15] = SSE41_SPECIAL, /* pextrw */
2994
[0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
2995
[0x17] = SSE41_SPECIAL, /* extractps */
2996
[0x20] = SSE41_SPECIAL, /* pinsrb */
2997
[0x21] = SSE41_SPECIAL, /* insertps */
2998
[0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
2999
[0x40] = SSE41_OP(dpps),
3000
[0x41] = SSE41_OP(dppd),
3001
[0x42] = SSE41_OP(mpsadbw),
3002
[0x60] = SSE42_OP(pcmpestrm),
3003
[0x61] = SSE42_OP(pcmpestri),
3004
[0x62] = SSE42_OP(pcmpistrm),
3005
[0x63] = SSE42_OP(pcmpistri),
3006
};
3007
2547
3008
2548
static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3009
2549
{
3010
2550
int b1, op1_offset, op2_offset, is_xmm, val, ot;
3011
2551
int modrm, mod, rm, reg, reg_addr, offset_addr;
3012
void *sse_op2;
2552
GenOpFunc2 *sse_op2;
2553
GenOpFunc3 *sse_op3;
3013
2554
3014
2555
b &= 0xff;
3015
if (s->prefix & PREFIX_DATA)
2556
if (s->prefix & PREFIX_DATA)
3016
2557
b1 = 1;
3017
else if (s->prefix & PREFIX_REPZ)
2558
else if (s->prefix & PREFIX_REPZ)
3018
2559
b1 = 2;
3019
else if (s->prefix & PREFIX_REPNZ)
2560
else if (s->prefix & PREFIX_REPNZ)
3020
2561
b1 = 3;
3021
2562
else
3022
2563
b1 = 0;
3023
2564
sse_op2 = sse_op_table1[b][b1];
3024
if (!sse_op2)
2565
if (!sse_op2)
3025
2566
goto illegal_op;
3026
if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
2567
if (b <= 0x5f || b == 0xc6 || b == 0xc2) {
3027
2568
is_xmm = 1;
3028
2569
} else {
3029
2570
if (b1 == 0) {
3044
2585
return;
3045
2586
}
3046
2587
if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
3047
if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3048
goto illegal_op;
3049
if (b == 0x0e) {
3050
if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3051
goto illegal_op;
3052
/* femms */
3053
tcg_gen_helper_0_0(helper_emms);
3054
return;
3055
}
2588
goto illegal_op;
3056
2589
if (b == 0x77) {
3057
2590
/* emms */
3058
tcg_gen_helper_0_0(helper_emms);
2591
gen_op_emms();
3059
2592
return;
3060
2593
}
3061
2594
/* prepare MMX state (XXX: optimize by storing fptt and fptags in
3062
2595
the static cpu state) */
3063
2596
if (!is_xmm) {
3064
tcg_gen_helper_0_0(helper_enter_mmx);
2597
gen_op_enter_mmx();
3065
2598
}
3066
2599
3067
2600
modrm = ldub_code(s->pc++);
3073
2606
b |= (b1 << 8);
3074
2607
switch(b) {
3075
2608
case 0x0e7: /* movntq */
3076
if (mod == 3)
2609
if (mod == 3)
3077
2610
goto illegal_op;
3078
2611
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3079
gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
2612
gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
3080
2613
break;
3081
2614
case 0x1e7: /* movntdq */
3082
2615
case 0x02b: /* movntps */
3085
2618
if (mod == 3)
3086
2619
goto illegal_op;
3087
2620
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3088
gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
2621
gen_sto_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
3089
2622
break;
3090
2623
case 0x6e: /* movd mm, ea */
3091
2624
#ifdef TARGET_X86_64
3092
2625
if (s->dflag == 2) {
3093
2626
gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3094
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3095
} else
2627
gen_op_movq_mm_T0_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
2628
} else
3096
2629
#endif
3097
2630
{
3098
2631
gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3099
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3100
offsetof(CPUX86State,fpregs[reg].mmx));
3101
tcg_gen_helper_0_2(helper_movl_mm_T0_mmx, cpu_ptr0, cpu_T[0]);
2632
gen_op_movl_mm_T0_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
3102
2633
}
3103
2634
break;
3104
2635
case 0x16e: /* movd xmm, ea */
3105
2636
#ifdef TARGET_X86_64
3106
2637
if (s->dflag == 2) {
3107
2638
gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3108
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3109
offsetof(CPUX86State,xmm_regs[reg]));
3110
tcg_gen_helper_0_2(helper_movq_mm_T0_xmm, cpu_ptr0, cpu_T[0]);
3111
} else
2639
gen_op_movq_mm_T0_xmm(offsetof(CPUX86State,xmm_regs[reg]));
2640
} else
3112
2641
#endif
3113
2642
{
3114
2643
gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3115
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3116
offsetof(CPUX86State,xmm_regs[reg]));
3117
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3118
tcg_gen_helper_0_2(helper_movl_mm_T0_xmm, cpu_ptr0, cpu_tmp2_i32);
2644
gen_op_movl_mm_T0_xmm(offsetof(CPUX86State,xmm_regs[reg]));
3119
2645
}
3120
2646
break;
3121
2647
case 0x6f: /* movq mm, ea */
3122
2648
if (mod != 3) {
3123
2649
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3124
gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
2650
gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
3125
2651
} else {
3126
2652
rm = (modrm & 7);
3127
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3128
offsetof(CPUX86State,fpregs[rm].mmx));
3129
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3130
offsetof(CPUX86State,fpregs[reg].mmx));
2653
gen_op_movq(offsetof(CPUX86State,fpregs[reg].mmx),
2654
offsetof(CPUX86State,fpregs[rm].mmx));
3131
2655
}
3132
2656
break;
3133
2657
case 0x010: /* movups */
3138
2662
case 0x26f: /* movdqu xmm, ea */
3139
2663
if (mod != 3) {
3140
2664
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3141
gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
2665
gen_ldo_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
3142
2666
} else {
3143
2667
rm = (modrm & 7) | REX_B(s);
3144
2668
gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3148
2672
case 0x210: /* movss xmm, ea */
3149
2673
if (mod != 3) {
3150
2674
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3151
gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3152
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2675
gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
2676
gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3153
2677
gen_op_movl_T0_0();
3154
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3155
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3156
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
2678
gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
2679
gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
2680
gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3157
2681
} else {
3158
2682
rm = (modrm & 7) | REX_B(s);
3159
2683
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3163
2687
case 0x310: /* movsd xmm, ea */
3164
2688
if (mod != 3) {
3165
2689
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3166
gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2690
gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3167
2691
gen_op_movl_T0_0();
3168
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3169
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
2692
gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
2693
gen_op_movl_env_T0(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3170
2694
} else {
3171
2695
rm = (modrm & 7) | REX_B(s);
3172
2696
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3177
2701
case 0x112: /* movlpd */
3178
2702
if (mod != 3) {
3179
2703
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3180
gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2704
gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3181
2705
} else {
3182
2706
/* movhlps */
3183
2707
rm = (modrm & 7) | REX_B(s);
3188
2712
case 0x212: /* movsldup */
3189
2713
if (mod != 3) {
3190
2714
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3191
gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
2715
gen_ldo_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
3192
2716
} else {
3193
2717
rm = (modrm & 7) | REX_B(s);
3194
2718
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3204
2728
case 0x312: /* movddup */
3205
2729
if (mod != 3) {
3206
2730
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3207
gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2731
gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3208
2732
} else {
3209
2733
rm = (modrm & 7) | REX_B(s);
3210
2734
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3217
2741
case 0x116: /* movhpd */
3218
2742
if (mod != 3) {
3219
2743
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3220
gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
2744
gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3221
2745
} else {
3222
2746
/* movlhps */
3223
2747
rm = (modrm & 7) | REX_B(s);
3228
2752
case 0x216: /* movshdup */
3229
2753
if (mod != 3) {
3230
2754
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3231
gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
2755
gen_ldo_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
3232
2756
} else {
3233
2757
rm = (modrm & 7) | REX_B(s);
3234
2758
gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3244
2768
case 0x7e: /* movd ea, mm */
3245
2769
#ifdef TARGET_X86_64
3246
2770
if (s->dflag == 2) {
3247
tcg_gen_ld_i64(cpu_T[0], cpu_env,
3248
offsetof(CPUX86State,fpregs[reg].mmx));
2771
gen_op_movq_T0_mm_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
3249
2772
gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3250
} else
2773
} else
3251
2774
#endif
3252
2775
{
3253
tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3254
offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
2776
gen_op_movl_T0_mm_mmx(offsetof(CPUX86State,fpregs[reg].mmx));
3255
2777
gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3256
2778
}
3257
2779
break;
3258
2780
case 0x17e: /* movd ea, xmm */
3259
2781
#ifdef TARGET_X86_64
3260
2782
if (s->dflag == 2) {
3261
tcg_gen_ld_i64(cpu_T[0], cpu_env,
3262
offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2783
gen_op_movq_T0_mm_xmm(offsetof(CPUX86State,xmm_regs[reg]));
3263
2784
gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3264
} else
2785
} else
3265
2786
#endif
3266
2787
{
3267
tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3268
offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2788
gen_op_movl_T0_mm_xmm(offsetof(CPUX86State,xmm_regs[reg]));
3269
2789
gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3270
2790
}
3271
2791
break;
3272
2792
case 0x27e: /* movq xmm, ea */
3273
2793
if (mod != 3) {
3274
2794
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3275
gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2795
gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3276
2796
} else {
3277
2797
rm = (modrm & 7) | REX_B(s);
3278
2798
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3283
2803
case 0x7f: /* movq ea, mm */
3284
2804
if (mod != 3) {
3285
2805
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3286
gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
2806
gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,fpregs[reg].mmx));
3287
2807
} else {
3288
2808
rm = (modrm & 7);
3289
2809
gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3298
2818
case 0x27f: /* movdqu ea, xmm */
3299
2819
if (mod != 3) {
3300
2820
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3301
gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
2821
gen_sto_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg]));
3302
2822
} else {
3303
2823
rm = (modrm & 7) | REX_B(s);
3304
2824
gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3308
2828
case 0x211: /* movss ea, xmm */
3309
2829
if (mod != 3) {
3310
2830
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3311
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3312
gen_op_st_T0_A0(OT_LONG + s->mem_index);
2831
gen_op_movl_T0_env(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
2832
gen_op_st_T0_A0[OT_LONG + s->mem_index]();
3313
2833
} else {
3314
2834
rm = (modrm & 7) | REX_B(s);
3315
2835
gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3319
2839
case 0x311: /* movsd ea, xmm */
3320
2840
if (mod != 3) {
3321
2841
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3322
gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2842
gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3323
2843
} else {
3324
2844
rm = (modrm & 7) | REX_B(s);
3325
2845
gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3330
2850
case 0x113: /* movlpd */
3331
2851
if (mod != 3) {
3332
2852
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3333
gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
2853
gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3334
2854
} else {
3335
2855
goto illegal_op;
3336
2856
}
3339
2859
case 0x117: /* movhpd */
3340
2860
if (mod != 3) {
3341
2861
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3342
gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
2862
gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3343
2863
} else {
3344
2864
goto illegal_op;
3345
2865
}
3353
2873
val = ldub_code(s->pc++);
3354
2874
if (is_xmm) {
3355
2875
gen_op_movl_T0_im(val);
3356
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
2876
gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3357
2877
gen_op_movl_T0_0();
3358
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
2878
gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3359
2879
op1_offset = offsetof(CPUX86State,xmm_t0);
3360
2880
} else {
3361
2881
gen_op_movl_T0_im(val);
3362
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
2882
gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3363
2883
gen_op_movl_T0_0();
3364
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
2884
gen_op_movl_env_T0(offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3365
2885
op1_offset = offsetof(CPUX86State,mmx_t0);
3366
2886
}
3367
2887
sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3374
2894
rm = (modrm & 7);
3375
2895
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3376
2896
}
3377
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3378
tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3379
tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
2897
sse_op2(op2_offset, op1_offset);
3380
2898
break;
3381
2899
case 0x050: /* movmskps */
3382
2900
rm = (modrm & 7) | REX_B(s);
3383
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3384
offsetof(CPUX86State,xmm_regs[rm]));
3385
tcg_gen_helper_1_1(helper_movmskps, cpu_tmp2_i32, cpu_ptr0);
3386
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3387
gen_op_mov_reg_T0(OT_LONG, reg);
2901
gen_op_movmskps(offsetof(CPUX86State,xmm_regs[rm]));
2902
gen_op_mov_reg_T0[OT_LONG][reg]();
3388
2903
break;
3389
2904
case 0x150: /* movmskpd */
3390
2905
rm = (modrm & 7) | REX_B(s);
3391
tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3392
offsetof(CPUX86State,xmm_regs[rm]));
3393
tcg_gen_helper_1_1(helper_movmskpd, cpu_tmp2_i32, cpu_ptr0);
3394
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3395
gen_op_mov_reg_T0(OT_LONG, reg);
2906
gen_op_movmskpd(offsetof(CPUX86State,xmm_regs[rm]));
2907
gen_op_mov_reg_T0[OT_LONG][reg]();
3396
2908
break;
3397
2909
case 0x02a: /* cvtpi2ps */
3398
2910
case 0x12a: /* cvtpi2pd */
3399
tcg_gen_helper_0_0(helper_enter_mmx);
2911
gen_op_enter_mmx();
3400
2912
if (mod != 3) {
3401
2913
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3402
2914
op2_offset = offsetof(CPUX86State,mmx_t0);
3403
gen_ldq_env_A0(s->mem_index, op2_offset);
2915
gen_ldq_env_A0[s->mem_index >> 2](op2_offset);
3404
2916
} else {
3405
2917
rm = (modrm & 7);
3406
2918
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3407
2919
}
3408
2920
op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3409
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3410
tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3411
2921
switch(b >> 8) {
3412
2922
case 0x0:
3413
tcg_gen_helper_0_2(helper_cvtpi2ps, cpu_ptr0, cpu_ptr1);
2923
gen_op_cvtpi2ps(op1_offset, op2_offset);
3414
2924
break;
3415
2925
default:
3416
2926
case 0x1:
3417
tcg_gen_helper_0_2(helper_cvtpi2pd, cpu_ptr0, cpu_ptr1);
2927
gen_op_cvtpi2pd(op1_offset, op2_offset);
3418
2928
break;
3419
2929
}
3420
2930
break;
3423
2933
ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3424
2934
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3425
2935
op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3426
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3427
sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)];
3428
if (ot == OT_LONG) {
3429
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3430
tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_tmp2_i32);
3431
} else {
3432
tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_T[0]);
3433
}
2936
sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)](op1_offset);
3434
2937
break;
3435
2938
case 0x02c: /* cvttps2pi */
3436
2939
case 0x12c: /* cvttpd2pi */
3437
2940
case 0x02d: /* cvtps2pi */
3438
2941
case 0x12d: /* cvtpd2pi */
3439
tcg_gen_helper_0_0(helper_enter_mmx);
2942
gen_op_enter_mmx();
3440
2943
if (mod != 3) {
3441
2944
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3442
2945
op2_offset = offsetof(CPUX86State,xmm_t0);
3443
gen_ldo_env_A0(s->mem_index, op2_offset);
2946
gen_ldo_env_A0[s->mem_index >> 2](op2_offset);
3444
2947
} else {
3445
2948
rm = (modrm & 7) | REX_B(s);
3446
2949
op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3447
2950
}
3448
2951
op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3449
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3450
tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3451
2952
switch(b) {
3452
2953
case 0x02c:
3453
tcg_gen_helper_0_2(helper_cvttps2pi, cpu_ptr0, cpu_ptr1);
2954
gen_op_cvttps2pi(op1_offset, op2_offset);
3454
2955
break;
3455
2956
case 0x12c:
3456
tcg_gen_helper_0_2(helper_cvttpd2pi, cpu_ptr0, cpu_ptr1);
2957
gen_op_cvttpd2pi(op1_offset, op2_offset);
3457
2958
break;
3458
2959
case 0x02d:
3459
tcg_gen_helper_0_2(helper_cvtps2pi, cpu_ptr0, cpu_ptr1);
2960
gen_op_cvtps2pi(op1_offset, op2_offset);
3460
2961
break;
3461
2962
case 0x12d:
3462
tcg_gen_helper_0_2(helper_cvtpd2pi, cpu_ptr0, cpu_ptr1);
2963
gen_op_cvtpd2pi(op1_offset, op2_offset);
3463
2964
break;
3464
2965
}
3465
2966
break;
3471
2972
if (mod != 3) {
3472
2973
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3473
2974
if ((b >> 8) & 1) {
3474
gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
2975
gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3475
2976
} else {
3476
gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3477
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
2977
gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
2978
gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3478
2979
}
3479
2980
op2_offset = offsetof(CPUX86State,xmm_t0);
3480
2981
} else {
3481
2982
rm = (modrm & 7) | REX_B(s);
3482
2983
op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3483
2984
}
3484
sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
3485
(b & 1) * 4];
3486
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3487
if (ot == OT_LONG) {
3488
tcg_gen_helper_1_1(sse_op2, cpu_tmp2_i32, cpu_ptr0);
3489
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3490
} else {
3491
tcg_gen_helper_1_1(sse_op2, cpu_T[0], cpu_ptr0);
3492
}
3493
gen_op_mov_reg_T0(ot, reg);
2985
sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
2986
(b & 1) * 4](op2_offset);
2987
gen_op_mov_reg_T0[ot][reg]();
3494
2988
break;
3495
2989
case 0xc4: /* pinsrw */
3496
case 0x1c4:
2990
case 0x1c4:
3497
2991
s->rip_offset = 1;
3498
2992
gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3499
2993
val = ldub_code(s->pc++);
3500
2994
if (b1) {
3501
2995
val &= 7;
3502
tcg_gen_st16_tl(cpu_T[0], cpu_env,
3503
offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
2996
gen_op_pinsrw_xmm(offsetof(CPUX86State,xmm_regs[reg]), val);
3504
2997
} else {
3505
2998
val &= 3;
3506
tcg_gen_st16_tl(cpu_T[0], cpu_env,
3507
offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
2999
gen_op_pinsrw_mmx(offsetof(CPUX86State,fpregs[reg].mmx), val);
3508
3000
}
3509
3001
break;
3510
3002
case 0xc5: /* pextrw */
3511
case 0x1c5:
3003
case 0x1c5:
3512
3004
if (mod != 3)
3513
3005
goto illegal_op;
3514
ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3515
3006
val = ldub_code(s->pc++);
3516
3007
if (b1) {
3517
3008
val &= 7;
3518
3009
rm = (modrm & 7) | REX_B(s);
3519
tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3520
offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3010
gen_op_pextrw_xmm(offsetof(CPUX86State,xmm_regs[rm]), val);
3521
3011
} else {
3522
3012
val &= 3;
3523
3013
rm = (modrm & 7);
3524
tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3525
offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3014
gen_op_pextrw_mmx(offsetof(CPUX86State,fpregs[rm].mmx), val);
3526
3015
}
3527
3016
reg = ((modrm >> 3) & 7) | rex_r;
3528
gen_op_mov_reg_T0(ot, reg);
3017
gen_op_mov_reg_T0[OT_LONG][reg]();
3529
3018
break;
3530
3019
case 0x1d6: /* movq ea, xmm */
3531
3020
if (mod != 3) {
3532
3021
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3533
gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3022
gen_stq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3534
3023
} else {
3535
3024
rm = (modrm & 7) | REX_B(s);
3536
3025
gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3539
3028
}
3540
3029
break;
3541
3030
case 0x2d6: /* movq2dq */
3542
tcg_gen_helper_0_0(helper_enter_mmx);
3031
gen_op_enter_mmx();
3543
3032
rm = (modrm & 7);
3544
3033
gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3545
3034
offsetof(CPUX86State,fpregs[rm].mmx));
3546
3035
gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3547
3036
break;
3548
3037
case 0x3d6: /* movdq2q */
3549
tcg_gen_helper_0_0(helper_enter_mmx);
3038
gen_op_enter_mmx();
3550
3039
rm = (modrm & 7) | REX_B(s);
3551
3040
gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3552
3041
offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3557
3046
goto illegal_op;
3558
3047
if (b1) {
3559
3048
rm = (modrm & 7) | REX_B(s);
3560
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3561
tcg_gen_helper_1_1(helper_pmovmskb_xmm, cpu_tmp2_i32, cpu_ptr0);
3049
gen_op_pmovmskb_xmm(offsetof(CPUX86State,xmm_regs[rm]));
3562
3050
} else {
3563
3051
rm = (modrm & 7);
3564
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3565
tcg_gen_helper_1_1(helper_pmovmskb_mmx, cpu_tmp2_i32, cpu_ptr0);
3566
}
3567
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3568
reg = ((modrm >> 3) & 7) | rex_r;
3569
gen_op_mov_reg_T0(OT_LONG, reg);
3570
break;
3571
case 0x138:
3572
if (s->prefix & PREFIX_REPNZ)
3573
goto crc32;
3574
case 0x038:
3575
b = modrm;
3576
modrm = ldub_code(s->pc++);
3577
rm = modrm & 7;
3578
reg = ((modrm >> 3) & 7) | rex_r;
3579
mod = (modrm >> 6) & 3;
3580
3581
sse_op2 = sse_op_table6[b].op[b1];
3582
if (!sse_op2)
3583
goto illegal_op;
3584
if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3585
goto illegal_op;
3586
3587
if (b1) {
3588
op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3589
if (mod == 3) {
3590
op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3591
} else {
3592
op2_offset = offsetof(CPUX86State,xmm_t0);
3593
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3594
switch (b) {
3595
case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3596
case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3597
case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3598
gen_ldq_env_A0(s->mem_index, op2_offset +
3599
offsetof(XMMReg, XMM_Q(0)));
3600
break;
3601
case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3602
case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3603
tcg_gen_qemu_ld32u(cpu_tmp2_i32, cpu_A0,
3604
(s->mem_index >> 2) - 1);
3605
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3606
offsetof(XMMReg, XMM_L(0)));
3607
break;
3608
case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3609
tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3610
(s->mem_index >> 2) - 1);
3611
tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3612
offsetof(XMMReg, XMM_W(0)));
3613
break;
3614
case 0x2a: /* movntqda */
3615
gen_ldo_env_A0(s->mem_index, op1_offset);
3616
return;
3617
default:
3618
gen_ldo_env_A0(s->mem_index, op2_offset);
3619
}
3620
}
3621
} else {
3622
op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3623
if (mod == 3) {
3624
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3625
} else {
3626
op2_offset = offsetof(CPUX86State,mmx_t0);
3627
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3628
gen_ldq_env_A0(s->mem_index, op2_offset);
3629
}
3630
}
3631
if (sse_op2 == SSE_SPECIAL)
3632
goto illegal_op;
3633
3634
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3635
tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3636
tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3637
3638
if (b == 0x17)
3639
s->cc_op = CC_OP_EFLAGS;
3640
break;
3641
case 0x338: /* crc32 */
3642
crc32:
3643
b = modrm;
3644
modrm = ldub_code(s->pc++);
3645
reg = ((modrm >> 3) & 7) | rex_r;
3646
3647
if (b != 0xf0 && b != 0xf1)
3648
goto illegal_op;
3649
if (!(s->cpuid_ext_features & CPUID_EXT_SSE42))
3650
goto illegal_op;
3651
3652
if (b == 0xf0)
3653
ot = OT_BYTE;
3654
else if (b == 0xf1 && s->dflag != 2)
3655
if (s->prefix & PREFIX_DATA)
3656
ot = OT_WORD;
3657
else
3658
ot = OT_LONG;
3659
else
3660
ot = OT_QUAD;
3661
3662
gen_op_mov_TN_reg(OT_LONG, 0, reg);
3663
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3664
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3665
tcg_gen_helper_1_3(helper_crc32, cpu_T[0], cpu_tmp2_i32,
3666
cpu_T[0], tcg_const_i32(8 << ot));
3667
3668
ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3669
gen_op_mov_reg_T0(ot, reg);
3670
break;
3671
case 0x03a:
3672
case 0x13a:
3673
b = modrm;
3674
modrm = ldub_code(s->pc++);
3675
rm = modrm & 7;
3676
reg = ((modrm >> 3) & 7) | rex_r;
3677
mod = (modrm >> 6) & 3;
3678
3679
sse_op2 = sse_op_table7[b].op[b1];
3680
if (!sse_op2)
3681
goto illegal_op;
3682
if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
3683
goto illegal_op;
3684
3685
if (sse_op2 == SSE_SPECIAL) {
3686
ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3687
rm = (modrm & 7) | REX_B(s);
3688
if (mod != 3)
3689
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3690
reg = ((modrm >> 3) & 7) | rex_r;
3691
val = ldub_code(s->pc++);
3692
switch (b) {
3693
case 0x14: /* pextrb */
3694
tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3695
xmm_regs[reg].XMM_B(val & 15)));
3696
if (mod == 3)
3697
gen_op_mov_reg_T0(ot, rm);
3698
else
3699
tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
3700
(s->mem_index >> 2) - 1);
3701
break;
3702
case 0x15: /* pextrw */
3703
tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3704
xmm_regs[reg].XMM_W(val & 7)));
3705
if (mod == 3)
3706
gen_op_mov_reg_T0(ot, rm);
3707
else
3708
tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
3709
(s->mem_index >> 2) - 1);
3710
break;
3711
case 0x16:
3712
if (ot == OT_LONG) { /* pextrd */
3713
tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3714
offsetof(CPUX86State,
3715
xmm_regs[reg].XMM_L(val & 3)));
3716
if (mod == 3)
3717
gen_op_mov_reg_v(ot, rm, cpu_tmp2_i32);
3718
else
3719
tcg_gen_qemu_st32(cpu_tmp2_i32, cpu_A0,
3720
(s->mem_index >> 2) - 1);
3721
} else { /* pextrq */
3722
tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3723
offsetof(CPUX86State,
3724
xmm_regs[reg].XMM_Q(val & 1)));
3725
if (mod == 3)
3726
gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
3727
else
3728
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
3729
(s->mem_index >> 2) - 1);
3730
}
3731
break;
3732
case 0x17: /* extractps */
3733
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3734
xmm_regs[reg].XMM_L(val & 3)));
3735
if (mod == 3)
3736
gen_op_mov_reg_T0(ot, rm);
3737
else
3738
tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3739
(s->mem_index >> 2) - 1);
3740
break;
3741
case 0x20: /* pinsrb */
3742
if (mod == 3)
3743
gen_op_mov_TN_reg(OT_LONG, 0, rm);
3744
else
3745
tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0,
3746
(s->mem_index >> 2) - 1);
3747
tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3748
xmm_regs[reg].XMM_B(val & 15)));
3749
break;
3750
case 0x21: /* insertps */
3751
if (mod == 3)
3752
tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3753
offsetof(CPUX86State,xmm_regs[rm]
3754
.XMM_L((val >> 6) & 3)));
3755
else
3756
tcg_gen_qemu_ld32u(cpu_tmp2_i32, cpu_A0,
3757
(s->mem_index >> 2) - 1);
3758
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3759
offsetof(CPUX86State,xmm_regs[reg]
3760
.XMM_L((val >> 4) & 3)));
3761
if ((val >> 0) & 1)
3762
tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3763
cpu_env, offsetof(CPUX86State,
3764
xmm_regs[reg].XMM_L(0)));
3765
if ((val >> 1) & 1)
3766
tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3767
cpu_env, offsetof(CPUX86State,
3768
xmm_regs[reg].XMM_L(1)));
3769
if ((val >> 2) & 1)
3770
tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3771
cpu_env, offsetof(CPUX86State,
3772
xmm_regs[reg].XMM_L(2)));
3773
if ((val >> 3) & 1)
3774
tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3775
cpu_env, offsetof(CPUX86State,
3776
xmm_regs[reg].XMM_L(3)));
3777
break;
3778
case 0x22:
3779
if (ot == OT_LONG) { /* pinsrd */
3780
if (mod == 3)
3781
gen_op_mov_v_reg(ot, cpu_tmp2_i32, rm);
3782
else
3783
tcg_gen_qemu_ld32u(cpu_tmp2_i32, cpu_A0,
3784
(s->mem_index >> 2) - 1);
3785
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3786
offsetof(CPUX86State,
3787
xmm_regs[reg].XMM_L(val & 3)));
3788
} else { /* pinsrq */
3789
if (mod == 3)
3790
gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
3791
else
3792
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
3793
(s->mem_index >> 2) - 1);
3794
tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3795
offsetof(CPUX86State,
3796
xmm_regs[reg].XMM_Q(val & 1)));
3797
}
3798
break;
3799
}
3800
return;
3801
}
3802
3803
if (b1) {
3804
op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3805
if (mod == 3) {
3806
op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3807
} else {
3808
op2_offset = offsetof(CPUX86State,xmm_t0);
3809
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3810
gen_ldo_env_A0(s->mem_index, op2_offset);
3811
}
3812
} else {
3813
op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3814
if (mod == 3) {
3815
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3816
} else {
3817
op2_offset = offsetof(CPUX86State,mmx_t0);
3818
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3819
gen_ldq_env_A0(s->mem_index, op2_offset);
3820
}
3821
}
3822
val = ldub_code(s->pc++);
3823
3824
if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
3825
s->cc_op = CC_OP_EFLAGS;
3826
3827
if (s->dflag == 2)
3828
/* The helper must use entire 64-bit gp registers */
3829
val |= 1 << 8;
3830
}
3831
3832
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3833
tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3834
tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3052
gen_op_pmovmskb_mmx(offsetof(CPUX86State,fpregs[rm].mmx));
3053
}
3054
reg = ((modrm >> 3) & 7) | rex_r;
3055
gen_op_mov_reg_T0[OT_LONG][reg]();
3835
3056
break;
3836
3057
default:
3837
3058
goto illegal_op;
3839
3060
} else {
3840
3061
/* generic MMX or SSE operation */
3841
3062
switch(b) {
3063
case 0xf7:
3064
/* maskmov : we must prepare A0 */
3065
if (mod != 3)
3066
goto illegal_op;
3067
#ifdef TARGET_X86_64
3068
if (s->aflag == 2) {
3069
gen_op_movq_A0_reg[R_EDI]();
3070
} else
3071
#endif
3072
{
3073
gen_op_movl_A0_reg[R_EDI]();
3074
if (s->aflag == 0)
3075
gen_op_andl_A0_ffff();
3076
}
3077
gen_add_A0_ds_seg(s);
3078
break;
3842
3079
case 0x70: /* pshufx insn */
3843
3080
case 0xc6: /* pshufx insn */
3844
3081
case 0xc2: /* compare insns */
3857
3094
/* specific case for SSE single instructions */
3858
3095
if (b1 == 2) {
3859
3096
/* 32 bit access */
3860
gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3861
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3097
gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
3098
gen_op_movl_env_T0(offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3862
3099
} else {
3863
3100
/* 64 bit access */
3864
gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
3101
gen_ldq_env_A0[s->mem_index >> 2](offsetof(CPUX86State,xmm_t0.XMM_D(0)));
3865
3102
}
3866
3103
} else {
3867
gen_ldo_env_A0(s->mem_index, op2_offset);
3104
gen_ldo_env_A0[s->mem_index >> 2](op2_offset);
3868
3105
}
3869
3106
} else {
3870
3107
rm = (modrm & 7) | REX_B(s);
3875
3112
if (mod != 3) {
3876
3113
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3877
3114
op2_offset = offsetof(CPUX86State,mmx_t0);
3878
gen_ldq_env_A0(s->mem_index, op2_offset);
3115
gen_ldq_env_A0[s->mem_index >> 2](op2_offset);
3879
3116
} else {
3880
3117
rm = (modrm & 7);
3881
3118
op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3882
3119
}
3883
3120
}
3884
3121
switch(b) {
3885
case 0x0f: /* 3DNow! data insns */
3886
if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3887
goto illegal_op;
3888
val = ldub_code(s->pc++);
3889
sse_op2 = sse_op_table5[val];
3890
if (!sse_op2)
3891
goto illegal_op;
3892
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3893
tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3894
tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3895
break;
3896
3122
case 0x70: /* pshufx insn */
3897
3123
case 0xc6: /* pshufx insn */
3898
3124
val = ldub_code(s->pc++);
3899
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3900
tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3901
tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3125
sse_op3 = (GenOpFunc3 *)sse_op2;
3126
sse_op3(op1_offset, op2_offset, val);
3902
3127
break;
3903
3128
case 0xc2:
3904
3129
/* compare insns */
3906
3131
if (val >= 8)
3907
3132
goto illegal_op;
3908
3133
sse_op2 = sse_op_table4[val][b1];
3909
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3910
tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3911
tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3912
break;
3913
case 0xf7:
3914
/* maskmov : we must prepare A0 */
3915
if (mod != 3)
3916
goto illegal_op;
3917
#ifdef TARGET_X86_64
3918
if (s->aflag == 2) {
3919
gen_op_movq_A0_reg(R_EDI);
3920
} else
3921
#endif
3922
{
3923
gen_op_movl_A0_reg(R_EDI);
3924
if (s->aflag == 0)
3925
gen_op_andl_A0_ffff();
3926
}
3927
gen_add_A0_ds_seg(s);
3928
3929
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3930
tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3931
tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, cpu_A0);
3134
sse_op2(op1_offset, op2_offset);
3932
3135
break;
3933
3136
default:
3934
tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3935
tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3936
tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3137
sse_op2(op1_offset, op2_offset);
3937
3138
break;
3938
3139
}
3939
3140
if (b == 0x2e || b == 0x2f) {
3942
3143
}
3943
3144
}
3944
3145
3146
3945
3147
/* convert one instruction. s->is_jmp is set if the translation must
3946
3148
be stopped. Return the next pc value */
3947
3149
static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
3952
3154
target_ulong next_eip, tval;
3953
3155
int rex_w, rex_r;
3954
3156
3955
if (unlikely(loglevel & CPU_LOG_TB_OP))
3956
tcg_gen_debug_insn_start(pc_start);
3957
3157
s->pc = pc_start;
3958
3158
prefixes = 0;
3959
3159
aflag = s->code32;
3964
3164
#ifdef TARGET_X86_64
3965
3165
s->rex_x = 0;
3966
3166
s->rex_b = 0;
3967
x86_64_hregs = 0;
3167
x86_64_hregs = 0;
3968
3168
#endif
3969
3169
s->rip_offset = 0; /* for relative ip address */
3970
3170
next_byte:
4025
3225
}
4026
3226
if (!(prefixes & PREFIX_ADR))
4027
3227
aflag = 2;
4028
} else
3228
} else
4029
3229
#endif
4030
3230
{
4031
3231
switch (b) {
4075
3275
4076
3276
/* lock generation */
4077
3277
if (prefixes & PREFIX_LOCK)
4078
tcg_gen_helper_0_0(helper_lock);
3278
gen_op_lock();
4079
3279
4080
3280
/* now check op code */
4081
3281
reswitch:
4085
3285
/* extended op code */
4086
3286
b = ldub_code(s->pc++) | 0x100;
4087
3287
goto reswitch;
4088
3288
4089
3289
/**************************/
4090
3290
/* arith & logic */
4091
3291
case 0x00 ... 0x05:
4105
3305
ot = OT_BYTE;
4106
3306
else
4107
3307
ot = dflag + OT_WORD;
4108
3308
4109
3309
switch(f) {
4110
3310
case 0: /* OP Ev, Gv */
4111
3311
modrm = ldub_code(s->pc++);
4120
3320
/* xor reg, reg optimisation */
4121
3321
gen_op_movl_T0_0();
4122
3322
s->cc_op = CC_OP_LOGICB + ot;
4123
gen_op_mov_reg_T0(ot, reg);
3323
gen_op_mov_reg_T0[ot][reg]();
4124
3324
gen_op_update1_cc();
4125
3325
break;
4126
3326
} else {
4127
3327
opreg = rm;
4128
3328
}
4129
gen_op_mov_TN_reg(ot, 1, reg);
3329
gen_op_mov_TN_reg[ot][1][reg]();
4130
3330
gen_op(s, op, ot, opreg);
4131
3331
break;
4132
3332
case 1: /* OP Gv, Ev */
4136
3336
rm = (modrm & 7) | REX_B(s);
4137
3337
if (mod != 3) {
4138
3338
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4139
gen_op_ld_T1_A0(ot + s->mem_index);
3339
gen_op_ld_T1_A0[ot + s->mem_index]();
4140
3340
} else if (op == OP_XORL && rm == reg) {
4141
3341
goto xor_zero;
4142
3342
} else {
4143
gen_op_mov_TN_reg(ot, 1, rm);
3343
gen_op_mov_TN_reg[ot][1][rm]();
4144
3344
}
4145
3345
gen_op(s, op, ot, reg);
4146
3346
break;
4153
3353
}
4154
3354
break;
4155
3355
4156
case 0x82:
4157
if (CODE64(s))
4158
goto illegal_op;
4159
3356
case 0x80: /* GRP1 */
4160
3357
case 0x81:
3358
case 0x82:
4161
3359
case 0x83:
4162
3360
{
4163
3361
int val;
4166
3364
ot = OT_BYTE;
4167
3365
else
4168
3366
ot = dflag + OT_WORD;
4169
3367
4170
3368
modrm = ldub_code(s->pc++);
4171
3369
mod = (modrm >> 6) & 3;
4172
3370
rm = (modrm & 7) | REX_B(s);
4173
3371
op = (modrm >> 3) & 7;
4174
3372
4175
3373
if (mod != 3) {
4176
3374
if (b == 0x83)
4177
3375
s->rip_offset = 1;
4224
3422
if (op == 0)
4225
3423
s->rip_offset = insn_const_size(ot);
4226
3424
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4227
gen_op_ld_T0_A0(ot + s->mem_index);
3425
gen_op_ld_T0_A0[ot + s->mem_index]();
4228
3426
} else {
4229
gen_op_mov_TN_reg(ot, 0, rm);
3427
gen_op_mov_TN_reg[ot][0][rm]();
4230
3428
}
4231
3429
4232
3430
switch(op) {
4237
3435
s->cc_op = CC_OP_LOGICB + ot;
4238
3436
break;
4239
3437
case 2: /* not */
4240
tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
3438
gen_op_notl_T0();
4241
3439
if (mod != 3) {
4242
gen_op_st_T0_A0(ot + s->mem_index);
3440
gen_op_st_T0_A0[ot + s->mem_index]();
4243
3441
} else {
4244
gen_op_mov_reg_T0(ot, rm);
3442
gen_op_mov_reg_T0[ot][rm]();
4245
3443
}
4246
3444
break;
4247
3445
case 3: /* neg */
4248
tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
3446
gen_op_negl_T0();
4249
3447
if (mod != 3) {
4250
gen_op_st_T0_A0(ot + s->mem_index);
3448
gen_op_st_T0_A0[ot + s->mem_index]();
4251
3449
} else {
4252
gen_op_mov_reg_T0(ot, rm);
3450
gen_op_mov_reg_T0[ot][rm]();
4253
3451
}
4254
3452
gen_op_update_neg_cc();
4255
3453
s->cc_op = CC_OP_SUBB + ot;
4257
3455
case 4: /* mul */
4258
3456
switch(ot) {
4259
3457
case OT_BYTE:
4260
gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4261
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4262
tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4263
/* XXX: use 32 bit mul which could be faster */
4264
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4265
gen_op_mov_reg_T0(OT_WORD, R_EAX);
4266
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4267
tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
3458
gen_op_mulb_AL_T0();
4268
3459
s->cc_op = CC_OP_MULB;
4269
3460
break;
4270
3461
case OT_WORD:
4271
gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4272
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4273
tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4274
/* XXX: use 32 bit mul which could be faster */
4275
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4276
gen_op_mov_reg_T0(OT_WORD, R_EAX);
4277
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4278
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4279
gen_op_mov_reg_T0(OT_WORD, R_EDX);
4280
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
3462
gen_op_mulw_AX_T0();
4281
3463
s->cc_op = CC_OP_MULW;
4282
3464
break;
4283
3465
default:
4284
3466
case OT_LONG:
4285
#ifdef TARGET_X86_64
4286
gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4287
tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4288
tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4289
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4290
gen_op_mov_reg_T0(OT_LONG, R_EAX);
4291
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4292
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4293
gen_op_mov_reg_T0(OT_LONG, R_EDX);
4294
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4295
#else
4296
{
4297
TCGv t0, t1;
4298
t0 = tcg_temp_new(TCG_TYPE_I64);
4299
t1 = tcg_temp_new(TCG_TYPE_I64);
4300
gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4301
tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4302
tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4303
tcg_gen_mul_i64(t0, t0, t1);
4304
tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4305
gen_op_mov_reg_T0(OT_LONG, R_EAX);
4306
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4307
tcg_gen_shri_i64(t0, t0, 32);
4308
tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4309
gen_op_mov_reg_T0(OT_LONG, R_EDX);
4310
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4311
}
4312
#endif
3467
gen_op_mull_EAX_T0();
4313
3468
s->cc_op = CC_OP_MULL;
4314
3469
break;
4315
3470
#ifdef TARGET_X86_64
4316
3471
case OT_QUAD:
4317
tcg_gen_helper_0_1(helper_mulq_EAX_T0, cpu_T[0]);
3472
gen_op_mulq_EAX_T0();
4318
3473
s->cc_op = CC_OP_MULQ;
4319
3474
break;
4320
3475
#endif
4323
3478
case 5: /* imul */
4324
3479
switch(ot) {
4325
3480
case OT_BYTE:
4326
gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4327
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4328
tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4329
/* XXX: use 32 bit mul which could be faster */
4330
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4331
gen_op_mov_reg_T0(OT_WORD, R_EAX);
4332
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4333
tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4334
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
3481
gen_op_imulb_AL_T0();
4335
3482
s->cc_op = CC_OP_MULB;
4336
3483
break;
4337
3484
case OT_WORD:
4338
gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4339
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4340
tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4341
/* XXX: use 32 bit mul which could be faster */
4342
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4343
gen_op_mov_reg_T0(OT_WORD, R_EAX);
4344
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4345
tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4346
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4347
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4348
gen_op_mov_reg_T0(OT_WORD, R_EDX);
3485
gen_op_imulw_AX_T0();
4349
3486
s->cc_op = CC_OP_MULW;
4350
3487
break;
4351
3488
default:
4352
3489
case OT_LONG:
4353
#ifdef TARGET_X86_64
4354
gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4355
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4356
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4357
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4358
gen_op_mov_reg_T0(OT_LONG, R_EAX);
4359
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4360
tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4361
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4362
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4363
gen_op_mov_reg_T0(OT_LONG, R_EDX);
4364
#else
4365
{
4366
TCGv t0, t1;
4367
t0 = tcg_temp_new(TCG_TYPE_I64);
4368
t1 = tcg_temp_new(TCG_TYPE_I64);
4369
gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4370
tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4371
tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4372
tcg_gen_mul_i64(t0, t0, t1);
4373
tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4374
gen_op_mov_reg_T0(OT_LONG, R_EAX);
4375
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4376
tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4377
tcg_gen_shri_i64(t0, t0, 32);
4378
tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4379
gen_op_mov_reg_T0(OT_LONG, R_EDX);
4380
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4381
}
4382
#endif
3490
gen_op_imull_EAX_T0();
4383
3491
s->cc_op = CC_OP_MULL;
4384
3492
break;
4385
3493
#ifdef TARGET_X86_64
4386
3494
case OT_QUAD:
4387
tcg_gen_helper_0_1(helper_imulq_EAX_T0, cpu_T[0]);
3495
gen_op_imulq_EAX_T0();
4388
3496
s->cc_op = CC_OP_MULQ;
4389
3497
break;
4390
3498
#endif
4394
3502
switch(ot) {
4395
3503
case OT_BYTE:
4396
3504
gen_jmp_im(pc_start - s->cs_base);
4397
tcg_gen_helper_0_1(helper_divb_AL, cpu_T[0]);
3505
gen_op_divb_AL_T0();
4398
3506
break;
4399
3507
case OT_WORD:
4400
3508
gen_jmp_im(pc_start - s->cs_base);
4401
tcg_gen_helper_0_1(helper_divw_AX, cpu_T[0]);
3509
gen_op_divw_AX_T0();
4402
3510
break;
4403
3511
default:
4404
3512
case OT_LONG:
4405
3513
gen_jmp_im(pc_start - s->cs_base);
4406
tcg_gen_helper_0_1(helper_divl_EAX, cpu_T[0]);
3514
gen_op_divl_EAX_T0();
4407
3515
break;
4408
3516
#ifdef TARGET_X86_64
4409
3517
case OT_QUAD:
4410
3518
gen_jmp_im(pc_start - s->cs_base);
4411
tcg_gen_helper_0_1(helper_divq_EAX, cpu_T[0]);
3519
gen_op_divq_EAX_T0();
4412
3520
break;
4413
3521
#endif
4414
3522
}
4417
3525
switch(ot) {
4418
3526
case OT_BYTE:
4419
3527
gen_jmp_im(pc_start - s->cs_base);
4420
tcg_gen_helper_0_1(helper_idivb_AL, cpu_T[0]);
3528
gen_op_idivb_AL_T0();
4421
3529
break;
4422
3530
case OT_WORD:
4423
3531
gen_jmp_im(pc_start - s->cs_base);
4424
tcg_gen_helper_0_1(helper_idivw_AX, cpu_T[0]);
3532
gen_op_idivw_AX_T0();
4425
3533
break;
4426
3534
default:
4427
3535
case OT_LONG:
4428
3536
gen_jmp_im(pc_start - s->cs_base);
4429
tcg_gen_helper_0_1(helper_idivl_EAX, cpu_T[0]);
3537
gen_op_idivl_EAX_T0();
4430
3538
break;
4431
3539
#ifdef TARGET_X86_64
4432
3540
case OT_QUAD:
4433
3541
gen_jmp_im(pc_start - s->cs_base);
4434
tcg_gen_helper_0_1(helper_idivq_EAX, cpu_T[0]);
3542
gen_op_idivq_EAX_T0();
4435
3543
break;
4436
3544
#endif
4437
3545
}
4471
3579
if (mod != 3) {
4472
3580
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4473
3581
if (op >= 2 && op != 3 && op != 5)
4474
gen_op_ld_T0_A0(ot + s->mem_index);
3582
gen_op_ld_T0_A0[ot + s->mem_index]();
4475
3583
} else {
4476
gen_op_mov_TN_reg(ot, 0, rm);
3584
gen_op_mov_TN_reg[ot][0][rm]();
4477
3585
}
4478
3586
4479
3587
switch(op) {
4502
3610
gen_eob(s);
4503
3611
break;
4504
3612
case 3: /* lcall Ev */
4505
gen_op_ld_T1_A0(ot + s->mem_index);
3613
gen_op_ld_T1_A0[ot + s->mem_index]();
4506
3614
gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4507
gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
3615
gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
4508
3616
do_lcall:
4509
3617
if (s->pe && !s->vm86) {
4510
3618
if (s->cc_op != CC_OP_DYNAMIC)
4511
3619
gen_op_set_cc_op(s->cc_op);
4512
3620
gen_jmp_im(pc_start - s->cs_base);
4513
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4514
tcg_gen_helper_0_4(helper_lcall_protected,
4515
cpu_tmp2_i32, cpu_T[1],
4516
tcg_const_i32(dflag),
4517
tcg_const_i32(s->pc - pc_start));
3621
gen_op_lcall_protected_T0_T1(dflag, s->pc - pc_start);
4518
3622
} else {
4519
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4520
tcg_gen_helper_0_4(helper_lcall_real,
4521
cpu_tmp2_i32, cpu_T[1],
4522
tcg_const_i32(dflag),
4523
tcg_const_i32(s->pc - s->cs_base));
3623
gen_op_lcall_real_T0_T1(dflag, s->pc - s->cs_base);
4524
3624
}
4525
3625
gen_eob(s);
4526
3626
break;
4531
3631
gen_eob(s);
4532
3632
break;
4533
3633
case 5: /* ljmp Ev */
4534
gen_op_ld_T1_A0(ot + s->mem_index);
3634
gen_op_ld_T1_A0[ot + s->mem_index]();
4535
3635
gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4536
gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
3636
gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
4537
3637
do_ljmp:
4538
3638
if (s->pe && !s->vm86) {
4539
3639
if (s->cc_op != CC_OP_DYNAMIC)
4540
3640
gen_op_set_cc_op(s->cc_op);
4541
3641
gen_jmp_im(pc_start - s->cs_base);
4542
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4543
tcg_gen_helper_0_3(helper_ljmp_protected,
4544
cpu_tmp2_i32,
4545
cpu_T[1],
4546
tcg_const_i32(s->pc - pc_start));
3642
gen_op_ljmp_protected_T0_T1(s->pc - pc_start);
4547
3643
} else {
4548
gen_op_movl_seg_T0_vm(R_CS);
3644
gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
4549
3645
gen_op_movl_T0_T1();
4550
3646
gen_op_jmp_T0();
4551
3647
}
4560
3656
break;
4561
3657
4562
3658
case 0x84: /* test Ev, Gv */
4563
case 0x85:
3659
case 0x85:
4564
3660
if ((b & 1) == 0)
4565
3661
ot = OT_BYTE;
4566
3662
else
4570
3666
mod = (modrm >> 6) & 3;
4571
3667
rm = (modrm & 7) | REX_B(s);
4572
3668
reg = ((modrm >> 3) & 7) | rex_r;
4573
3669
4574
3670
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4575
gen_op_mov_TN_reg(ot, 1, reg);
3671
gen_op_mov_TN_reg[ot][1][reg]();
4576
3672
gen_op_testl_T0_T1_cc();
4577
3673
s->cc_op = CC_OP_LOGICB + ot;
4578
3674
break;
4579
3675
4580
3676
case 0xa8: /* test eAX, Iv */
4581
3677
case 0xa9:
4582
3678
if ((b & 1) == 0)
4585
3681
ot = dflag + OT_WORD;
4586
3682
val = insn_get(s, ot);
4587
3683
4588
gen_op_mov_TN_reg(ot, 0, OR_EAX);
3684
gen_op_mov_TN_reg[ot][0][OR_EAX]();
4589
3685
gen_op_movl_T1_im(val);
4590
3686
gen_op_testl_T0_T1_cc();
4591
3687
s->cc_op = CC_OP_LOGICB + ot;
4592
3688
break;
4593
3689
4594
3690
case 0x98: /* CWDE/CBW */
4595
3691
#ifdef TARGET_X86_64
4596
3692
if (dflag == 2) {
4597
gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4598
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4599
gen_op_mov_reg_T0(OT_QUAD, R_EAX);
3693
gen_op_movslq_RAX_EAX();
4600
3694
} else
4601
3695
#endif
4602
if (dflag == 1) {
4603
gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4604
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4605
gen_op_mov_reg_T0(OT_LONG, R_EAX);
4606
} else {
4607
gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4608
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4609
gen_op_mov_reg_T0(OT_WORD, R_EAX);
4610
}
3696
if (dflag == 1)
3697
gen_op_movswl_EAX_AX();
3698
else
3699
gen_op_movsbw_AX_AL();
4611
3700
break;
4612
3701
case 0x99: /* CDQ/CWD */
4613
3702
#ifdef TARGET_X86_64
4614
3703
if (dflag == 2) {
4615
gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4616
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4617
gen_op_mov_reg_T0(OT_QUAD, R_EDX);
3704
gen_op_movsqo_RDX_RAX();
4618
3705
} else
4619
3706
#endif
4620
if (dflag == 1) {
4621
gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4622
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4623
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4624
gen_op_mov_reg_T0(OT_LONG, R_EDX);
4625
} else {
4626
gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4627
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4628
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4629
gen_op_mov_reg_T0(OT_WORD, R_EDX);
4630
}
3707
if (dflag == 1)
3708
gen_op_movslq_EDX_EAX();
3709
else
3710
gen_op_movswl_DX_AX();
4631
3711
break;
4632
3712
case 0x1af: /* imul Gv, Ev */
4633
3713
case 0x69: /* imul Gv, Ev, I */
4647
3727
val = (int8_t)insn_get(s, OT_BYTE);
4648
3728
gen_op_movl_T1_im(val);
4649
3729
} else {
4650
gen_op_mov_TN_reg(ot, 1, reg);
3730
gen_op_mov_TN_reg[ot][1][reg]();
4651
3731
}
4652
3732
4653
3733
#ifdef TARGET_X86_64
4654
3734
if (ot == OT_QUAD) {
4655
tcg_gen_helper_1_2(helper_imulq_T0_T1, cpu_T[0], cpu_T[0], cpu_T[1]);
3735
gen_op_imulq_T0_T1();
4656
3736
} else
4657
3737
#endif
4658
3738
if (ot == OT_LONG) {
4659
#ifdef TARGET_X86_64
4660
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4661
tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4662
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4663
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4664
tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4665
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4666
#else
4667
{
4668
TCGv t0, t1;
4669
t0 = tcg_temp_new(TCG_TYPE_I64);
4670
t1 = tcg_temp_new(TCG_TYPE_I64);
4671
tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4672
tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4673
tcg_gen_mul_i64(t0, t0, t1);
4674
tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4675
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4676
tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4677
tcg_gen_shri_i64(t0, t0, 32);
4678
tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4679
tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4680
}
4681
#endif
3739
gen_op_imull_T0_T1();
4682
3740
} else {
4683
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4684
tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4685
/* XXX: use 32 bit mul which could be faster */
4686
tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4687
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4688
tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4689
tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
3741
gen_op_imulw_T0_T1();
4690
3742
}
4691
gen_op_mov_reg_T0(ot, reg);
3743
gen_op_mov_reg_T0[ot][reg]();
4692
3744
s->cc_op = CC_OP_MULB + ot;
4693
3745
break;
4694
3746
case 0x1c0:
4702
3754
mod = (modrm >> 6) & 3;
4703
3755
if (mod == 3) {
4704
3756
rm = (modrm & 7) | REX_B(s);
4705
gen_op_mov_TN_reg(ot, 0, reg);
4706
gen_op_mov_TN_reg(ot, 1, rm);
3757
gen_op_mov_TN_reg[ot][0][reg]();
3758
gen_op_mov_TN_reg[ot][1][rm]();
4707
3759
gen_op_addl_T0_T1();
4708
gen_op_mov_reg_T1(ot, reg);
4709
gen_op_mov_reg_T0(ot, rm);
3760
gen_op_mov_reg_T1[ot][reg]();
3761
gen_op_mov_reg_T0[ot][rm]();
4710
3762
} else {
4711
3763
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4712
gen_op_mov_TN_reg(ot, 0, reg);
4713
gen_op_ld_T1_A0(ot + s->mem_index);
3764
gen_op_mov_TN_reg[ot][0][reg]();
3765
gen_op_ld_T1_A0[ot + s->mem_index]();
4714
3766
gen_op_addl_T0_T1();
4715
gen_op_st_T0_A0(ot + s->mem_index);
4716
gen_op_mov_reg_T1(ot, reg);
3767
gen_op_st_T0_A0[ot + s->mem_index]();
3768
gen_op_mov_reg_T1[ot][reg]();
4717
3769
}
4718
3770
gen_op_update2_cc();
4719
3771
s->cc_op = CC_OP_ADDB + ot;
4720
3772
break;
4721
3773
case 0x1b0:
4722
3774
case 0x1b1: /* cmpxchg Ev, Gv */
4723
{
4724
int label1, label2;
4725
TCGv t0, t1, t2, a0;
4726
4727
if ((b & 1) == 0)
4728
ot = OT_BYTE;
4729
else
4730
ot = dflag + OT_WORD;
4731
modrm = ldub_code(s->pc++);
4732
reg = ((modrm >> 3) & 7) | rex_r;
4733
mod = (modrm >> 6) & 3;
4734
t0 = tcg_temp_local_new(TCG_TYPE_TL);
4735
t1 = tcg_temp_local_new(TCG_TYPE_TL);
4736
t2 = tcg_temp_local_new(TCG_TYPE_TL);
4737
a0 = tcg_temp_local_new(TCG_TYPE_TL);
4738
gen_op_mov_v_reg(ot, t1, reg);
4739
if (mod == 3) {
4740
rm = (modrm & 7) | REX_B(s);
4741
gen_op_mov_v_reg(ot, t0, rm);
4742
} else {
4743
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4744
tcg_gen_mov_tl(a0, cpu_A0);
4745
gen_op_ld_v(ot + s->mem_index, t0, a0);
4746
rm = 0; /* avoid warning */
4747
}
4748
label1 = gen_new_label();
4749
tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUState, regs[R_EAX]));
4750
tcg_gen_sub_tl(t2, t2, t0);
4751
gen_extu(ot, t2);
4752
tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
4753
if (mod == 3) {
4754
label2 = gen_new_label();
4755
gen_op_mov_reg_v(ot, R_EAX, t0);
4756
tcg_gen_br(label2);
4757
gen_set_label(label1);
4758
gen_op_mov_reg_v(ot, rm, t1);
4759
gen_set_label(label2);
4760
} else {
4761
tcg_gen_mov_tl(t1, t0);
4762
gen_op_mov_reg_v(ot, R_EAX, t0);
4763
gen_set_label(label1);
4764
/* always store */
4765
gen_op_st_v(ot + s->mem_index, t1, a0);
4766
}
4767
tcg_gen_mov_tl(cpu_cc_src, t0);
4768
tcg_gen_mov_tl(cpu_cc_dst, t2);
4769
s->cc_op = CC_OP_SUBB + ot;
4770
tcg_temp_free(t0);
4771
tcg_temp_free(t1);
4772
tcg_temp_free(t2);
4773
tcg_temp_free(a0);
3775
if ((b & 1) == 0)
3776
ot = OT_BYTE;
3777
else
3778
ot = dflag + OT_WORD;
3779
modrm = ldub_code(s->pc++);
3780
reg = ((modrm >> 3) & 7) | rex_r;
3781
mod = (modrm >> 6) & 3;
3782
gen_op_mov_TN_reg[ot][1][reg]();
3783
if (mod == 3) {
3784
rm = (modrm & 7) | REX_B(s);
3785
gen_op_mov_TN_reg[ot][0][rm]();
3786
gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
3787
gen_op_mov_reg_T0[ot][rm]();
3788
} else {
3789
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3790
gen_op_ld_T0_A0[ot + s->mem_index]();
3791
gen_op_cmpxchg_mem_T0_T1_EAX_cc[ot + s->mem_index]();
4774
3792
}
3793
s->cc_op = CC_OP_SUBB + ot;
4775
3794
break;
4776
3795
case 0x1c7: /* cmpxchg8b */
4777
3796
modrm = ldub_code(s->pc++);
4778
3797
mod = (modrm >> 6) & 3;
4779
if ((mod == 3) || ((modrm & 0x38) != 0x8))
3798
if (mod == 3)
4780
3799
goto illegal_op;
4781
#ifdef TARGET_X86_64
4782
if (dflag == 2) {
4783
if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
4784
goto illegal_op;
4785
gen_jmp_im(pc_start - s->cs_base);
4786
if (s->cc_op != CC_OP_DYNAMIC)
4787
gen_op_set_cc_op(s->cc_op);
4788
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4789
tcg_gen_helper_0_1(helper_cmpxchg16b, cpu_A0);
4790
} else
4791
#endif
4792
{
4793
if (!(s->cpuid_features & CPUID_CX8))
4794
goto illegal_op;
4795
gen_jmp_im(pc_start - s->cs_base);
4796
if (s->cc_op != CC_OP_DYNAMIC)
4797
gen_op_set_cc_op(s->cc_op);
4798
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4799
tcg_gen_helper_0_1(helper_cmpxchg8b, cpu_A0);
4800
}
3800
if (s->cc_op != CC_OP_DYNAMIC)
3801
gen_op_set_cc_op(s->cc_op);
3802
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3803
gen_op_cmpxchg8b();
4801
3804
s->cc_op = CC_OP_EFLAGS;
4802
3805
break;
4803
3806
4804
3807
/**************************/
4805
3808
/* push/pop */
4806
3809
case 0x50 ... 0x57: /* push */
4807
gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
3810
gen_op_mov_TN_reg[OT_LONG][0][(b & 7) | REX_B(s)]();
4808
3811
gen_push_T0(s);
4809
3812
break;
4810
3813
case 0x58 ... 0x5f: /* pop */
4816
3819
gen_pop_T0(s);
4817
3820
/* NOTE: order is important for pop %sp */
4818
3821
gen_pop_update(s);
4819
gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
3822
gen_op_mov_reg_T0[ot][(b & 7) | REX_B(s)]();
4820
3823
break;
4821
3824
case 0x60: /* pusha */
4822
3825
if (CODE64(s))
4855
3858
/* NOTE: order is important for pop %sp */
4856
3859
gen_pop_update(s);
4857
3860
rm = (modrm & 7) | REX_B(s);
4858
gen_op_mov_reg_T0(ot, rm);
3861
gen_op_mov_reg_T0[ot][rm]();
4859
3862
} else {
4860
3863
/* NOTE: order is important too for MMU exceptions */
4861
3864
s->popl_esp_hack = 1 << ot;
4876
3879
case 0xc9: /* leave */
4877
3880
/* XXX: exception not precise (ESP is updated before potential exception) */
4878
3881
if (CODE64(s)) {
4879
gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
4880
gen_op_mov_reg_T0(OT_QUAD, R_ESP);
3882
gen_op_mov_TN_reg[OT_QUAD][0][R_EBP]();
3883
gen_op_mov_reg_T0[OT_QUAD][R_ESP]();
4881
3884
} else if (s->ss32) {
4882
gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
4883
gen_op_mov_reg_T0(OT_LONG, R_ESP);
3885
gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
3886
gen_op_mov_reg_T0[OT_LONG][R_ESP]();
4884
3887
} else {
4885
gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
4886
gen_op_mov_reg_T0(OT_WORD, R_ESP);
3888
gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
3889
gen_op_mov_reg_T0[OT_WORD][R_ESP]();
4887
3890
}
4888
3891
gen_pop_T0(s);
4889
3892
if (CODE64(s)) {
4891
3894
} else {
4892
3895
ot = dflag + OT_WORD;
4893
3896
}
4894
gen_op_mov_reg_T0(ot, R_EBP);
3897
gen_op_mov_reg_T0[ot][R_EBP]();
4895
3898
gen_pop_update(s);
4896
3899
break;
4897
3900
case 0x06: /* push es */
4922
3925
/* If several instructions disable interrupts, only the
4923
3926
_first_ does it */
4924
3927
if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
4925
tcg_gen_helper_0_0(helper_set_inhibit_irq);
3928
gen_op_set_inhibit_irq();
4926
3929
s->tf = 0;
4927
3930
}
4928
3931
if (s->is_jmp) {
4951
3954
ot = dflag + OT_WORD;
4952
3955
modrm = ldub_code(s->pc++);
4953
3956
reg = ((modrm >> 3) & 7) | rex_r;
4954
3957
4955
3958
/* generate a generic store */
4956
3959
gen_ldst_modrm(s, modrm, ot, reg, 1);
4957
3960
break;
4970
3973
val = insn_get(s, ot);
4971
3974
gen_op_movl_T0_im(val);
4972
3975
if (mod != 3)
4973
gen_op_st_T0_A0(ot + s->mem_index);
3976
gen_op_st_T0_A0[ot + s->mem_index]();
4974
3977
else
4975
gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
3978
gen_op_mov_reg_T0[ot][(modrm & 7) | REX_B(s)]();
4976
3979
break;
4977
3980
case 0x8a:
4978
3981
case 0x8b: /* mov Ev, Gv */
4982
3985
ot = OT_WORD + dflag;
4983
3986
modrm = ldub_code(s->pc++);
4984
3987
reg = ((modrm >> 3) & 7) | rex_r;
4985
3988
4986
3989
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4987
gen_op_mov_reg_T0(ot, reg);
3990
gen_op_mov_reg_T0[ot][reg]();
4988
3991
break;
4989
3992
case 0x8e: /* mov seg, Gv */
4990
3993
modrm = ldub_code(s->pc++);
4998
4001
/* If several instructions disable interrupts, only the
4999
4002
_first_ does it */
5000
4003
if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5001
tcg_gen_helper_0_0(helper_set_inhibit_irq);
4004
gen_op_set_inhibit_irq();
5002
4005
s->tf = 0;
5003
4006
}
5004
4007
if (s->is_jmp) {
5034
4037
reg = ((modrm >> 3) & 7) | rex_r;
5035
4038
mod = (modrm >> 6) & 3;
5036
4039
rm = (modrm & 7) | REX_B(s);
5037
4040
5038
4041
if (mod == 3) {
5039
gen_op_mov_TN_reg(ot, 0, rm);
4042
gen_op_mov_TN_reg[ot][0][rm]();
5040
4043
switch(ot | (b & 8)) {
5041
4044
case OT_BYTE:
5042
tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4045
gen_op_movzbl_T0_T0();
5043
4046
break;
5044
4047
case OT_BYTE | 8:
5045
tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4048
gen_op_movsbl_T0_T0();
5046
4049
break;
5047
4050
case OT_WORD:
5048
tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4051
gen_op_movzwl_T0_T0();
5049
4052
break;
5050
4053
default:
5051
4054
case OT_WORD | 8:
5052
tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4055
gen_op_movswl_T0_T0();
5053
4056
break;
5054
4057
}
5055
gen_op_mov_reg_T0(d_ot, reg);
4058
gen_op_mov_reg_T0[d_ot][reg]();
5056
4059
} else {
5057
4060
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5058
4061
if (b & 8) {
5059
gen_op_lds_T0_A0(ot + s->mem_index);
4062
gen_op_lds_T0_A0[ot + s->mem_index]();
5060
4063
} else {
5061
gen_op_ldu_T0_A0(ot + s->mem_index);
4064
gen_op_ldu_T0_A0[ot + s->mem_index]();
5062
4065
}
5063
gen_op_mov_reg_T0(d_ot, reg);
4066
gen_op_mov_reg_T0[d_ot][reg]();
5064
4067
}
5065
4068
}
5066
4069
break;
5078
4081
s->addseg = 0;
5079
4082
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5080
4083
s->addseg = val;
5081
gen_op_mov_reg_A0(ot - OT_WORD, reg);
4084
gen_op_mov_reg_A0[ot - OT_WORD][reg]();
5082
4085
break;
5083
4086
5084
4087
case 0xa0: /* mov EAX, Ov */
5085
4088
case 0xa1:
5086
4089
case 0xa2: /* mov Ov, EAX */
5096
4099
if (s->aflag == 2) {
5097
4100
offset_addr = ldq_code(s->pc);
5098
4101
s->pc += 8;
5099
gen_op_movq_A0_im(offset_addr);
5100
} else
4102
if (offset_addr == (int32_t)offset_addr)
4103
gen_op_movq_A0_im(offset_addr);
4104
else
4105
gen_op_movq_A0_im64(offset_addr >> 32, offset_addr);
4106
} else
5101
4107
#endif
5102
4108
{
5103
4109
if (s->aflag) {
5109
4115
}
5110
4116
gen_add_A0_ds_seg(s);
5111
4117
if ((b & 2) == 0) {
5112
gen_op_ld_T0_A0(ot + s->mem_index);
5113
gen_op_mov_reg_T0(ot, R_EAX);
4118
gen_op_ld_T0_A0[ot + s->mem_index]();
4119
gen_op_mov_reg_T0[ot][R_EAX]();
5114
4120
} else {
5115
gen_op_mov_TN_reg(ot, 0, R_EAX);
5116
gen_op_st_T0_A0(ot + s->mem_index);
4121
gen_op_mov_TN_reg[ot][0][R_EAX]();
4122
gen_op_st_T0_A0[ot + s->mem_index]();
5117
4123
}
5118
4124
}
5119
4125
break;
5120
4126
case 0xd7: /* xlat */
5121
4127
#ifdef TARGET_X86_64
5122
4128
if (s->aflag == 2) {
5123
gen_op_movq_A0_reg(R_EBX);
5124
gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
5125
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5126
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5127
} else
4129
gen_op_movq_A0_reg[R_EBX]();
4130
gen_op_addq_A0_AL();
4131
} else
5128
4132
#endif
5129
4133
{
5130
gen_op_movl_A0_reg(R_EBX);
5131
gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
5132
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5133
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
4134
gen_op_movl_A0_reg[R_EBX]();
4135
gen_op_addl_A0_AL();
5134
4136
if (s->aflag == 0)
5135
4137
gen_op_andl_A0_ffff();
5136
else
5137
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
5138
4138
}
5139
4139
gen_add_A0_ds_seg(s);
5140
gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
5141
gen_op_mov_reg_T0(OT_BYTE, R_EAX);
4140
gen_op_ldu_T0_A0[OT_BYTE + s->mem_index]();
4141
gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
5142
4142
break;
5143
4143
case 0xb0 ... 0xb7: /* mov R, Ib */
5144
4144
val = insn_get(s, OT_BYTE);
5145
4145
gen_op_movl_T0_im(val);
5146
gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
4146
gen_op_mov_reg_T0[OT_BYTE][(b & 7) | REX_B(s)]();
5147
4147
break;
5148
4148
case 0xb8 ... 0xbf: /* mov R, Iv */
5149
4149
#ifdef TARGET_X86_64
5154
4154
s->pc += 8;
5155
4155
reg = (b & 7) | REX_B(s);
5156
4156
gen_movtl_T0_im(tmp);
5157
gen_op_mov_reg_T0(OT_QUAD, reg);
5158
} else
4157
gen_op_mov_reg_T0[OT_QUAD][reg]();
4158
} else
5159
4159
#endif
5160
4160
{
5161
4161
ot = dflag ? OT_LONG : OT_WORD;
5162
4162
val = insn_get(s, ot);
5163
4163
reg = (b & 7) | REX_B(s);
5164
4164
gen_op_movl_T0_im(val);
5165
gen_op_mov_reg_T0(ot, reg);
4165
gen_op_mov_reg_T0[ot][reg]();
5166
4166
}
5167
4167
break;
5168
4168
5183
4183
if (mod == 3) {
5184
4184
rm = (modrm & 7) | REX_B(s);
5185
4185
do_xchg_reg:
5186
gen_op_mov_TN_reg(ot, 0, reg);
5187
gen_op_mov_TN_reg(ot, 1, rm);
5188
gen_op_mov_reg_T0(ot, rm);
5189
gen_op_mov_reg_T1(ot, reg);
4186
gen_op_mov_TN_reg[ot][0][reg]();
4187
gen_op_mov_TN_reg[ot][1][rm]();
4188
gen_op_mov_reg_T0[ot][rm]();
4189
gen_op_mov_reg_T1[ot][reg]();
5190
4190
} else {
5191
4191
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5192
gen_op_mov_TN_reg(ot, 0, reg);
4192
gen_op_mov_TN_reg[ot][0][reg]();
5193
4193
/* for xchg, lock is implicit */
5194
4194
if (!(prefixes & PREFIX_LOCK))
5195
tcg_gen_helper_0_0(helper_lock);
5196
gen_op_ld_T1_A0(ot + s->mem_index);
5197
gen_op_st_T0_A0(ot + s->mem_index);
4195
gen_op_lock();
4196
gen_op_ld_T1_A0[ot + s->mem_index]();
4197
gen_op_st_T0_A0[ot + s->mem_index]();
5198
4198
if (!(prefixes & PREFIX_LOCK))
5199
tcg_gen_helper_0_0(helper_unlock);
5200
gen_op_mov_reg_T1(ot, reg);
4199
gen_op_unlock();
4200
gen_op_mov_reg_T1[ot][reg]();
5201
4201
}
5202
4202
break;
5203
4203
case 0xc4: /* les Gv */
5226
4226
if (mod == 3)
5227
4227
goto illegal_op;
5228
4228
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5229
gen_op_ld_T1_A0(ot + s->mem_index);
4229
gen_op_ld_T1_A0[ot + s->mem_index]();
5230
4230
gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
5231
4231
/* load the segment first to handle exceptions properly */
5232
gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4232
gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
5233
4233
gen_movl_seg_T0(s, op, pc_start - s->cs_base);
5234
4234
/* then put the data */
5235
gen_op_mov_reg_T1(ot, reg);
4235
gen_op_mov_reg_T1[ot][reg]();
5236
4236
if (s->is_jmp) {
5237
4237
gen_jmp_im(s->pc - s->cs_base);
5238
4238
gen_eob(s);
5239
4239
}
5240
4240
break;
5241
4241
5242
4242
/************************/
5243
4243
/* shifts */
5244
4244
case 0xc0:
5251
4251
ot = OT_BYTE;
5252
4252
else
5253
4253
ot = dflag + OT_WORD;
5254
4254
5255
4255
modrm = ldub_code(s->pc++);
5256
4256
mod = (modrm >> 6) & 3;
5257
4257
op = (modrm >> 3) & 7;
5258
4258
5259
4259
if (mod != 3) {
5260
4260
if (shift == 2) {
5261
4261
s->rip_offset = 1;
5309
4309
mod = (modrm >> 6) & 3;
5310
4310
rm = (modrm & 7) | REX_B(s);
5311
4311
reg = ((modrm >> 3) & 7) | rex_r;
4312
5312
4313
if (mod != 3) {
5313
4314
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5314
opreg = OR_TMP0;
4315
gen_op_ld_T0_A0[ot + s->mem_index]();
5315
4316
} else {
5316
opreg = rm;
4317
gen_op_mov_TN_reg[ot][0][rm]();
5317
4318
}
5318
gen_op_mov_TN_reg(ot, 1, reg);
5319
4319
gen_op_mov_TN_reg[ot][1][reg]();
4320
5320
4321
if (shift) {
5321
4322
val = ldub_code(s->pc++);
5322
tcg_gen_movi_tl(cpu_T3, val);
4323
if (ot == OT_QUAD)
4324
val &= 0x3f;
4325
else
4326
val &= 0x1f;
4327
if (val) {
4328
if (mod == 3)
4329
gen_op_shiftd_T0_T1_im_cc[ot][op](val);
4330
else
4331
gen_op_shiftd_mem_T0_T1_im_cc[ot + s->mem_index][op](val);
4332
if (op == 0 && ot != OT_WORD)
4333
s->cc_op = CC_OP_SHLB + ot;
4334
else
4335
s->cc_op = CC_OP_SARB + ot;
4336
}
5323
4337
} else {
5324
tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_ECX]));
5325
}
5326
gen_shiftd_rm_T1_T3(s, ot, opreg, op);
4338
if (s->cc_op != CC_OP_DYNAMIC)
4339
gen_op_set_cc_op(s->cc_op);
4340
if (mod == 3)
4341
gen_op_shiftd_T0_T1_ECX_cc[ot][op]();
4342
else
4343
gen_op_shiftd_mem_T0_T1_ECX_cc[ot + s->mem_index][op]();
4344
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
4345
}
4346
if (mod == 3) {
4347
gen_op_mov_reg_T0[ot][rm]();
4348
}
5327
4349
break;
5328
4350
5329
4351
/************************/
5330
4352
/* floats */
5331
case 0xd8 ... 0xdf:
4353
case 0xd8 ... 0xdf:
5332
4354
if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5333
4355
/* if CR0.EM or CR0.TS are set, generate an FPU exception */
5334
4356
/* XXX: what to do if illegal op ? */
5353
4375
5354
4376
switch(op >> 4) {
5355
4377
case 0:
5356
gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5357
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5358
tcg_gen_helper_0_1(helper_flds_FT0, cpu_tmp2_i32);
4378
gen_op_flds_FT0_A0();
5359
4379
break;
5360
4380
case 1:
5361
gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5362
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5363
tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32);
4381
gen_op_fildl_FT0_A0();
5364
4382
break;
5365
4383
case 2:
5366
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5367
(s->mem_index >> 2) - 1);
5368
tcg_gen_helper_0_1(helper_fldl_FT0, cpu_tmp1_i64);
4384
gen_op_fldl_FT0_A0();
5369
4385
break;
5370
4386
case 3:
5371
4387
default:
5372
gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5373
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5374
tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32);
4388
gen_op_fild_FT0_A0();
5375
4389
break;
5376
4390
}
5377
5378
tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]);
4391
4392
gen_op_fp_arith_ST0_FT0[op1]();
5379
4393
if (op1 == 3) {
5380
4394
/* fcomp needs pop */
5381
tcg_gen_helper_0_0(helper_fpop);
4395
gen_op_fpop();
5382
4396
}
5383
4397
}
5384
4398
break;
5392
4406
case 0:
5393
4407
switch(op >> 4) {
5394
4408
case 0:
5395
gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5396
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5397
tcg_gen_helper_0_1(helper_flds_ST0, cpu_tmp2_i32);
4409
gen_op_flds_ST0_A0();
5398
4410
break;
5399
4411
case 1:
5400
gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5401
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5402
tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32);
4412
gen_op_fildl_ST0_A0();
5403
4413
break;
5404
4414
case 2:
5405
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5406
(s->mem_index >> 2) - 1);
5407
tcg_gen_helper_0_1(helper_fldl_ST0, cpu_tmp1_i64);
4415
gen_op_fldl_ST0_A0();
5408
4416
break;
5409
4417
case 3:
5410
4418
default:
5411
gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5412
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5413
tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32);
4419
gen_op_fild_ST0_A0();
5414
4420
break;
5415
4421
}
5416
4422
break;
5417
4423
case 1:
5418
/* XXX: the corresponding CPUID bit must be tested ! */
5419
4424
switch(op >> 4) {
5420
4425
case 1:
5421
tcg_gen_helper_1_0(helper_fisttl_ST0, cpu_tmp2_i32);
5422
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5423
gen_op_st_T0_A0(OT_LONG + s->mem_index);
4426
gen_op_fisttl_ST0_A0();
5424
4427
break;
5425
4428
case 2:
5426
tcg_gen_helper_1_0(helper_fisttll_ST0, cpu_tmp1_i64);
5427
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5428
(s->mem_index >> 2) - 1);
4429
gen_op_fisttll_ST0_A0();
5429
4430
break;
5430
4431
case 3:
5431
4432
default:
5432
tcg_gen_helper_1_0(helper_fistt_ST0, cpu_tmp2_i32);
5433
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5434
gen_op_st_T0_A0(OT_WORD + s->mem_index);
5435
break;
4433
gen_op_fistt_ST0_A0();
5436
4434
}
5437
tcg_gen_helper_0_0(helper_fpop);
4435
gen_op_fpop();
5438
4436
break;
5439
4437
default:
5440
4438
switch(op >> 4) {
5441
4439
case 0:
5442
tcg_gen_helper_1_0(helper_fsts_ST0, cpu_tmp2_i32);
5443
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5444
gen_op_st_T0_A0(OT_LONG + s->mem_index);
4440
gen_op_fsts_ST0_A0();
5445
4441
break;
5446
4442
case 1:
5447
tcg_gen_helper_1_0(helper_fistl_ST0, cpu_tmp2_i32);
5448
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5449
gen_op_st_T0_A0(OT_LONG + s->mem_index);
4443
gen_op_fistl_ST0_A0();
5450
4444
break;
5451
4445
case 2:
5452
tcg_gen_helper_1_0(helper_fstl_ST0, cpu_tmp1_i64);
5453
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5454
(s->mem_index >> 2) - 1);
4446
gen_op_fstl_ST0_A0();
5455
4447
break;
5456
4448
case 3:
5457
4449
default:
5458
tcg_gen_helper_1_0(helper_fist_ST0, cpu_tmp2_i32);
5459
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5460
gen_op_st_T0_A0(OT_WORD + s->mem_index);
4450
gen_op_fist_ST0_A0();
5461
4451
break;
5462
4452
}
5463
4453
if ((op & 7) == 3)
5464
tcg_gen_helper_0_0(helper_fpop);
4454
gen_op_fpop();
5465
4455
break;
5466
4456
}
5467
4457
break;
5468
4458
case 0x0c: /* fldenv mem */
5469
if (s->cc_op != CC_OP_DYNAMIC)
5470
gen_op_set_cc_op(s->cc_op);
5471
gen_jmp_im(pc_start - s->cs_base);
5472
tcg_gen_helper_0_2(helper_fldenv,
5473
cpu_A0, tcg_const_i32(s->dflag));
4459
gen_op_fldenv_A0(s->dflag);
5474
4460
break;
5475
4461
case 0x0d: /* fldcw mem */
5476
gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5477
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5478
tcg_gen_helper_0_1(helper_fldcw, cpu_tmp2_i32);
4462
gen_op_fldcw_A0();
5479
4463
break;
5480
4464
case 0x0e: /* fnstenv mem */
5481
if (s->cc_op != CC_OP_DYNAMIC)
5482
gen_op_set_cc_op(s->cc_op);
5483
gen_jmp_im(pc_start - s->cs_base);
5484
tcg_gen_helper_0_2(helper_fstenv,
5485
cpu_A0, tcg_const_i32(s->dflag));
4465
gen_op_fnstenv_A0(s->dflag);
5486
4466
break;
5487
4467
case 0x0f: /* fnstcw mem */
5488
tcg_gen_helper_1_0(helper_fnstcw, cpu_tmp2_i32);
5489
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5490
gen_op_st_T0_A0(OT_WORD + s->mem_index);
4468
gen_op_fnstcw_A0();
5491
4469
break;
5492
4470
case 0x1d: /* fldt mem */
5493
if (s->cc_op != CC_OP_DYNAMIC)
5494
gen_op_set_cc_op(s->cc_op);
5495
gen_jmp_im(pc_start - s->cs_base);
5496
tcg_gen_helper_0_1(helper_fldt_ST0, cpu_A0);
4471
gen_op_fldt_ST0_A0();
5497
4472
break;
5498
4473
case 0x1f: /* fstpt mem */
5499
if (s->cc_op != CC_OP_DYNAMIC)
5500
gen_op_set_cc_op(s->cc_op);
5501
gen_jmp_im(pc_start - s->cs_base);
5502
tcg_gen_helper_0_1(helper_fstt_ST0, cpu_A0);
5503
tcg_gen_helper_0_0(helper_fpop);
4474
gen_op_fstt_ST0_A0();
4475
gen_op_fpop();
5504
4476
break;
5505
4477
case 0x2c: /* frstor mem */
5506
if (s->cc_op != CC_OP_DYNAMIC)
5507
gen_op_set_cc_op(s->cc_op);
5508
gen_jmp_im(pc_start - s->cs_base);
5509
tcg_gen_helper_0_2(helper_frstor,
5510
cpu_A0, tcg_const_i32(s->dflag));
4478
gen_op_frstor_A0(s->dflag);
5511
4479
break;
5512
4480
case 0x2e: /* fnsave mem */
5513
if (s->cc_op != CC_OP_DYNAMIC)
5514
gen_op_set_cc_op(s->cc_op);
5515
gen_jmp_im(pc_start - s->cs_base);
5516
tcg_gen_helper_0_2(helper_fsave,
5517
cpu_A0, tcg_const_i32(s->dflag));
4481
gen_op_fnsave_A0(s->dflag);
5518
4482
break;
5519
4483
case 0x2f: /* fnstsw mem */
5520
tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32);
5521
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5522
gen_op_st_T0_A0(OT_WORD + s->mem_index);
4484
gen_op_fnstsw_A0();
5523
4485
break;
5524
4486
case 0x3c: /* fbld */
5525
if (s->cc_op != CC_OP_DYNAMIC)
5526
gen_op_set_cc_op(s->cc_op);
5527
gen_jmp_im(pc_start - s->cs_base);
5528
tcg_gen_helper_0_1(helper_fbld_ST0, cpu_A0);
4487
gen_op_fbld_ST0_A0();
5529
4488
break;
5530
4489
case 0x3e: /* fbstp */
5531
if (s->cc_op != CC_OP_DYNAMIC)
5532
gen_op_set_cc_op(s->cc_op);
5533
gen_jmp_im(pc_start - s->cs_base);
5534
tcg_gen_helper_0_1(helper_fbst_ST0, cpu_A0);
5535
tcg_gen_helper_0_0(helper_fpop);
4490
gen_op_fbst_ST0_A0();
4491
gen_op_fpop();
5536
4492
break;
5537
4493
case 0x3d: /* fildll */
5538
tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5539
(s->mem_index >> 2) - 1);
5540
tcg_gen_helper_0_1(helper_fildll_ST0, cpu_tmp1_i64);
4494
gen_op_fildll_ST0_A0();
5541
4495
break;
5542
4496
case 0x3f: /* fistpll */
5543
tcg_gen_helper_1_0(helper_fistll_ST0, cpu_tmp1_i64);
5544
tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5545
(s->mem_index >> 2) - 1);
5546
tcg_gen_helper_0_0(helper_fpop);
4497
gen_op_fistll_ST0_A0();
4498
gen_op_fpop();
5547
4499
break;
5548
4500
default:
5549
4501
goto illegal_op;
5554
4506
5555
4507
switch(op) {
5556
4508
case 0x08: /* fld sti */
5557
tcg_gen_helper_0_0(helper_fpush);
5558
tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32((opreg + 1) & 7));
4509
gen_op_fpush();
4510
gen_op_fmov_ST0_STN((opreg + 1) & 7);
5559
4511
break;
5560
4512
case 0x09: /* fxchg sti */
5561
4513
case 0x29: /* fxchg4 sti, undocumented op */
5562
4514
case 0x39: /* fxchg7 sti, undocumented op */
5563
tcg_gen_helper_0_1(helper_fxchg_ST0_STN, tcg_const_i32(opreg));
4515
gen_op_fxchg_ST0_STN(opreg);
5564
4516
break;
5565
4517
case 0x0a: /* grp d9/2 */
5566
4518
switch(rm) {
5569
4521
if (s->cc_op != CC_OP_DYNAMIC)
5570
4522
gen_op_set_cc_op(s->cc_op);
5571
4523
gen_jmp_im(pc_start - s->cs_base);
5572
tcg_gen_helper_0_0(helper_fwait);
4524
gen_op_fwait();
5573
4525
break;
5574
4526
default:
5575
4527
goto illegal_op;
5578
4530
case 0x0c: /* grp d9/4 */
5579
4531
switch(rm) {
5580
4532
case 0: /* fchs */
5581
tcg_gen_helper_0_0(helper_fchs_ST0);
4533
gen_op_fchs_ST0();
5582
4534
break;
5583
4535
case 1: /* fabs */
5584
tcg_gen_helper_0_0(helper_fabs_ST0);
4536
gen_op_fabs_ST0();
5585
4537
break;
5586
4538
case 4: /* ftst */
5587
tcg_gen_helper_0_0(helper_fldz_FT0);
5588
tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
4539
gen_op_fldz_FT0();
4540
gen_op_fcom_ST0_FT0();
5589
4541
break;
5590
4542
case 5: /* fxam */
5591
tcg_gen_helper_0_0(helper_fxam_ST0);
4543
gen_op_fxam_ST0();
5592
4544
break;
5593
4545
default:
5594
4546
goto illegal_op;
5598
4550
{
5599
4551
switch(rm) {
5600
4552
case 0:
5601
tcg_gen_helper_0_0(helper_fpush);
5602
tcg_gen_helper_0_0(helper_fld1_ST0);
4553
gen_op_fpush();
4554
gen_op_fld1_ST0();
5603
4555
break;
5604
4556
case 1:
5605
tcg_gen_helper_0_0(helper_fpush);
5606
tcg_gen_helper_0_0(helper_fldl2t_ST0);
4557
gen_op_fpush();
4558
gen_op_fldl2t_ST0();
5607
4559
break;
5608
4560
case 2:
5609
tcg_gen_helper_0_0(helper_fpush);
5610
tcg_gen_helper_0_0(helper_fldl2e_ST0);
4561
gen_op_fpush();
4562
gen_op_fldl2e_ST0();
5611
4563
break;
5612
4564
case 3:
5613
tcg_gen_helper_0_0(helper_fpush);
5614
tcg_gen_helper_0_0(helper_fldpi_ST0);
4565
gen_op_fpush();
4566
gen_op_fldpi_ST0();
5615
4567
break;
5616
4568
case 4:
5617
tcg_gen_helper_0_0(helper_fpush);
5618
tcg_gen_helper_0_0(helper_fldlg2_ST0);
4569
gen_op_fpush();
4570
gen_op_fldlg2_ST0();
5619
4571
break;
5620
4572
case 5:
5621
tcg_gen_helper_0_0(helper_fpush);
5622
tcg_gen_helper_0_0(helper_fldln2_ST0);
4573
gen_op_fpush();
4574
gen_op_fldln2_ST0();
5623
4575
break;
5624
4576
case 6:
5625
tcg_gen_helper_0_0(helper_fpush);
5626
tcg_gen_helper_0_0(helper_fldz_ST0);
4577
gen_op_fpush();
4578
gen_op_fldz_ST0();
5627
4579
break;
5628
4580
default:
5629
4581
goto illegal_op;
5633
4585
case 0x0e: /* grp d9/6 */
5634
4586
switch(rm) {
5635
4587
case 0: /* f2xm1 */
5636
tcg_gen_helper_0_0(helper_f2xm1);
4588
gen_op_f2xm1();
5637
4589
break;
5638
4590
case 1: /* fyl2x */
5639
tcg_gen_helper_0_0(helper_fyl2x);
4591
gen_op_fyl2x();
5640
4592
break;
5641
4593
case 2: /* fptan */
5642
tcg_gen_helper_0_0(helper_fptan);
4594
gen_op_fptan();
5643
4595
break;
5644
4596
case 3: /* fpatan */
5645
tcg_gen_helper_0_0(helper_fpatan);
4597
gen_op_fpatan();
5646
4598
break;
5647
4599
case 4: /* fxtract */
5648
tcg_gen_helper_0_0(helper_fxtract);
4600
gen_op_fxtract();
5649
4601
break;
5650
4602
case 5: /* fprem1 */
5651
tcg_gen_helper_0_0(helper_fprem1);
4603
gen_op_fprem1();
5652
4604
break;
5653
4605
case 6: /* fdecstp */
5654
tcg_gen_helper_0_0(helper_fdecstp);
4606
gen_op_fdecstp();
5655
4607
break;
5656
4608
default:
5657
4609
case 7: /* fincstp */
5658
tcg_gen_helper_0_0(helper_fincstp);
4610
gen_op_fincstp();
5659
4611
break;
5660
4612
}
5661
4613
break;
5662
4614
case 0x0f: /* grp d9/7 */
5663
4615
switch(rm) {
5664
4616
case 0: /* fprem */
5665
tcg_gen_helper_0_0(helper_fprem);
4617
gen_op_fprem();
5666
4618
break;
5667
4619
case 1: /* fyl2xp1 */
5668
tcg_gen_helper_0_0(helper_fyl2xp1);
4620
gen_op_fyl2xp1();
5669
4621
break;
5670
4622
case 2: /* fsqrt */
5671
tcg_gen_helper_0_0(helper_fsqrt);
4623
gen_op_fsqrt();
5672
4624
break;
5673
4625
case 3: /* fsincos */
5674
tcg_gen_helper_0_0(helper_fsincos);
4626
gen_op_fsincos();
5675
4627
break;
5676
4628
case 5: /* fscale */
5677
tcg_gen_helper_0_0(helper_fscale);
4629
gen_op_fscale();
5678
4630
break;
5679
4631
case 4: /* frndint */
5680
tcg_gen_helper_0_0(helper_frndint);
4632
gen_op_frndint();
5681
4633
break;
5682
4634
case 6: /* fsin */
5683
tcg_gen_helper_0_0(helper_fsin);
4635
gen_op_fsin();
5684
4636
break;
5685
4637
default:
5686
4638
case 7: /* fcos */
5687
tcg_gen_helper_0_0(helper_fcos);
4639
gen_op_fcos();
5688
4640
break;
5689
4641
}
5690
4642
break;
5693
4645
case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5694
4646
{
5695
4647
int op1;
5696
4648
5697
4649
op1 = op & 7;
5698
4650
if (op >= 0x20) {
5699
tcg_gen_helper_0_1(helper_fp_arith_STN_ST0[op1], tcg_const_i32(opreg));
4651
gen_op_fp_arith_STN_ST0[op1](opreg);
5700
4652
if (op >= 0x30)
5701
tcg_gen_helper_0_0(helper_fpop);
4653
gen_op_fpop();
5702
4654
} else {
5703
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5704
tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]);
4655
gen_op_fmov_FT0_STN(opreg);
4656
gen_op_fp_arith_ST0_FT0[op1]();
5705
4657
}
5706
4658
}
5707
4659
break;
5708
4660
case 0x02: /* fcom */
5709
4661
case 0x22: /* fcom2, undocumented op */
5710
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5711
tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
4662
gen_op_fmov_FT0_STN(opreg);
4663
gen_op_fcom_ST0_FT0();
5712
4664
break;
5713
4665
case 0x03: /* fcomp */
5714
4666
case 0x23: /* fcomp3, undocumented op */
5715
4667
case 0x32: /* fcomp5, undocumented op */
5716
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5717
tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5718
tcg_gen_helper_0_0(helper_fpop);
4668
gen_op_fmov_FT0_STN(opreg);
4669
gen_op_fcom_ST0_FT0();
4670
gen_op_fpop();
5719
4671
break;
5720
4672
case 0x15: /* da/5 */
5721
4673
switch(rm) {
5722
4674
case 1: /* fucompp */
5723
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
5724
tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5725
tcg_gen_helper_0_0(helper_fpop);
5726
tcg_gen_helper_0_0(helper_fpop);
4675
gen_op_fmov_FT0_STN(1);
4676
gen_op_fucom_ST0_FT0();
4677
gen_op_fpop();
4678
gen_op_fpop();
5727
4679
break;
5728
4680
default:
5729
4681
goto illegal_op;
5736
4688
case 1: /* fdisi (287 only, just do nop here) */
5737
4689
break;
5738
4690
case 2: /* fclex */
5739
tcg_gen_helper_0_0(helper_fclex);
4691
gen_op_fclex();
5740
4692
break;
5741
4693
case 3: /* fninit */
5742
tcg_gen_helper_0_0(helper_fninit);
4694
gen_op_fninit();
5743
4695
break;
5744
4696
case 4: /* fsetpm (287 only, just do nop here) */
5745
4697
break;
5750
4702
case 0x1d: /* fucomi */
5751
4703
if (s->cc_op != CC_OP_DYNAMIC)
5752
4704
gen_op_set_cc_op(s->cc_op);
5753
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5754
tcg_gen_helper_0_0(helper_fucomi_ST0_FT0);
4705
gen_op_fmov_FT0_STN(opreg);
4706
gen_op_fucomi_ST0_FT0();
5755
4707
s->cc_op = CC_OP_EFLAGS;
5756
4708
break;
5757
4709
case 0x1e: /* fcomi */
5758
4710
if (s->cc_op != CC_OP_DYNAMIC)
5759
4711
gen_op_set_cc_op(s->cc_op);
5760
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5761
tcg_gen_helper_0_0(helper_fcomi_ST0_FT0);
4712
gen_op_fmov_FT0_STN(opreg);
4713
gen_op_fcomi_ST0_FT0();
5762
4714
s->cc_op = CC_OP_EFLAGS;
5763
4715
break;
5764
4716
case 0x28: /* ffree sti */
5765
tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg));
5766
break;
4717
gen_op_ffree_STN(opreg);
4718
break;
5767
4719
case 0x2a: /* fst sti */
5768
tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg));
4720
gen_op_fmov_STN_ST0(opreg);
5769
4721
break;
5770
4722
case 0x2b: /* fstp sti */
5771
4723
case 0x0b: /* fstp1 sti, undocumented op */
5772
4724
case 0x3a: /* fstp8 sti, undocumented op */
5773
4725
case 0x3b: /* fstp9 sti, undocumented op */
5774
tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg));
5775
tcg_gen_helper_0_0(helper_fpop);
4726
gen_op_fmov_STN_ST0(opreg);
4727
gen_op_fpop();
5776
4728
break;
5777
4729
case 0x2c: /* fucom st(i) */
5778
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5779
tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
4730
gen_op_fmov_FT0_STN(opreg);
4731
gen_op_fucom_ST0_FT0();
5780
4732
break;
5781
4733
case 0x2d: /* fucomp st(i) */
5782
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5783
tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5784
tcg_gen_helper_0_0(helper_fpop);
4734
gen_op_fmov_FT0_STN(opreg);
4735
gen_op_fucom_ST0_FT0();
4736
gen_op_fpop();
5785
4737
break;
5786
4738
case 0x33: /* de/3 */
5787
4739
switch(rm) {
5788
4740
case 1: /* fcompp */
5789
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
5790
tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5791
tcg_gen_helper_0_0(helper_fpop);
5792
tcg_gen_helper_0_0(helper_fpop);
4741
gen_op_fmov_FT0_STN(1);
4742
gen_op_fcom_ST0_FT0();
4743
gen_op_fpop();
4744
gen_op_fpop();
5793
4745
break;
5794
4746
default:
5795
4747
goto illegal_op;
5796
4748
}
5797
4749
break;
5798
4750
case 0x38: /* ffreep sti, undocumented op */
5799
tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg));
5800
tcg_gen_helper_0_0(helper_fpop);
4751
gen_op_ffree_STN(opreg);
4752
gen_op_fpop();
5801
4753
break;
5802
4754
case 0x3c: /* df/4 */
5803
4755
switch(rm) {
5804
4756
case 0:
5805
tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32);
5806
tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5807
gen_op_mov_reg_T0(OT_WORD, R_EAX);
4757
gen_op_fnstsw_EAX();
5808
4758
break;
5809
4759
default:
5810
4760
goto illegal_op;
5813
4763
case 0x3d: /* fucomip */
5814
4764
if (s->cc_op != CC_OP_DYNAMIC)
5815
4765
gen_op_set_cc_op(s->cc_op);
5816
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5817
tcg_gen_helper_0_0(helper_fucomi_ST0_FT0);
5818
tcg_gen_helper_0_0(helper_fpop);
4766
gen_op_fmov_FT0_STN(opreg);
4767
gen_op_fucomi_ST0_FT0();
4768
gen_op_fpop();
5819
4769
s->cc_op = CC_OP_EFLAGS;
5820
4770
break;
5821
4771
case 0x3e: /* fcomip */
5822
4772
if (s->cc_op != CC_OP_DYNAMIC)
5823
4773
gen_op_set_cc_op(s->cc_op);
5824
tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5825
tcg_gen_helper_0_0(helper_fcomi_ST0_FT0);
5826
tcg_gen_helper_0_0(helper_fpop);
4774
gen_op_fmov_FT0_STN(opreg);
4775
gen_op_fcomi_ST0_FT0();
4776
gen_op_fpop();
5827
4777
s->cc_op = CC_OP_EFLAGS;
5828
4778
break;
5829
4779
case 0x10 ... 0x13: /* fcmovxx */
5830
4780
case 0x18 ... 0x1b:
5831
4781
{
5832
int op1, l1;
5833
static const uint8_t fcmov_cc[8] = {
4782
int op1;
4783
const static uint8_t fcmov_cc[8] = {
5834
4784
(JCC_B << 1),
5835
4785
(JCC_Z << 1),
5836
4786
(JCC_BE << 1),
5837
4787
(JCC_P << 1),
5838
4788
};
5839
op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
5840
l1 = gen_new_label();
5841
gen_jcc1(s, s->cc_op, op1, l1);
5842
tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32(opreg));
5843
gen_set_label(l1);
4789
op1 = fcmov_cc[op & 3] | ((op >> 3) & 1);
4790
gen_setcc(s, op1);
4791
gen_op_fcmov_ST0_STN_T0(opreg);
5844
4792
}
5845
4793
break;
5846
4794
default:
5847
4795
goto illegal_op;
5848
4796
}
5849
4797
}
4798
#ifdef USE_CODE_COPY
4799
s->tb->cflags |= CF_TB_FP_USED;
4800
#endif
5850
4801
break;
5851
4802
/************************/
5852
4803
/* string ops */
5864
4815
gen_movs(s, ot);
5865
4816
}
5866
4817
break;
5867
4818
5868
4819
case 0xaa: /* stosS */
5869
4820
case 0xab:
5870
4821
if ((b & 1) == 0)
5927
4878
ot = OT_BYTE;
5928
4879
else
5929
4880
ot = dflag ? OT_LONG : OT_WORD;
5930
gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5931
gen_op_andl_T0_ffff();
5932
gen_check_io(s, ot, pc_start - s->cs_base,
5933
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
4881
gen_check_io(s, ot, 1, pc_start - s->cs_base);
5934
4882
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5935
4883
gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5936
4884
} else {
5937
4885
gen_ins(s, ot);
5938
if (use_icount) {
5939
gen_jmp(s, s->pc - s->cs_base);
5940
}
5941
4886
}
5942
4887
break;
5943
4888
case 0x6e: /* outsS */
5946
4891
ot = OT_BYTE;
5947
4892
else
5948
4893
ot = dflag ? OT_LONG : OT_WORD;
5949
gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5950
gen_op_andl_T0_ffff();
5951
gen_check_io(s, ot, pc_start - s->cs_base,
5952
svm_is_rep(prefixes) | 4);
4894
gen_check_io(s, ot, 1, pc_start - s->cs_base);
5953
4895
if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5954
4896
gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5955
4897
} else {
5956
4898
gen_outs(s, ot);
5957
if (use_icount) {
5958
gen_jmp(s, s->pc - s->cs_base);
5959
}
5960
4899
}
5961
4900
break;
5962
4901
5963
4902
/************************/
5964
4903
/* port I/O */
5965
5966
4904
case 0xe4:
5967
4905
case 0xe5:
5968
4906
if ((b & 1) == 0)
5971
4909
ot = dflag ? OT_LONG : OT_WORD;
5972
4910
val = ldub_code(s->pc++);
5973
4911
gen_op_movl_T0_im(val);
5974
gen_check_io(s, ot, pc_start - s->cs_base,
5975
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
5976
if (use_icount)
5977
gen_io_start();
5978
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5979
tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
5980
gen_op_mov_reg_T1(ot, R_EAX);
5981
if (use_icount) {
5982
gen_io_end();
5983
gen_jmp(s, s->pc - s->cs_base);
5984
}
4912
gen_check_io(s, ot, 0, pc_start - s->cs_base);
4913
gen_op_in[ot]();
4914
gen_op_mov_reg_T1[ot][R_EAX]();
5985
4915
break;
5986
4916
case 0xe6:
5987
4917
case 0xe7:
5991
4921
ot = dflag ? OT_LONG : OT_WORD;
5992
4922
val = ldub_code(s->pc++);
5993
4923
gen_op_movl_T0_im(val);
5994
gen_check_io(s, ot, pc_start - s->cs_base,
5995
svm_is_rep(prefixes));
5996
gen_op_mov_TN_reg(ot, 1, R_EAX);
5997
5998
if (use_icount)
5999
gen_io_start();
6000
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6001
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
6002
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6003
tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
6004
if (use_icount) {
6005
gen_io_end();
6006
gen_jmp(s, s->pc - s->cs_base);
6007
}
4924
gen_check_io(s, ot, 0, pc_start - s->cs_base);
4925
gen_op_mov_TN_reg[ot][1][R_EAX]();
4926
gen_op_out[ot]();
6008
4927
break;
6009
4928
case 0xec:
6010
4929
case 0xed:
6012
4931
ot = OT_BYTE;
6013
4932
else
6014
4933
ot = dflag ? OT_LONG : OT_WORD;
6015
gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
4934
gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
6016
4935
gen_op_andl_T0_ffff();
6017
gen_check_io(s, ot, pc_start - s->cs_base,
6018
SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6019
if (use_icount)
6020
gen_io_start();
6021
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6022
tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
6023
gen_op_mov_reg_T1(ot, R_EAX);
6024
if (use_icount) {
6025
gen_io_end();
6026
gen_jmp(s, s->pc - s->cs_base);
6027
}
4936
gen_check_io(s, ot, 0, pc_start - s->cs_base);
4937
gen_op_in[ot]();
4938
gen_op_mov_reg_T1[ot][R_EAX]();
6028
4939
break;
6029
4940
case 0xee:
6030
4941
case 0xef:
6032
4943
ot = OT_BYTE;
6033
4944
else
6034
4945
ot = dflag ? OT_LONG : OT_WORD;
6035
gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
4946
gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
6036
4947
gen_op_andl_T0_ffff();
6037
gen_check_io(s, ot, pc_start - s->cs_base,
6038
svm_is_rep(prefixes));
6039
gen_op_mov_TN_reg(ot, 1, R_EAX);
6040
6041
if (use_icount)
6042
gen_io_start();
6043
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6044
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
6045
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6046
tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
6047
if (use_icount) {
6048
gen_io_end();
6049
gen_jmp(s, s->pc - s->cs_base);
6050
}
4948
gen_check_io(s, ot, 0, pc_start - s->cs_base);
4949
gen_op_mov_TN_reg[ot][1][R_EAX]();
4950
gen_op_out[ot]();
6051
4951
break;
6052
4952
6053
4953
/************************/
6080
4980
if (s->cc_op != CC_OP_DYNAMIC)
6081
4981
gen_op_set_cc_op(s->cc_op);
6082
4982
gen_jmp_im(pc_start - s->cs_base);
6083
tcg_gen_helper_0_2(helper_lret_protected,
6084
tcg_const_i32(s->dflag),
6085
tcg_const_i32(val));
4983
gen_op_lret_protected(s->dflag, val);
6086
4984
} else {
6087
4985
gen_stack_A0(s);
6088
4986
/* pop offset */
6089
gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
4987
gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
6090
4988
if (s->dflag == 0)
6091
4989
gen_op_andl_T0_ffff();
6092
4990
/* NOTE: keeping EIP updated is not a problem in case of
6094
4992
gen_op_jmp_T0();
6095
4993
/* pop selector */
6096
4994
gen_op_addl_A0_im(2 << s->dflag);
6097
gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6098
gen_op_movl_seg_T0_vm(R_CS);
4995
gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
4996
gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
6099
4997
/* add stack offset */
6100
4998
gen_stack_update(s, val + (4 << s->dflag));
6101
4999
}
6105
5003
val = 0;
6106
5004
goto do_lret;
6107
5005
case 0xcf: /* iret */
6108
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
6109
5006
if (!s->pe) {
6110
5007
/* real mode */
6111
tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag));
5008
gen_op_iret_real(s->dflag);
6112
5009
s->cc_op = CC_OP_EFLAGS;
6113
5010
} else if (s->vm86) {
6114
5011
if (s->iopl != 3) {
6115
5012
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6116
5013
} else {
6117
tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag));
5014
gen_op_iret_real(s->dflag);
6118
5015
s->cc_op = CC_OP_EFLAGS;
6119
5016
}
6120
5017
} else {
6121
5018
if (s->cc_op != CC_OP_DYNAMIC)
6122
5019
gen_op_set_cc_op(s->cc_op);
6123
5020
gen_jmp_im(pc_start - s->cs_base);
6124
tcg_gen_helper_0_2(helper_iret_protected,
6125
tcg_const_i32(s->dflag),
6126
tcg_const_i32(s->pc - s->cs_base));
5021
gen_op_iret_protected(s->dflag, s->pc - s->cs_base);
6127
5022
s->cc_op = CC_OP_EFLAGS;
6128
5023
}
6129
5024
gen_eob(s);
6146
5041
case 0x9a: /* lcall im */
6147
5042
{
6148
5043
unsigned int selector, offset;
6149
5044
6150
5045
if (CODE64(s))
6151
5046
goto illegal_op;
6152
5047
ot = dflag ? OT_LONG : OT_WORD;
6153
5048
offset = insn_get(s, ot);
6154
5049
selector = insn_get(s, OT_WORD);
6155
5050
6156
5051
gen_op_movl_T0_im(selector);
6157
5052
gen_op_movl_T1_imu(offset);
6158
5053
}
6176
5071
ot = dflag ? OT_LONG : OT_WORD;
6177
5072
offset = insn_get(s, ot);
6178
5073
selector = insn_get(s, OT_WORD);
6179
5074
6180
5075
gen_op_movl_T0_im(selector);
6181
5076
gen_op_movl_T1_imu(offset);
6182
5077
}
6195
5090
if (dflag) {
6196
5091
tval = (int32_t)insn_get(s, OT_LONG);
6197
5092
} else {
6198
tval = (int16_t)insn_get(s, OT_WORD);
5093
tval = (int16_t)insn_get(s, OT_WORD);
6199
5094
}
6200
5095
do_jcc:
6201
5096
next_eip = s->pc - s->cs_base;
6211
5106
gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
6212
5107
break;
6213
5108
case 0x140 ... 0x14f: /* cmov Gv, Ev */
6214
{
6215
int l1;
6216
TCGv t0;
6217
6218
ot = dflag + OT_WORD;
6219
modrm = ldub_code(s->pc++);
6220
reg = ((modrm >> 3) & 7) | rex_r;
6221
mod = (modrm >> 6) & 3;
6222
t0 = tcg_temp_local_new(TCG_TYPE_TL);
6223
if (mod != 3) {
6224
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6225
gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
6226
} else {
6227
rm = (modrm & 7) | REX_B(s);
6228
gen_op_mov_v_reg(ot, t0, rm);
6229
}
6230
#ifdef TARGET_X86_64
6231
if (ot == OT_LONG) {
6232
/* XXX: specific Intel behaviour ? */
6233
l1 = gen_new_label();
6234
gen_jcc1(s, s->cc_op, b ^ 1, l1);
6235
tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
6236
gen_set_label(l1);
6237
tcg_gen_movi_tl(cpu_tmp0, 0);
6238
tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
6239
} else
6240
#endif
6241
{
6242
l1 = gen_new_label();
6243
gen_jcc1(s, s->cc_op, b ^ 1, l1);
6244
gen_op_mov_reg_v(ot, reg, t0);
6245
gen_set_label(l1);
6246
}
6247
tcg_temp_free(t0);
5109
ot = dflag + OT_WORD;
5110
modrm = ldub_code(s->pc++);
5111
reg = ((modrm >> 3) & 7) | rex_r;
5112
mod = (modrm >> 6) & 3;
5113
gen_setcc(s, b);
5114
if (mod != 3) {
5115
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5116
gen_op_ld_T1_A0[ot + s->mem_index]();
5117
} else {
5118
rm = (modrm & 7) | REX_B(s);
5119
gen_op_mov_TN_reg[ot][1][rm]();
6248
5120
}
5121
gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
6249
5122
break;
6250
5123
6251
5124
/************************/
6252
5125
/* flags */
6253
5126
case 0x9c: /* pushf */
6254
gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
6255
5127
if (s->vm86 && s->iopl != 3) {
6256
5128
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6257
5129
} else {
6258
5130
if (s->cc_op != CC_OP_DYNAMIC)
6259
5131
gen_op_set_cc_op(s->cc_op);
6260
tcg_gen_helper_1_0(helper_read_eflags, cpu_T[0]);
5132
gen_op_movl_T0_eflags();
6261
5133
gen_push_T0(s);
6262
5134
}
6263
5135
break;
6264
5136
case 0x9d: /* popf */
6265
gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
6266
5137
if (s->vm86 && s->iopl != 3) {
6267
5138
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6268
5139
} else {
6269
5140
gen_pop_T0(s);
6270
5141
if (s->cpl == 0) {
6271
5142
if (s->dflag) {
6272
tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6273
tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)));
5143
gen_op_movl_eflags_T0_cpl0();
6274
5144
} else {
6275
tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6276
tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff));
5145
gen_op_movw_eflags_T0_cpl0();
6277
5146
}
6278
5147
} else {
6279
5148
if (s->cpl <= s->iopl) {
6280
5149
if (s->dflag) {
6281
tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6282
tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)));
5150
gen_op_movl_eflags_T0_io();
6283
5151
} else {
6284
tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6285
tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff));
5152
gen_op_movw_eflags_T0_io();
6286
5153
}
6287
5154
} else {
6288
5155
if (s->dflag) {
6289
tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6290
tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK)));
5156
gen_op_movl_eflags_T0();
6291
5157
} else {
6292
tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6293
tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff));
5158
gen_op_movw_eflags_T0();
6294
5159
}
6295
5160
}
6296
5161
}
6302
5167
}
6303
5168
break;
6304
5169
case 0x9e: /* sahf */
6305
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
5170
if (CODE64(s))
6306
5171
goto illegal_op;
6307
gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
5172
gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
6308
5173
if (s->cc_op != CC_OP_DYNAMIC)
6309
5174
gen_op_set_cc_op(s->cc_op);
6310
gen_compute_eflags(cpu_cc_src);
6311
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6312
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6313
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
5175
gen_op_movb_eflags_T0();
6314
5176
s->cc_op = CC_OP_EFLAGS;
6315
5177
break;
6316
5178
case 0x9f: /* lahf */
6317
if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
5179
if (CODE64(s))
6318
5180
goto illegal_op;
6319
5181
if (s->cc_op != CC_OP_DYNAMIC)
6320
5182
gen_op_set_cc_op(s->cc_op);
6321
gen_compute_eflags(cpu_T[0]);
6322
/* Note: gen_compute_eflags() only gives the condition codes */
6323
tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02);
6324
gen_op_mov_reg_T0(OT_BYTE, R_AH);
5183
gen_op_movl_T0_eflags();
5184
gen_op_mov_reg_T0[OT_BYTE][R_AH]();
6325
5185
break;
6326
5186
case 0xf5: /* cmc */
6327
5187
if (s->cc_op != CC_OP_DYNAMIC)
6328
5188
gen_op_set_cc_op(s->cc_op);
6329
gen_compute_eflags(cpu_cc_src);
6330
tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
5189
gen_op_cmc();
6331
5190
s->cc_op = CC_OP_EFLAGS;
6332
5191
break;
6333
5192
case 0xf8: /* clc */
6334
5193
if (s->cc_op != CC_OP_DYNAMIC)
6335
5194
gen_op_set_cc_op(s->cc_op);
6336
gen_compute_eflags(cpu_cc_src);
6337
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
5195
gen_op_clc();
6338
5196
s->cc_op = CC_OP_EFLAGS;
6339
5197
break;
6340
5198
case 0xf9: /* stc */
6341
5199
if (s->cc_op != CC_OP_DYNAMIC)
6342
5200
gen_op_set_cc_op(s->cc_op);
6343
gen_compute_eflags(cpu_cc_src);
6344
tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
5201
gen_op_stc();
6345
5202
s->cc_op = CC_OP_EFLAGS;
6346
5203
break;
6347
5204
case 0xfc: /* cld */
6348
tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6349
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
5205
gen_op_cld();
6350
5206
break;
6351
5207
case 0xfd: /* std */
6352
tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6353
tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
5208
gen_op_std();
6354
5209
break;
6355
5210
6356
5211
/************************/
6364
5219
if (mod != 3) {
6365
5220
s->rip_offset = 1;
6366
5221
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6367
gen_op_ld_T0_A0(ot + s->mem_index);
5222
gen_op_ld_T0_A0[ot + s->mem_index]();
6368
5223
} else {
6369
gen_op_mov_TN_reg(ot, 0, rm);
5224
gen_op_mov_TN_reg[ot][0][rm]();
6370
5225
}
6371
5226
/* load shift */
6372
5227
val = ldub_code(s->pc++);
6374
5229
if (op < 4)
6375
5230
goto illegal_op;
6376
5231
op -= 4;
6377
goto bt_op;
5232
gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
5233
s->cc_op = CC_OP_SARB + ot;
5234
if (op != 0) {
5235
if (mod != 3)
5236
gen_op_st_T0_A0[ot + s->mem_index]();
5237
else
5238
gen_op_mov_reg_T0[ot][rm]();
5239
gen_op_update_bt_cc();
5240
}
5241
break;
6378
5242
case 0x1a3: /* bt Gv, Ev */
6379
5243
op = 0;
6380
5244
goto do_btx;
6392
5256
reg = ((modrm >> 3) & 7) | rex_r;
6393
5257
mod = (modrm >> 6) & 3;
6394
5258
rm = (modrm & 7) | REX_B(s);
6395
gen_op_mov_TN_reg(OT_LONG, 1, reg);
5259
gen_op_mov_TN_reg[OT_LONG][1][reg]();
6396
5260
if (mod != 3) {
6397
5261
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6398
5262
/* specific case: we need to add a displacement */
6399
gen_exts(ot, cpu_T[1]);
6400
tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6401
tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6402
tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6403
gen_op_ld_T0_A0(ot + s->mem_index);
5263
gen_op_add_bit_A0_T1[ot - OT_WORD]();
5264
gen_op_ld_T0_A0[ot + s->mem_index]();
6404
5265
} else {
6405
gen_op_mov_TN_reg(ot, 0, rm);
6406
}
6407
bt_op:
6408
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6409
switch(op) {
6410
case 0:
6411
tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6412
tcg_gen_movi_tl(cpu_cc_dst, 0);
6413
break;
6414
case 1:
6415
tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6416
tcg_gen_movi_tl(cpu_tmp0, 1);
6417
tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6418
tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6419
break;
6420
case 2:
6421
tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6422
tcg_gen_movi_tl(cpu_tmp0, 1);
6423
tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6424
tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6425
tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6426
break;
6427
default:
6428
case 3:
6429
tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6430
tcg_gen_movi_tl(cpu_tmp0, 1);
6431
tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6432
tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6433
break;
6434
}
5266
gen_op_mov_TN_reg[ot][0][rm]();
5267
}
5268
gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
6435
5269
s->cc_op = CC_OP_SARB + ot;
6436
5270
if (op != 0) {
6437
5271
if (mod != 3)
6438
gen_op_st_T0_A0(ot + s->mem_index);
5272
gen_op_st_T0_A0[ot + s->mem_index]();
6439
5273
else
6440
gen_op_mov_reg_T0(ot, rm);
6441
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6442
tcg_gen_movi_tl(cpu_cc_dst, 0);
5274
gen_op_mov_reg_T0[ot][rm]();
5275
gen_op_update_bt_cc();
6443
5276
}
6444
5277
break;
6445
5278
case 0x1bc: /* bsf */
6446
5279
case 0x1bd: /* bsr */
6447
{
6448
int label1;
6449
TCGv t0;
6450
6451
ot = dflag + OT_WORD;
6452
modrm = ldub_code(s->pc++);
6453
reg = ((modrm >> 3) & 7) | rex_r;
6454
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
6455
gen_extu(ot, cpu_T[0]);
6456
label1 = gen_new_label();
6457
tcg_gen_movi_tl(cpu_cc_dst, 0);
6458
t0 = tcg_temp_local_new(TCG_TYPE_TL);
6459
tcg_gen_mov_tl(t0, cpu_T[0]);
6460
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
6461
if (b & 1) {
6462
tcg_gen_helper_1_1(helper_bsr, cpu_T[0], t0);
6463
} else {
6464
tcg_gen_helper_1_1(helper_bsf, cpu_T[0], t0);
6465
}
6466
gen_op_mov_reg_T0(ot, reg);
6467
tcg_gen_movi_tl(cpu_cc_dst, 1);
6468
gen_set_label(label1);
6469
tcg_gen_discard_tl(cpu_cc_src);
6470
s->cc_op = CC_OP_LOGICB + ot;
6471
tcg_temp_free(t0);
6472
}
5280
ot = dflag + OT_WORD;
5281
modrm = ldub_code(s->pc++);
5282
reg = ((modrm >> 3) & 7) | rex_r;
5283
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5284
/* NOTE: in order to handle the 0 case, we must load the
5285
result. It could be optimized with a generated jump */
5286
gen_op_mov_TN_reg[ot][1][reg]();
5287
gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
5288
gen_op_mov_reg_T1[ot][reg]();
5289
s->cc_op = CC_OP_LOGICB + ot;
6473
5290
break;
6474
5291
/************************/
6475
5292
/* bcd */
6478
5295
goto illegal_op;
6479
5296
if (s->cc_op != CC_OP_DYNAMIC)
6480
5297
gen_op_set_cc_op(s->cc_op);
6481
tcg_gen_helper_0_0(helper_daa);
5298
gen_op_daa();
6482
5299
s->cc_op = CC_OP_EFLAGS;
6483
5300
break;
6484
5301
case 0x2f: /* das */
6486
5303
goto illegal_op;
6487
5304
if (s->cc_op != CC_OP_DYNAMIC)
6488
5305
gen_op_set_cc_op(s->cc_op);
6489
tcg_gen_helper_0_0(helper_das);
5306
gen_op_das();
6490
5307
s->cc_op = CC_OP_EFLAGS;
6491
5308
break;
6492
5309
case 0x37: /* aaa */
6494
5311
goto illegal_op;
6495
5312
if (s->cc_op != CC_OP_DYNAMIC)
6496
5313
gen_op_set_cc_op(s->cc_op);
6497
tcg_gen_helper_0_0(helper_aaa);
5314
gen_op_aaa();
6498
5315
s->cc_op = CC_OP_EFLAGS;
6499
5316
break;
6500
5317
case 0x3f: /* aas */
6502
5319
goto illegal_op;
6503
5320
if (s->cc_op != CC_OP_DYNAMIC)
6504
5321
gen_op_set_cc_op(s->cc_op);
6505
tcg_gen_helper_0_0(helper_aas);
5322
gen_op_aas();
6506
5323
s->cc_op = CC_OP_EFLAGS;
6507
5324
break;
6508
5325
case 0xd4: /* aam */
6509
5326
if (CODE64(s))
6510
5327
goto illegal_op;
6511
5328
val = ldub_code(s->pc++);
6512
if (val == 0) {
6513
gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6514
} else {
6515
tcg_gen_helper_0_1(helper_aam, tcg_const_i32(val));
6516
s->cc_op = CC_OP_LOGICB;
6517
}
5329
gen_op_aam(val);
5330
s->cc_op = CC_OP_LOGICB;
6518
5331
break;
6519
5332
case 0xd5: /* aad */
6520
5333
if (CODE64(s))
6521
5334
goto illegal_op;
6522
5335
val = ldub_code(s->pc++);
6523
tcg_gen_helper_0_1(helper_aad, tcg_const_i32(val));
5336
gen_op_aad(val);
6524
5337
s->cc_op = CC_OP_LOGICB;
6525
5338
break;
6526
5339
/************************/
6530
5343
/* XXX: correct lock test for all insn */
6531
5344
if (prefixes & PREFIX_LOCK)
6532
5345
goto illegal_op;
6533
if (prefixes & PREFIX_REPZ) {
6534
gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6535
}
6536
5346
break;
6537
5347
case 0x9b: /* fwait */
6538
if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
5348
if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6539
5349
(HF_MP_MASK | HF_TS_MASK)) {
6540
5350
gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6541
5351
} else {
6542
5352
if (s->cc_op != CC_OP_DYNAMIC)
6543
5353
gen_op_set_cc_op(s->cc_op);
6544
5354
gen_jmp_im(pc_start - s->cs_base);
6545
tcg_gen_helper_0_0(helper_fwait);
5355
gen_op_fwait();
6546
5356
}
6547
5357
break;
6548
5358
case 0xcc: /* int3 */
6551
5361
case 0xcd: /* int N */
6552
5362
val = ldub_code(s->pc++);
6553
5363
if (s->vm86 && s->iopl != 3) {
6554
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5364
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6555
5365
} else {
6556
5366
gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6557
5367
}
6562
5372
if (s->cc_op != CC_OP_DYNAMIC)
6563
5373
gen_op_set_cc_op(s->cc_op);
6564
5374
gen_jmp_im(pc_start - s->cs_base);
6565
tcg_gen_helper_0_1(helper_into, tcg_const_i32(s->pc - pc_start));
5375
gen_op_into(s->pc - pc_start);
6566
5376
break;
6567
5377
case 0xf1: /* icebp (undocumented, exits to external debugger) */
6568
gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
6569
5378
#if 1
6570
5379
gen_debug(s, pc_start - s->cs_base);
6571
5380
#else
6577
5386
case 0xfa: /* cli */
6578
5387
if (!s->vm86) {
6579
5388
if (s->cpl <= s->iopl) {
6580
tcg_gen_helper_0_0(helper_cli);
5389
gen_op_cli();
6581
5390
} else {
6582
5391
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6583
5392
}
6584
5393
} else {
6585
5394
if (s->iopl == 3) {
6586
tcg_gen_helper_0_0(helper_cli);
5395
gen_op_cli();
6587
5396
} else {
6588
5397
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6589
5398
}
6593
5402
if (!s->vm86) {
6594
5403
if (s->cpl <= s->iopl) {
6595
5404
gen_sti:
6596
tcg_gen_helper_0_0(helper_sti);
5405
gen_op_sti();
6597
5406
/* interruptions are enabled only the first insn after sti */
6598
5407
/* If several instructions disable interrupts, only the
6599
5408
_first_ does it */
6600
5409
if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6601
tcg_gen_helper_0_0(helper_set_inhibit_irq);
5410
gen_op_set_inhibit_irq();
6602
5411
/* give a chance to handle pending irqs */
6603
5412
gen_jmp_im(s->pc - s->cs_base);
6604
5413
gen_eob(s);
6622
5431
mod = (modrm >> 6) & 3;
6623
5432
if (mod == 3)
6624
5433
goto illegal_op;
6625
gen_op_mov_TN_reg(ot, 0, reg);
5434
gen_op_mov_TN_reg[ot][0][reg]();
6626
5435
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6627
5436
gen_jmp_im(pc_start - s->cs_base);
6628
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6629
5437
if (ot == OT_WORD)
6630
tcg_gen_helper_0_2(helper_boundw, cpu_A0, cpu_tmp2_i32);
5438
gen_op_boundw();
6631
5439
else
6632
tcg_gen_helper_0_2(helper_boundl, cpu_A0, cpu_tmp2_i32);
5440
gen_op_boundl();
6633
5441
break;
6634
5442
case 0x1c8 ... 0x1cf: /* bswap reg */
6635
5443
reg = (b & 7) | REX_B(s);
6636
5444
#ifdef TARGET_X86_64
6637
5445
if (dflag == 2) {
6638
gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6639
tcg_gen_bswap_i64(cpu_T[0], cpu_T[0]);
6640
gen_op_mov_reg_T0(OT_QUAD, reg);
6641
} else
6642
{
6643
TCGv tmp0;
6644
gen_op_mov_TN_reg(OT_LONG, 0, reg);
6645
6646
tmp0 = tcg_temp_new(TCG_TYPE_I32);
6647
tcg_gen_trunc_i64_i32(tmp0, cpu_T[0]);
6648
tcg_gen_bswap_i32(tmp0, tmp0);
6649
tcg_gen_extu_i32_i64(cpu_T[0], tmp0);
6650
gen_op_mov_reg_T0(OT_LONG, reg);
6651
}
6652
#else
6653
{
6654
gen_op_mov_TN_reg(OT_LONG, 0, reg);
6655
tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]);
6656
gen_op_mov_reg_T0(OT_LONG, reg);
6657
}
5446
gen_op_mov_TN_reg[OT_QUAD][0][reg]();
5447
gen_op_bswapq_T0();
5448
gen_op_mov_reg_T0[OT_QUAD][reg]();
5449
} else
6658
5450
#endif
5451
{
5452
gen_op_mov_TN_reg[OT_LONG][0][reg]();
5453
gen_op_bswapl_T0();
5454
gen_op_mov_reg_T0[OT_LONG][reg]();
5455
}
6659
5456
break;
6660
5457
case 0xd6: /* salc */
6661
5458
if (CODE64(s))
6662
5459
goto illegal_op;
6663
5460
if (s->cc_op != CC_OP_DYNAMIC)
6664
5461
gen_op_set_cc_op(s->cc_op);
6665
gen_compute_eflags_c(cpu_T[0]);
6666
tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6667
gen_op_mov_reg_T0(OT_BYTE, R_EAX);
5462
gen_op_salc();
6668
5463
break;
6669
5464
case 0xe0: /* loopnz */
6670
5465
case 0xe1: /* loopz */
5466
if (s->cc_op != CC_OP_DYNAMIC)
5467
gen_op_set_cc_op(s->cc_op);
5468
/* FALL THRU */
6671
5469
case 0xe2: /* loop */
6672
5470
case 0xe3: /* jecxz */
6673
5471
{
6674
int l1, l2, l3;
5472
int l1, l2;
6675
5473
6676
5474
tval = (int8_t)insn_get(s, OT_BYTE);
6677
5475
next_eip = s->pc - s->cs_base;
6678
5476
tval += next_eip;
6679
5477
if (s->dflag == 0)
6680
5478
tval &= 0xffff;
6681
5479
6682
5480
l1 = gen_new_label();
6683
5481
l2 = gen_new_label();
6684
l3 = gen_new_label();
6685
5482
b &= 3;
6686
switch(b) {
6687
case 0: /* loopnz */
6688
case 1: /* loopz */
6689
if (s->cc_op != CC_OP_DYNAMIC)
6690
gen_op_set_cc_op(s->cc_op);
6691
gen_op_add_reg_im(s->aflag, R_ECX, -1);
6692
gen_op_jz_ecx(s->aflag, l3);
6693
gen_compute_eflags(cpu_tmp0);
6694
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
6695
if (b == 0) {
6696
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
6697
} else {
6698
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1);
6699
}
6700
break;
6701
case 2: /* loop */
6702
gen_op_add_reg_im(s->aflag, R_ECX, -1);
6703
gen_op_jnz_ecx(s->aflag, l1);
6704
break;
6705
default:
6706
case 3: /* jcxz */
6707
gen_op_jz_ecx(s->aflag, l1);
6708
break;
5483
if (b == 3) {
5484
gen_op_jz_ecx[s->aflag](l1);
5485
} else {
5486
gen_op_dec_ECX[s->aflag]();
5487
if (b <= 1)
5488
gen_op_mov_T0_cc();
5489
gen_op_loop[s->aflag][b](l1);
6709
5490
}
6710
5491
6711
gen_set_label(l3);
6712
5492
gen_jmp_im(next_eip);
6713
tcg_gen_br(l2);
6714
5493
gen_op_jmp_label(l2);
6715
5494
gen_set_label(l1);
6716
5495
gen_jmp_im(tval);
6717
5496
gen_set_label(l2);
6723
5502
if (s->cpl != 0) {
6724
5503
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6725
5504
} else {
6726
if (s->cc_op != CC_OP_DYNAMIC)
6727
gen_op_set_cc_op(s->cc_op);
6728
gen_jmp_im(pc_start - s->cs_base);
6729
if (b & 2) {
6730
tcg_gen_helper_0_0(helper_rdmsr);
6731
} else {
6732
tcg_gen_helper_0_0(helper_wrmsr);
6733
}
5505
if (b & 2)
5506
gen_op_rdmsr();
5507
else
5508
gen_op_wrmsr();
6734
5509
}
6735
5510
break;
6736
5511
case 0x131: /* rdtsc */
6737
if (s->cc_op != CC_OP_DYNAMIC)
6738
gen_op_set_cc_op(s->cc_op);
6739
gen_jmp_im(pc_start - s->cs_base);
6740
if (use_icount)
6741
gen_io_start();
6742
tcg_gen_helper_0_0(helper_rdtsc);
6743
if (use_icount) {
6744
gen_io_end();
6745
gen_jmp(s, s->pc - s->cs_base);
6746
}
6747
break;
6748
case 0x133: /* rdpmc */
6749
if (s->cc_op != CC_OP_DYNAMIC)
6750
gen_op_set_cc_op(s->cc_op);
6751
gen_jmp_im(pc_start - s->cs_base);
6752
tcg_gen_helper_0_0(helper_rdpmc);
5512
gen_jmp_im(pc_start - s->cs_base);
5513
gen_op_rdtsc();
6753
5514
break;
6754
5515
case 0x134: /* sysenter */
6755
/* For Intel SYSENTER is valid on 64-bit */
6756
if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
5516
if (CODE64(s))
6757
5517
goto illegal_op;
6758
5518
if (!s->pe) {
6759
5519
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6763
5523
s->cc_op = CC_OP_DYNAMIC;
6764
5524
}
6765
5525
gen_jmp_im(pc_start - s->cs_base);
6766
tcg_gen_helper_0_0(helper_sysenter);
5526
gen_op_sysenter();
6767
5527
gen_eob(s);
6768
5528
}
6769
5529
break;
6770
5530
case 0x135: /* sysexit */
6771
/* For Intel SYSEXIT is valid on 64-bit */
6772
if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
5531
if (CODE64(s))
6773
5532
goto illegal_op;
6774
5533
if (!s->pe) {
6775
5534
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6779
5538
s->cc_op = CC_OP_DYNAMIC;
6780
5539
}
6781
5540
gen_jmp_im(pc_start - s->cs_base);
6782
tcg_gen_helper_0_1(helper_sysexit, tcg_const_i32(dflag));
5541
gen_op_sysexit();
6783
5542
gen_eob(s);
6784
5543
}
6785
5544
break;
6791
5550
s->cc_op = CC_OP_DYNAMIC;
6792
5551
}
6793
5552
gen_jmp_im(pc_start - s->cs_base);
6794
tcg_gen_helper_0_1(helper_syscall, tcg_const_i32(s->pc - pc_start));
5553
gen_op_syscall(s->pc - pc_start);
6795
5554
gen_eob(s);
6796
5555
break;
6797
5556
case 0x107: /* sysret */
6803
5562
s->cc_op = CC_OP_DYNAMIC;
6804
5563
}
6805
5564
gen_jmp_im(pc_start - s->cs_base);
6806
tcg_gen_helper_0_1(helper_sysret, tcg_const_i32(s->dflag));
5565
gen_op_sysret(s->dflag);
6807
5566
/* condition codes are modified only in long mode */
6808
5567
if (s->lma)
6809
5568
s->cc_op = CC_OP_EFLAGS;
6812
5571
break;
6813
5572
#endif
6814
5573
case 0x1a2: /* cpuid */
6815
if (s->cc_op != CC_OP_DYNAMIC)
6816
gen_op_set_cc_op(s->cc_op);
6817
gen_jmp_im(pc_start - s->cs_base);
6818
tcg_gen_helper_0_0(helper_cpuid);
5574
gen_op_cpuid();
6819
5575
break;
6820
5576
case 0xf4: /* hlt */
6821
5577
if (s->cpl != 0) {
6823
5579
} else {
6824
5580
if (s->cc_op != CC_OP_DYNAMIC)
6825
5581
gen_op_set_cc_op(s->cc_op);
6826
gen_jmp_im(pc_start - s->cs_base);
6827
tcg_gen_helper_0_1(helper_hlt, tcg_const_i32(s->pc - pc_start));
5582
gen_jmp_im(s->pc - s->cs_base);
5583
gen_op_hlt();
6828
5584
s->is_jmp = 3;
6829
5585
}
6830
5586
break;
6836
5592
case 0: /* sldt */
6837
5593
if (!s->pe || s->vm86)
6838
5594
goto illegal_op;
6839
gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
6840
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
5595
gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
6841
5596
ot = OT_WORD;
6842
5597
if (mod == 3)
6843
5598
ot += s->dflag;
6849
5604
if (s->cpl != 0) {
6850
5605
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6851
5606
} else {
6852
gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
6853
5607
gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6854
5608
gen_jmp_im(pc_start - s->cs_base);
6855
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6856
tcg_gen_helper_0_1(helper_lldt, cpu_tmp2_i32);
5609
gen_op_lldt_T0();
6857
5610
}
6858
5611
break;
6859
5612
case 1: /* str */
6860
5613
if (!s->pe || s->vm86)
6861
5614
goto illegal_op;
6862
gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
6863
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
5615
gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
6864
5616
ot = OT_WORD;
6865
5617
if (mod == 3)
6866
5618
ot += s->dflag;
6872
5624
if (s->cpl != 0) {
6873
5625
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6874
5626
} else {
6875
gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
6876
5627
gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6877
5628
gen_jmp_im(pc_start - s->cs_base);
6878
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6879
tcg_gen_helper_0_1(helper_ltr, cpu_tmp2_i32);
5629
gen_op_ltr_T0();
6880
5630
}
6881
5631
break;
6882
5632
case 4: /* verr */
6887
5637
if (s->cc_op != CC_OP_DYNAMIC)
6888
5638
gen_op_set_cc_op(s->cc_op);
6889
5639
if (op == 4)
6890
tcg_gen_helper_0_1(helper_verr, cpu_T[0]);
5640
gen_op_verr();
6891
5641
else
6892
tcg_gen_helper_0_1(helper_verw, cpu_T[0]);
5642
gen_op_verw();
6893
5643
s->cc_op = CC_OP_EFLAGS;
6894
5644
break;
6895
5645
default:
6905
5655
case 0: /* sgdt */
6906
5656
if (mod == 3)
6907
5657
goto illegal_op;
6908
gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
6909
5658
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6910
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
6911
gen_op_st_T0_A0(OT_WORD + s->mem_index);
5659
gen_op_movl_T0_env(offsetof(CPUX86State, gdt.limit));
5660
gen_op_st_T0_A0[OT_WORD + s->mem_index]();
6912
5661
gen_add_A0_im(s, 2);
6913
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
5662
gen_op_movtl_T0_env(offsetof(CPUX86State, gdt.base));
6914
5663
if (!s->dflag)
6915
5664
gen_op_andl_T0_im(0xffffff);
6916
gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
5665
gen_op_st_T0_A0[CODE64(s) + OT_LONG + s->mem_index]();
6917
5666
break;
6918
5667
case 1:
6919
5668
if (mod == 3) {
6922
5671
if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
6923
5672
s->cpl != 0)
6924
5673
goto illegal_op;
6925
if (s->cc_op != CC_OP_DYNAMIC)
6926
gen_op_set_cc_op(s->cc_op);
6927
5674
gen_jmp_im(pc_start - s->cs_base);
6928
5675
#ifdef TARGET_X86_64
6929
5676
if (s->aflag == 2) {
6930
gen_op_movq_A0_reg(R_EAX);
6931
} else
5677
gen_op_movq_A0_reg[R_EBX]();
5678
gen_op_addq_A0_AL();
5679
} else
6932
5680
#endif
6933
5681
{
6934
gen_op_movl_A0_reg(R_EAX);
5682
gen_op_movl_A0_reg[R_EBX]();
5683
gen_op_addl_A0_AL();
6935
5684
if (s->aflag == 0)
6936
5685
gen_op_andl_A0_ffff();
6937
5686
}
6938
5687
gen_add_A0_ds_seg(s);
6939
tcg_gen_helper_0_1(helper_monitor, cpu_A0);
5688
gen_op_monitor();
6940
5689
break;
6941
5690
case 1: /* mwait */
6942
5691
if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
6946
5695
gen_op_set_cc_op(s->cc_op);
6947
5696
s->cc_op = CC_OP_DYNAMIC;
6948
5697
}
6949
gen_jmp_im(pc_start - s->cs_base);
6950
tcg_gen_helper_0_1(helper_mwait, tcg_const_i32(s->pc - pc_start));
5698
gen_jmp_im(s->pc - s->cs_base);
5699
gen_op_mwait();
6951
5700
gen_eob(s);
6952
5701
break;
6953
5702
default:
6954
5703
goto illegal_op;
6955
5704
}
6956
5705
} else { /* sidt */
6957
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
6958
5706
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6959
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
6960
gen_op_st_T0_A0(OT_WORD + s->mem_index);
5707
gen_op_movl_T0_env(offsetof(CPUX86State, idt.limit));
5708
gen_op_st_T0_A0[OT_WORD + s->mem_index]();
6961
5709
gen_add_A0_im(s, 2);
6962
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
5710
gen_op_movtl_T0_env(offsetof(CPUX86State, idt.base));
6963
5711
if (!s->dflag)
6964
5712
gen_op_andl_T0_im(0xffffff);
6965
gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
5713
gen_op_st_T0_A0[CODE64(s) + OT_LONG + s->mem_index]();
6966
5714
}
6967
5715
break;
6968
5716
case 2: /* lgdt */
6969
5717
case 3: /* lidt */
6970
if (mod == 3) {
6971
if (s->cc_op != CC_OP_DYNAMIC)
6972
gen_op_set_cc_op(s->cc_op);
6973
gen_jmp_im(pc_start - s->cs_base);
6974
switch(rm) {
6975
case 0: /* VMRUN */
6976
if (!(s->flags & HF_SVME_MASK) || !s->pe)
6977
goto illegal_op;
6978
if (s->cpl != 0) {
6979
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6980
break;
6981
} else {
6982
tcg_gen_helper_0_2(helper_vmrun,
6983
tcg_const_i32(s->aflag),
6984
tcg_const_i32(s->pc - pc_start));
6985
tcg_gen_exit_tb(0);
6986
s->is_jmp = 3;
6987
}
6988
break;
6989
case 1: /* VMMCALL */
6990
if (!(s->flags & HF_SVME_MASK))
6991
goto illegal_op;
6992
tcg_gen_helper_0_0(helper_vmmcall);
6993
break;
6994
case 2: /* VMLOAD */
6995
if (!(s->flags & HF_SVME_MASK) || !s->pe)
6996
goto illegal_op;
6997
if (s->cpl != 0) {
6998
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6999
break;
7000
} else {
7001
tcg_gen_helper_0_1(helper_vmload,
7002
tcg_const_i32(s->aflag));
7003
}
7004
break;
7005
case 3: /* VMSAVE */
7006
if (!(s->flags & HF_SVME_MASK) || !s->pe)
7007
goto illegal_op;
7008
if (s->cpl != 0) {
7009
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7010
break;
7011
} else {
7012
tcg_gen_helper_0_1(helper_vmsave,
7013
tcg_const_i32(s->aflag));
7014
}
7015
break;
7016
case 4: /* STGI */
7017
if ((!(s->flags & HF_SVME_MASK) &&
7018
!(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7019
!s->pe)
7020
goto illegal_op;
7021
if (s->cpl != 0) {
7022
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7023
break;
7024
} else {
7025
tcg_gen_helper_0_0(helper_stgi);
7026
}
7027
break;
7028
case 5: /* CLGI */
7029
if (!(s->flags & HF_SVME_MASK) || !s->pe)
7030
goto illegal_op;
7031
if (s->cpl != 0) {
7032
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7033
break;
7034
} else {
7035
tcg_gen_helper_0_0(helper_clgi);
7036
}
7037
break;
7038
case 6: /* SKINIT */
7039
if ((!(s->flags & HF_SVME_MASK) &&
7040
!(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7041
!s->pe)
7042
goto illegal_op;
7043
tcg_gen_helper_0_0(helper_skinit);
7044
break;
7045
case 7: /* INVLPGA */
7046
if (!(s->flags & HF_SVME_MASK) || !s->pe)
7047
goto illegal_op;
7048
if (s->cpl != 0) {
7049
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7050
break;
7051
} else {
7052
tcg_gen_helper_0_1(helper_invlpga,
7053
tcg_const_i32(s->aflag));
7054
}
7055
break;
7056
default:
7057
goto illegal_op;
7058
}
7059
} else if (s->cpl != 0) {
5718
if (mod == 3)
5719
goto illegal_op;
5720
if (s->cpl != 0) {
7060
5721
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7061
5722
} else {
7062
gen_svm_check_intercept(s, pc_start,
7063
op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
7064
5723
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7065
gen_op_ld_T1_A0(OT_WORD + s->mem_index);
5724
gen_op_ld_T1_A0[OT_WORD + s->mem_index]();
7066
5725
gen_add_A0_im(s, 2);
7067
gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
5726
gen_op_ld_T0_A0[CODE64(s) + OT_LONG + s->mem_index]();
7068
5727
if (!s->dflag)
7069
5728
gen_op_andl_T0_im(0xffffff);
7070
5729
if (op == 2) {
7071
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7072
tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
5730
gen_op_movtl_env_T0(offsetof(CPUX86State,gdt.base));
5731
gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
7073
5732
} else {
7074
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7075
tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
5733
gen_op_movtl_env_T0(offsetof(CPUX86State,idt.base));
5734
gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
7076
5735
}
7077
5736
}
7078
5737
break;
7079
5738
case 4: /* smsw */
7080
gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
7081
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
5739
gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
7082
5740
gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
7083
5741
break;
7084
5742
case 6: /* lmsw */
7085
5743
if (s->cpl != 0) {
7086
5744
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7087
5745
} else {
7088
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7089
5746
gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7090
tcg_gen_helper_0_1(helper_lmsw, cpu_T[0]);
5747
gen_op_lmsw_T0();
7091
5748
gen_jmp_im(s->pc - s->cs_base);
7092
5749
gen_eob(s);
7093
5750
}
7100
5757
#ifdef TARGET_X86_64
7101
5758
if (CODE64(s) && rm == 0) {
7102
5759
/* swapgs */
7103
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
7104
tcg_gen_ld_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,kernelgsbase));
7105
tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
7106
tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,kernelgsbase));
7107
} else
5760
gen_op_movtl_T0_env(offsetof(CPUX86State,segs[R_GS].base));
5761
gen_op_movtl_T1_env(offsetof(CPUX86State,kernelgsbase));
5762
gen_op_movtl_env_T1(offsetof(CPUX86State,segs[R_GS].base));
5763
gen_op_movtl_env_T0(offsetof(CPUX86State,kernelgsbase));
5764
} else
7108
5765
#endif
7109
5766
{
7110
5767
goto illegal_op;
7111
5768
}
7112
5769
} else {
7113
if (s->cc_op != CC_OP_DYNAMIC)
7114
gen_op_set_cc_op(s->cc_op);
7115
gen_jmp_im(pc_start - s->cs_base);
7116
5770
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7117
tcg_gen_helper_0_1(helper_invlpg, cpu_A0);
5771
gen_op_invlpg_A0();
7118
5772
gen_jmp_im(s->pc - s->cs_base);
7119
5773
gen_eob(s);
7120
5774
}
7129
5783
if (s->cpl != 0) {
7130
5784
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7131
5785
} else {
7132
gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
7133
5786
/* nothing to do */
7134
5787
}
7135
5788
break;
7144
5797
reg = ((modrm >> 3) & 7) | rex_r;
7145
5798
mod = (modrm >> 6) & 3;
7146
5799
rm = (modrm & 7) | REX_B(s);
7147
5800
7148
5801
if (mod == 3) {
7149
gen_op_mov_TN_reg(OT_LONG, 0, rm);
5802
gen_op_mov_TN_reg[OT_LONG][0][rm]();
7150
5803
/* sign extend */
7151
5804
if (d_ot == OT_QUAD)
7152
tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
7153
gen_op_mov_reg_T0(d_ot, reg);
5805
gen_op_movslq_T0_T0();
5806
gen_op_mov_reg_T0[d_ot][reg]();
7154
5807
} else {
7155
5808
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7156
5809
if (d_ot == OT_QUAD) {
7157
gen_op_lds_T0_A0(OT_LONG + s->mem_index);
5810
gen_op_lds_T0_A0[OT_LONG + s->mem_index]();
7158
5811
} else {
7159
gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5812
gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
7160
5813
}
7161
gen_op_mov_reg_T0(d_ot, reg);
5814
gen_op_mov_reg_T0[d_ot][reg]();
7162
5815
}
7163
} else
5816
} else
7164
5817
#endif
7165
5818
{
7166
int label1;
7167
TCGv t0, t1, t2;
7168
7169
5819
if (!s->pe || s->vm86)
7170
5820
goto illegal_op;
7171
t0 = tcg_temp_local_new(TCG_TYPE_TL);
7172
t1 = tcg_temp_local_new(TCG_TYPE_TL);
7173
t2 = tcg_temp_local_new(TCG_TYPE_TL);
7174
ot = OT_WORD;
5821
ot = dflag ? OT_LONG : OT_WORD;
7175
5822
modrm = ldub_code(s->pc++);
7176
5823
reg = (modrm >> 3) & 7;
7177
5824
mod = (modrm >> 6) & 3;
7178
5825
rm = modrm & 7;
7179
5826
if (mod != 3) {
7180
5827
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7181
gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
7182
} else {
7183
gen_op_mov_v_reg(ot, t0, rm);
7184
}
7185
gen_op_mov_v_reg(ot, t1, reg);
7186
tcg_gen_andi_tl(cpu_tmp0, t0, 3);
7187
tcg_gen_andi_tl(t1, t1, 3);
7188
tcg_gen_movi_tl(t2, 0);
7189
label1 = gen_new_label();
7190
tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
7191
tcg_gen_andi_tl(t0, t0, ~3);
7192
tcg_gen_or_tl(t0, t0, t1);
7193
tcg_gen_movi_tl(t2, CC_Z);
7194
gen_set_label(label1);
7195
if (mod != 3) {
7196
gen_op_st_v(ot + s->mem_index, t0, cpu_A0);
7197
} else {
7198
gen_op_mov_reg_v(ot, rm, t0);
5828
gen_op_ld_T0_A0[ot + s->mem_index]();
5829
} else {
5830
gen_op_mov_TN_reg[ot][0][rm]();
7199
5831
}
7200
5832
if (s->cc_op != CC_OP_DYNAMIC)
7201
5833
gen_op_set_cc_op(s->cc_op);
7202
gen_compute_eflags(cpu_cc_src);
7203
tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
7204
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
5834
gen_op_arpl();
7205
5835
s->cc_op = CC_OP_EFLAGS;
7206
tcg_temp_free(t0);
7207
tcg_temp_free(t1);
7208
tcg_temp_free(t2);
5836
if (mod != 3) {
5837
gen_op_st_T0_A0[ot + s->mem_index]();
5838
} else {
5839
gen_op_mov_reg_T0[ot][rm]();
5840
}
5841
gen_op_arpl_update();
7209
5842
}
7210
5843
break;
7211
5844
case 0x102: /* lar */
7212
5845
case 0x103: /* lsl */
7213
{
7214
int label1;
7215
TCGv t0;
7216
if (!s->pe || s->vm86)
7217
goto illegal_op;
7218
ot = dflag ? OT_LONG : OT_WORD;
7219
modrm = ldub_code(s->pc++);
7220
reg = ((modrm >> 3) & 7) | rex_r;
7221
gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7222
t0 = tcg_temp_local_new(TCG_TYPE_TL);
7223
if (s->cc_op != CC_OP_DYNAMIC)
7224
gen_op_set_cc_op(s->cc_op);
7225
if (b == 0x102)
7226
tcg_gen_helper_1_1(helper_lar, t0, cpu_T[0]);
7227
else
7228
tcg_gen_helper_1_1(helper_lsl, t0, cpu_T[0]);
7229
tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
7230
label1 = gen_new_label();
7231
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
7232
gen_op_mov_reg_v(ot, reg, t0);
7233
gen_set_label(label1);
7234
s->cc_op = CC_OP_EFLAGS;
7235
tcg_temp_free(t0);
7236
}
5846
if (!s->pe || s->vm86)
5847
goto illegal_op;
5848
ot = dflag ? OT_LONG : OT_WORD;
5849
modrm = ldub_code(s->pc++);
5850
reg = ((modrm >> 3) & 7) | rex_r;
5851
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5852
gen_op_mov_TN_reg[ot][1][reg]();
5853
if (s->cc_op != CC_OP_DYNAMIC)
5854
gen_op_set_cc_op(s->cc_op);
5855
if (b == 0x102)
5856
gen_op_lar();
5857
else
5858
gen_op_lsl();
5859
s->cc_op = CC_OP_EFLAGS;
5860
gen_op_mov_reg_T1[ot][reg]();
7237
5861
break;
7238
5862
case 0x118:
7239
5863
modrm = ldub_code(s->pc++);
7278
5902
case 3:
7279
5903
case 4:
7280
5904
case 8:
7281
if (s->cc_op != CC_OP_DYNAMIC)
7282
gen_op_set_cc_op(s->cc_op);
7283
gen_jmp_im(pc_start - s->cs_base);
7284
5905
if (b & 2) {
7285
gen_op_mov_TN_reg(ot, 0, rm);
7286
tcg_gen_helper_0_2(helper_write_crN,
7287
tcg_const_i32(reg), cpu_T[0]);
5906
gen_op_mov_TN_reg[ot][0][rm]();
5907
gen_op_movl_crN_T0(reg);
7288
5908
gen_jmp_im(s->pc - s->cs_base);
7289
5909
gen_eob(s);
7290
5910
} else {
7291
tcg_gen_helper_1_1(helper_read_crN,
7292
cpu_T[0], tcg_const_i32(reg));
7293
gen_op_mov_reg_T0(ot, rm);
5911
#if !defined(CONFIG_USER_ONLY)
5912
if (reg == 8)
5913
gen_op_movtl_T0_cr8();
5914
else
5915
#endif
5916
gen_op_movtl_T0_env(offsetof(CPUX86State,cr[reg]));
5917
gen_op_mov_reg_T0[ot][rm]();
7294
5918
}
7295
5919
break;
7296
5920
default:
7316
5940
if (reg == 4 || reg == 5 || reg >= 8)
7317
5941
goto illegal_op;
7318
5942
if (b & 2) {
7319
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
7320
gen_op_mov_TN_reg(ot, 0, rm);
7321
tcg_gen_helper_0_2(helper_movl_drN_T0,
7322
tcg_const_i32(reg), cpu_T[0]);
5943
gen_op_mov_TN_reg[ot][0][rm]();
5944
gen_op_movl_drN_T0(reg);
7323
5945
gen_jmp_im(s->pc - s->cs_base);
7324
5946
gen_eob(s);
7325
5947
} else {
7326
gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
7327
tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7328
gen_op_mov_reg_T0(ot, rm);
5948
gen_op_movtl_T0_env(offsetof(CPUX86State,dr[reg]));
5949
gen_op_mov_reg_T0[ot][rm]();
7329
5950
}
7330
5951
}
7331
5952
break;
7333
5954
if (s->cpl != 0) {
7334
5955
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7335
5956
} else {
7336
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7337
tcg_gen_helper_0_0(helper_clts);
5957
gen_op_clts();
7338
5958
/* abort block because static cpu state changed */
7339
5959
gen_jmp_im(s->pc - s->cs_base);
7340
5960
gen_eob(s);
7341
5961
}
7342
5962
break;
7343
/* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
5963
/* MMX/SSE/SSE2/PNI support */
7344
5964
case 0x1c3: /* MOVNTI reg, mem */
7345
5965
if (!(s->cpuid_features & CPUID_SSE2))
7346
5966
goto illegal_op;
7359
5979
op = (modrm >> 3) & 7;
7360
5980
switch(op) {
7361
5981
case 0: /* fxsave */
7362
if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
5982
if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7363
5983
(s->flags & HF_EM_MASK))
7364
5984
goto illegal_op;
7365
5985
if (s->flags & HF_TS_MASK) {
7367
5987
break;
7368
5988
}
7369
5989
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7370
if (s->cc_op != CC_OP_DYNAMIC)
7371
gen_op_set_cc_op(s->cc_op);
7372
gen_jmp_im(pc_start - s->cs_base);
7373
tcg_gen_helper_0_2(helper_fxsave,
7374
cpu_A0, tcg_const_i32((s->dflag == 2)));
5990
gen_op_fxsave_A0((s->dflag == 2));
7375
5991
break;
7376
5992
case 1: /* fxrstor */
7377
if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
5993
if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7378
5994
(s->flags & HF_EM_MASK))
7379
5995
goto illegal_op;
7380
5996
if (s->flags & HF_TS_MASK) {
7382
5998
break;
7383
5999
}
7384
6000
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7385
if (s->cc_op != CC_OP_DYNAMIC)
7386
gen_op_set_cc_op(s->cc_op);
7387
gen_jmp_im(pc_start - s->cs_base);
7388
tcg_gen_helper_0_2(helper_fxrstor,
7389
cpu_A0, tcg_const_i32((s->dflag == 2)));
6001
gen_op_fxrstor_A0((s->dflag == 2));
7390
6002
break;
7391
6003
case 2: /* ldmxcsr */
7392
6004
case 3: /* stmxcsr */
7399
6011
goto illegal_op;
7400
6012
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7401
6013
if (op == 2) {
7402
gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7403
tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
6014
gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
6015
gen_op_movl_env_T0(offsetof(CPUX86State, mxcsr));
7404
6016
} else {
7405
tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7406
gen_op_st_T0_A0(OT_LONG + s->mem_index);
6017
gen_op_movl_T0_env(offsetof(CPUX86State, mxcsr));
6018
gen_op_st_T0_A0[OT_LONG + s->mem_index]();
7407
6019
}
7408
6020
break;
7409
6021
case 5: /* lfence */
7414
6026
case 7: /* sfence / clflush */
7415
6027
if ((modrm & 0xc7) == 0xc0) {
7416
6028
/* sfence */
7417
/* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7418
6029
if (!(s->cpuid_features & CPUID_SSE))
7419
6030
goto illegal_op;
7420
6031
} else {
7428
6039
goto illegal_op;
7429
6040
}
7430
6041
break;
7431
case 0x10d: /* 3DNow! prefetch(w) */
6042
case 0x10d: /* prefetch */
7432
6043
modrm = ldub_code(s->pc++);
7433
mod = (modrm >> 6) & 3;
7434
if (mod == 3)
7435
goto illegal_op;
7436
6044
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7437
6045
/* ignore for now */
7438
6046
break;
7439
6047
case 0x1aa: /* rsm */
7440
gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
7441
6048
if (!(s->flags & HF_SMM_MASK))
7442
6049
goto illegal_op;
7443
6050
if (s->cc_op != CC_OP_DYNAMIC) {
7445
6052
s->cc_op = CC_OP_DYNAMIC;
7446
6053
}
7447
6054
gen_jmp_im(s->pc - s->cs_base);
7448
tcg_gen_helper_0_0(helper_rsm);
6055
gen_op_rsm();
7449
6056
gen_eob(s);
7450
6057
break;
7451
case 0x1b8: /* SSE4.2 popcnt */
7452
if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
7453
PREFIX_REPZ)
7454
goto illegal_op;
7455
if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
7456
goto illegal_op;
7457
7458
modrm = ldub_code(s->pc++);
7459
reg = ((modrm >> 3) & 7);
7460
7461
if (s->prefix & PREFIX_DATA)
7462
ot = OT_WORD;
7463
else if (s->dflag != 2)
7464
ot = OT_LONG;
7465
else
7466
ot = OT_QUAD;
7467
7468
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
7469
tcg_gen_helper_1_2(helper_popcnt,
7470
cpu_T[0], cpu_T[0], tcg_const_i32(ot));
7471
gen_op_mov_reg_T0(ot, reg);
7472
7473
s->cc_op = CC_OP_EFLAGS;
7474
break;
7475
case 0x10e ... 0x10f:
7476
/* 3DNow! instructions, ignore prefixes */
7477
s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7478
6058
case 0x110 ... 0x117:
7479
6059
case 0x128 ... 0x12f:
7480
case 0x138 ... 0x13a:
7481
6060
case 0x150 ... 0x177:
7482
6061
case 0x17c ... 0x17f:
7483
6062
case 0x1c2:
7490
6069
}
7491
6070
/* lock generation */
7492
6071
if (s->prefix & PREFIX_LOCK)
7493
tcg_gen_helper_0_0(helper_unlock);
6072
gen_op_unlock();
7494
6073
return s->pc;
7495
6074
illegal_op:
7496
6075
if (s->prefix & PREFIX_LOCK)
7497
tcg_gen_helper_0_0(helper_unlock);
6076
gen_op_unlock();
7498
6077
/* XXX: ensure that no lock was generated */
7499
6078
gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7500
6079
return s->pc;
7501
6080
}
7502
6081
6082
#define CC_OSZAPC (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C)
6083
#define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P)
6084
6085
/* flags read by an operation */
6086
static uint16_t opc_read_flags[NB_OPS] = {
6087
[INDEX_op_aas] = CC_A,
6088
[INDEX_op_aaa] = CC_A,
6089
[INDEX_op_das] = CC_A | CC_C,
6090
[INDEX_op_daa] = CC_A | CC_C,
6091
6092
/* subtle: due to the incl/decl implementation, C is used */
6093
[INDEX_op_update_inc_cc] = CC_C,
6094
6095
[INDEX_op_into] = CC_O,
6096
6097
[INDEX_op_jb_subb] = CC_C,
6098
[INDEX_op_jb_subw] = CC_C,
6099
[INDEX_op_jb_subl] = CC_C,
6100
6101
[INDEX_op_jz_subb] = CC_Z,
6102
[INDEX_op_jz_subw] = CC_Z,
6103
[INDEX_op_jz_subl] = CC_Z,
6104
6105
[INDEX_op_jbe_subb] = CC_Z | CC_C,
6106
[INDEX_op_jbe_subw] = CC_Z | CC_C,
6107
[INDEX_op_jbe_subl] = CC_Z | CC_C,
6108
6109
[INDEX_op_js_subb] = CC_S,
6110
[INDEX_op_js_subw] = CC_S,
6111
[INDEX_op_js_subl] = CC_S,
6112
6113
[INDEX_op_jl_subb] = CC_O | CC_S,
6114
[INDEX_op_jl_subw] = CC_O | CC_S,
6115
[INDEX_op_jl_subl] = CC_O | CC_S,
6116
6117
[INDEX_op_jle_subb] = CC_O | CC_S | CC_Z,
6118
[INDEX_op_jle_subw] = CC_O | CC_S | CC_Z,
6119
[INDEX_op_jle_subl] = CC_O | CC_S | CC_Z,
6120
6121
[INDEX_op_loopnzw] = CC_Z,
6122
[INDEX_op_loopnzl] = CC_Z,
6123
[INDEX_op_loopzw] = CC_Z,
6124
[INDEX_op_loopzl] = CC_Z,
6125
6126
[INDEX_op_seto_T0_cc] = CC_O,
6127
[INDEX_op_setb_T0_cc] = CC_C,
6128
[INDEX_op_setz_T0_cc] = CC_Z,
6129
[INDEX_op_setbe_T0_cc] = CC_Z | CC_C,
6130
[INDEX_op_sets_T0_cc] = CC_S,
6131
[INDEX_op_setp_T0_cc] = CC_P,
6132
[INDEX_op_setl_T0_cc] = CC_O | CC_S,
6133
[INDEX_op_setle_T0_cc] = CC_O | CC_S | CC_Z,
6134
6135
[INDEX_op_setb_T0_subb] = CC_C,
6136
[INDEX_op_setb_T0_subw] = CC_C,
6137
[INDEX_op_setb_T0_subl] = CC_C,
6138
6139
[INDEX_op_setz_T0_subb] = CC_Z,
6140
[INDEX_op_setz_T0_subw] = CC_Z,
6141
[INDEX_op_setz_T0_subl] = CC_Z,
6142
6143
[INDEX_op_setbe_T0_subb] = CC_Z | CC_C,
6144
[INDEX_op_setbe_T0_subw] = CC_Z | CC_C,
6145
[INDEX_op_setbe_T0_subl] = CC_Z | CC_C,
6146
6147
[INDEX_op_sets_T0_subb] = CC_S,
6148
[INDEX_op_sets_T0_subw] = CC_S,
6149
[INDEX_op_sets_T0_subl] = CC_S,
6150
6151
[INDEX_op_setl_T0_subb] = CC_O | CC_S,
6152
[INDEX_op_setl_T0_subw] = CC_O | CC_S,
6153
[INDEX_op_setl_T0_subl] = CC_O | CC_S,
6154
6155
[INDEX_op_setle_T0_subb] = CC_O | CC_S | CC_Z,
6156
[INDEX_op_setle_T0_subw] = CC_O | CC_S | CC_Z,
6157
[INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z,
6158
6159
[INDEX_op_movl_T0_eflags] = CC_OSZAPC,
6160
[INDEX_op_cmc] = CC_C,
6161
[INDEX_op_salc] = CC_C,
6162
6163
/* needed for correct flag optimisation before string ops */
6164
[INDEX_op_jnz_ecxw] = CC_OSZAPC,
6165
[INDEX_op_jnz_ecxl] = CC_OSZAPC,
6166
[INDEX_op_jz_ecxw] = CC_OSZAPC,
6167
[INDEX_op_jz_ecxl] = CC_OSZAPC,
6168
6169
#ifdef TARGET_X86_64
6170
[INDEX_op_jb_subq] = CC_C,
6171
[INDEX_op_jz_subq] = CC_Z,
6172
[INDEX_op_jbe_subq] = CC_Z | CC_C,
6173
[INDEX_op_js_subq] = CC_S,
6174
[INDEX_op_jl_subq] = CC_O | CC_S,
6175
[INDEX_op_jle_subq] = CC_O | CC_S | CC_Z,
6176
6177
[INDEX_op_loopnzq] = CC_Z,
6178
[INDEX_op_loopzq] = CC_Z,
6179
6180
[INDEX_op_setb_T0_subq] = CC_C,
6181
[INDEX_op_setz_T0_subq] = CC_Z,
6182
[INDEX_op_setbe_T0_subq] = CC_Z | CC_C,
6183
[INDEX_op_sets_T0_subq] = CC_S,
6184
[INDEX_op_setl_T0_subq] = CC_O | CC_S,
6185
[INDEX_op_setle_T0_subq] = CC_O | CC_S | CC_Z,
6186
6187
[INDEX_op_jnz_ecxq] = CC_OSZAPC,
6188
[INDEX_op_jz_ecxq] = CC_OSZAPC,
6189
#endif
6190
6191
#define DEF_READF(SUFFIX)\
6192
[INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_C,\
6193
[INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_C,\
6194
[INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_C,\
6195
X86_64_DEF([INDEX_op_adcq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
6196
[INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_C,\
6197
[INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_C,\
6198
[INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_C,\
6199
X86_64_DEF([INDEX_op_sbbq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
6200
\
6201
[INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_C,\
6202
[INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_C,\
6203
[INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_C,\
6204
X86_64_DEF([INDEX_op_rclq ## SUFFIX ## _T0_T1_cc] = CC_C,)\
6205
[INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_C,\
6206
[INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_C,\
6207
[INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_C,\
6208
X86_64_DEF([INDEX_op_rcrq ## SUFFIX ## _T0_T1_cc] = CC_C,)
6209
6210
DEF_READF( )
6211
DEF_READF(_raw)
6212
#ifndef CONFIG_USER_ONLY
6213
DEF_READF(_kernel)
6214
DEF_READF(_user)
6215
#endif
6216
};
6217
6218
/* flags written by an operation */
6219
static uint16_t opc_write_flags[NB_OPS] = {
6220
[INDEX_op_update2_cc] = CC_OSZAPC,
6221
[INDEX_op_update1_cc] = CC_OSZAPC,
6222
[INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
6223
[INDEX_op_update_neg_cc] = CC_OSZAPC,
6224
/* subtle: due to the incl/decl implementation, C is used */
6225
[INDEX_op_update_inc_cc] = CC_OSZAPC,
6226
[INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
6227
6228
[INDEX_op_mulb_AL_T0] = CC_OSZAPC,
6229
[INDEX_op_mulw_AX_T0] = CC_OSZAPC,
6230
[INDEX_op_mull_EAX_T0] = CC_OSZAPC,
6231
X86_64_DEF([INDEX_op_mulq_EAX_T0] = CC_OSZAPC,)
6232
[INDEX_op_imulb_AL_T0] = CC_OSZAPC,
6233
[INDEX_op_imulw_AX_T0] = CC_OSZAPC,
6234
[INDEX_op_imull_EAX_T0] = CC_OSZAPC,
6235
X86_64_DEF([INDEX_op_imulq_EAX_T0] = CC_OSZAPC,)
6236
[INDEX_op_imulw_T0_T1] = CC_OSZAPC,
6237
[INDEX_op_imull_T0_T1] = CC_OSZAPC,
6238
X86_64_DEF([INDEX_op_imulq_T0_T1] = CC_OSZAPC,)
6239
6240
/* sse */
6241
[INDEX_op_ucomiss] = CC_OSZAPC,
6242
[INDEX_op_ucomisd] = CC_OSZAPC,
6243
[INDEX_op_comiss] = CC_OSZAPC,
6244
[INDEX_op_comisd] = CC_OSZAPC,
6245
6246
/* bcd */
6247
[INDEX_op_aam] = CC_OSZAPC,
6248
[INDEX_op_aad] = CC_OSZAPC,
6249
[INDEX_op_aas] = CC_OSZAPC,
6250
[INDEX_op_aaa] = CC_OSZAPC,
6251
[INDEX_op_das] = CC_OSZAPC,
6252
[INDEX_op_daa] = CC_OSZAPC,
6253
6254
[INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C,
6255
[INDEX_op_movw_eflags_T0] = CC_OSZAPC,
6256
[INDEX_op_movl_eflags_T0] = CC_OSZAPC,
6257
[INDEX_op_movw_eflags_T0_io] = CC_OSZAPC,
6258
[INDEX_op_movl_eflags_T0_io] = CC_OSZAPC,
6259
[INDEX_op_movw_eflags_T0_cpl0] = CC_OSZAPC,
6260
[INDEX_op_movl_eflags_T0_cpl0] = CC_OSZAPC,
6261
[INDEX_op_clc] = CC_C,
6262
[INDEX_op_stc] = CC_C,
6263
[INDEX_op_cmc] = CC_C,
6264
6265
[INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
6266
[INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
6267
X86_64_DEF([INDEX_op_btq_T0_T1_cc] = CC_OSZAPC,)
6268
[INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
6269
[INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
6270
X86_64_DEF([INDEX_op_btsq_T0_T1_cc] = CC_OSZAPC,)
6271
[INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
6272
[INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
6273
X86_64_DEF([INDEX_op_btrq_T0_T1_cc] = CC_OSZAPC,)
6274
[INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
6275
[INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
6276
X86_64_DEF([INDEX_op_btcq_T0_T1_cc] = CC_OSZAPC,)
6277
6278
[INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
6279
[INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
6280
X86_64_DEF([INDEX_op_bsfq_T0_cc] = CC_OSZAPC,)
6281
[INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
6282
[INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
6283
X86_64_DEF([INDEX_op_bsrq_T0_cc] = CC_OSZAPC,)
6284
6285
[INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
6286
[INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
6287
[INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
6288
X86_64_DEF([INDEX_op_cmpxchgq_T0_T1_EAX_cc] = CC_OSZAPC,)
6289
6290
[INDEX_op_cmpxchg8b] = CC_Z,
6291
[INDEX_op_lar] = CC_Z,
6292
[INDEX_op_lsl] = CC_Z,
6293
[INDEX_op_verr] = CC_Z,
6294
[INDEX_op_verw] = CC_Z,
6295
[INDEX_op_fcomi_ST0_FT0] = CC_Z | CC_P | CC_C,
6296
[INDEX_op_fucomi_ST0_FT0] = CC_Z | CC_P | CC_C,
6297
6298
#define DEF_WRITEF(SUFFIX)\
6299
[INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6300
[INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6301
[INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6302
X86_64_DEF([INDEX_op_adcq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6303
[INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6304
[INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6305
[INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6306
X86_64_DEF([INDEX_op_sbbq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6307
\
6308
[INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6309
[INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6310
[INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6311
X86_64_DEF([INDEX_op_rolq ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,)\
6312
[INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6313
[INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6314
[INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6315
X86_64_DEF([INDEX_op_rorq ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,)\
6316
\
6317
[INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6318
[INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6319
[INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6320
X86_64_DEF([INDEX_op_rclq ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,)\
6321
[INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6322
[INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6323
[INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
6324
X86_64_DEF([INDEX_op_rcrq ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,)\
6325
\
6326
[INDEX_op_shlb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6327
[INDEX_op_shlw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6328
[INDEX_op_shll ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6329
X86_64_DEF([INDEX_op_shlq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6330
\
6331
[INDEX_op_shrb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6332
[INDEX_op_shrw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6333
[INDEX_op_shrl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6334
X86_64_DEF([INDEX_op_shrq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6335
\
6336
[INDEX_op_sarb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6337
[INDEX_op_sarw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6338
[INDEX_op_sarl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
6339
X86_64_DEF([INDEX_op_sarq ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,)\
6340
\
6341
[INDEX_op_shldw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6342
[INDEX_op_shldl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6343
X86_64_DEF([INDEX_op_shldq ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,)\
6344
[INDEX_op_shldw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6345
[INDEX_op_shldl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6346
X86_64_DEF([INDEX_op_shldq ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,)\
6347
\
6348
[INDEX_op_shrdw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6349
[INDEX_op_shrdl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
6350
X86_64_DEF([INDEX_op_shrdq ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,)\
6351
[INDEX_op_shrdw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6352
[INDEX_op_shrdl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
6353
X86_64_DEF([INDEX_op_shrdq ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,)\
6354
\
6355
[INDEX_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6356
[INDEX_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6357
[INDEX_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
6358
X86_64_DEF([INDEX_op_cmpxchgq ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,)
6359
6360
6361
DEF_WRITEF( )
6362
DEF_WRITEF(_raw)
6363
#ifndef CONFIG_USER_ONLY
6364
DEF_WRITEF(_kernel)
6365
DEF_WRITEF(_user)
6366
#endif
6367
};
6368
6369
/* simpler form of an operation if no flags need to be generated */
6370
static uint16_t opc_simpler[NB_OPS] = {
6371
[INDEX_op_update2_cc] = INDEX_op_nop,
6372
[INDEX_op_update1_cc] = INDEX_op_nop,
6373
[INDEX_op_update_neg_cc] = INDEX_op_nop,
6374
#if 0
6375
/* broken: CC_OP logic must be rewritten */
6376
[INDEX_op_update_inc_cc] = INDEX_op_nop,
6377
#endif
6378
6379
[INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
6380
[INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
6381
[INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
6382
X86_64_DEF([INDEX_op_shlq_T0_T1_cc] = INDEX_op_shlq_T0_T1,)
6383
6384
[INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
6385
[INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
6386
[INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
6387
X86_64_DEF([INDEX_op_shrq_T0_T1_cc] = INDEX_op_shrq_T0_T1,)
6388
6389
[INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
6390
[INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
6391
[INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
6392
X86_64_DEF([INDEX_op_sarq_T0_T1_cc] = INDEX_op_sarq_T0_T1,)
6393
6394
#define DEF_SIMPLER(SUFFIX)\
6395
[INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolb ## SUFFIX ## _T0_T1,\
6396
[INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolw ## SUFFIX ## _T0_T1,\
6397
[INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = INDEX_op_roll ## SUFFIX ## _T0_T1,\
6398
X86_64_DEF([INDEX_op_rolq ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolq ## SUFFIX ## _T0_T1,)\
6399
\
6400
[INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorb ## SUFFIX ## _T0_T1,\
6401
[INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorw ## SUFFIX ## _T0_T1,\
6402
[INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorl ## SUFFIX ## _T0_T1,\
6403
X86_64_DEF([INDEX_op_rorq ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorq ## SUFFIX ## _T0_T1,)
6404
6405
DEF_SIMPLER( )
6406
DEF_SIMPLER(_raw)
6407
#ifndef CONFIG_USER_ONLY
6408
DEF_SIMPLER(_kernel)
6409
DEF_SIMPLER(_user)
6410
#endif
6411
};
6412
7503
6413
void optimize_flags_init(void)
7504
6414
{
7505
#if TCG_TARGET_REG_BITS == 32
7506
assert(sizeof(CCTable) == (1 << 3));
7507
#else
7508
assert(sizeof(CCTable) == (1 << 4));
7509
#endif
7510
cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
7511
cpu_cc_op = tcg_global_mem_new(TCG_TYPE_I32,
7512
TCG_AREG0, offsetof(CPUState, cc_op), "cc_op");
7513
cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
7514
TCG_AREG0, offsetof(CPUState, cc_src), "cc_src");
7515
cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
7516
TCG_AREG0, offsetof(CPUState, cc_dst), "cc_dst");
7517
cpu_cc_tmp = tcg_global_mem_new(TCG_TYPE_TL,
7518
TCG_AREG0, offsetof(CPUState, cc_tmp), "cc_tmp");
7519
7520
/* register helpers */
7521
7522
#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
7523
#include "helper.h"
6415
int i;
6416
/* put default values in arrays */
6417
for(i = 0; i < NB_OPS; i++) {
6418
if (opc_simpler[i] == 0)
6419
opc_simpler[i] = i;
6420
}
6421
}
6422
6423
/* CPU flags computation optimization: we move backward thru the
6424
generated code to see which flags are needed. The operation is
6425
modified if suitable */
6426
static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
6427
{
6428
uint16_t *opc_ptr;
6429
int live_flags, write_flags, op;
6430
6431
opc_ptr = opc_buf + opc_buf_len;
6432
/* live_flags contains the flags needed by the next instructions
6433
in the code. At the end of the bloc, we consider that all the
6434
flags are live. */
6435
live_flags = CC_OSZAPC;
6436
while (opc_ptr > opc_buf) {
6437
op = *--opc_ptr;
6438
/* if none of the flags written by the instruction is used,
6439
then we can try to find a simpler instruction */
6440
write_flags = opc_write_flags[op];
6441
if ((live_flags & write_flags) == 0) {
6442
*opc_ptr = opc_simpler[op];
6443
}
6444
/* compute the live flags before the instruction */
6445
live_flags &= ~write_flags;
6446
live_flags |= opc_read_flags[op];
6447
}
7524
6448
}
7525
6449
7526
6450
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7527
6451
basic block 'tb'. If search_pc is TRUE, also generate PC
7528
6452
information for each intermediate instruction. */
7529
static inline void gen_intermediate_code_internal(CPUState *env,
7530
TranslationBlock *tb,
7531
int search_pc)
6453
static inline int gen_intermediate_code_internal(CPUState *env,
6454
TranslationBlock *tb,
6455
int search_pc)
7532
6456
{
7533
6457
DisasContext dc1, *dc = &dc1;
7534
6458
target_ulong pc_ptr;
7535
6459
uint16_t *gen_opc_end;
7536
int j, lj, cflags;
7537
uint64_t flags;
6460
int flags, j, lj, cflags;
7538
6461
target_ulong pc_start;
7539
6462
target_ulong cs_base;
7540
int num_insns;
7541
int max_insns;
7542
6463
7543
6464
/* generate intermediate code */
7544
6465
pc_start = tb->pc;
7545
6466
cs_base = tb->cs_base;
7570
6491
}
7571
6492
dc->cpuid_features = env->cpuid_features;
7572
6493
dc->cpuid_ext_features = env->cpuid_ext_features;
7573
dc->cpuid_ext2_features = env->cpuid_ext2_features;
7574
dc->cpuid_ext3_features = env->cpuid_ext3_features;
7575
6494
#ifdef TARGET_X86_64
7576
6495
dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7577
6496
dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7589
6508
printf("ERROR addseg\n");
7590
6509
#endif
7591
6510
7592
cpu_T[0] = tcg_temp_new(TCG_TYPE_TL);
7593
cpu_T[1] = tcg_temp_new(TCG_TYPE_TL);
7594
cpu_A0 = tcg_temp_new(TCG_TYPE_TL);
7595
cpu_T3 = tcg_temp_new(TCG_TYPE_TL);
7596
7597
cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
7598
cpu_tmp1_i64 = tcg_temp_new(TCG_TYPE_I64);
7599
cpu_tmp2_i32 = tcg_temp_new(TCG_TYPE_I32);
7600
cpu_tmp3_i32 = tcg_temp_new(TCG_TYPE_I32);
7601
cpu_tmp4 = tcg_temp_new(TCG_TYPE_TL);
7602
cpu_tmp5 = tcg_temp_new(TCG_TYPE_TL);
7603
cpu_tmp6 = tcg_temp_new(TCG_TYPE_TL);
7604
cpu_ptr0 = tcg_temp_new(TCG_TYPE_PTR);
7605
cpu_ptr1 = tcg_temp_new(TCG_TYPE_PTR);
7606
6511
gen_opc_ptr = gen_opc_buf;
7607
6512
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6513
gen_opparam_ptr = gen_opparam_buf;
6514
nb_gen_labels = 0;
7608
6515
7609
6516
dc->is_jmp = DISAS_NEXT;
7610
6517
pc_ptr = pc_start;
7611
6518
lj = -1;
7612
num_insns = 0;
7613
max_insns = tb->cflags & CF_COUNT_MASK;
7614
if (max_insns == 0)
7615
max_insns = CF_COUNT_MASK;
7616
6519
7617
gen_icount_start();
7618
6520
for(;;) {
7619
6521
if (env->nb_breakpoints > 0) {
7620
6522
for(j = 0; j < env->nb_breakpoints; j++) {
7634
6536
gen_opc_pc[lj] = pc_ptr;
7635
6537
gen_opc_cc_op[lj] = dc->cc_op;
7636
6538
gen_opc_instr_start[lj] = 1;
7637
gen_opc_icount[lj] = num_insns;
7638
6539
}
7639
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7640
gen_io_start();
7641
7642
6540
pc_ptr = disas_insn(dc, pc_ptr);
7643
num_insns++;
7644
6541
/* stop translation if indicated */
7645
6542
if (dc->is_jmp)
7646
6543
break;
7649
6546
/* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7650
6547
the flag and abort the translation to give the irqs a
7651
6548
change to be happen */
7652
if (dc->tf || dc->singlestep_enabled ||
7653
(flags & HF_INHIBIT_IRQ_MASK)) {
6549
if (dc->tf || dc->singlestep_enabled ||
6550
(flags & HF_INHIBIT_IRQ_MASK) ||
6551
(cflags & CF_SINGLE_INSN)) {
7654
6552
gen_jmp_im(pc_ptr - dc->cs_base);
7655
6553
gen_eob(dc);
7656
6554
break;
7657
6555
}
7658
6556
/* if too long translation, stop generation too */
7659
6557
if (gen_opc_ptr >= gen_opc_end ||
7660
(pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
7661
num_insns >= max_insns) {
6558
(pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
7662
6559
gen_jmp_im(pc_ptr - dc->cs_base);
7663
6560
gen_eob(dc);
7664
6561
break;
7665
6562
}
7666
6563
}
7667
if (tb->cflags & CF_LAST_IO)
7668
gen_io_end();
7669
gen_icount_end(tb, num_insns);
7670
6564
*gen_opc_ptr = INDEX_op_end;
7671
6565
/* we don't forget to fill the last values */
7672
6566
if (search_pc) {
7675
6569
while (lj <= j)
7676
6570
gen_opc_instr_start[lj++] = 0;
7677
6571
}
7678
6572
7679
6573
#ifdef DEBUG_DISAS
7680
6574
if (loglevel & CPU_LOG_TB_CPU) {
7681
6575
cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
7692
6586
disas_flags = !dc->code32;
7693
6587
target_disas(logfile, pc_start, pc_ptr - pc_start, disas_flags);
7694
6588
fprintf(logfile, "\n");
7695
}
7696
#endif
7697
7698
if (!search_pc) {
6589
if (loglevel & CPU_LOG_TB_OP) {
6590
fprintf(logfile, "OP:\n");
6591
dump_ops(gen_opc_buf, gen_opparam_buf);
6592
fprintf(logfile, "\n");
6593
}
6594
}
6595
#endif
6596
6597
/* optimize flag computations */
6598
optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
6599
6600
#ifdef DEBUG_DISAS
6601
if (loglevel & CPU_LOG_TB_OP_OPT) {
6602
fprintf(logfile, "AFTER FLAGS OPT:\n");
6603
dump_ops(gen_opc_buf, gen_opparam_buf);
6604
fprintf(logfile, "\n");
6605
}
6606
#endif
6607
if (!search_pc)
7699
6608
tb->size = pc_ptr - pc_start;
7700
tb->icount = num_insns;
7701
}
7702
}
7703
7704
void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
7705
{
7706
gen_intermediate_code_internal(env, tb, 0);
7707
}
7708
7709
void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
7710
{
7711
gen_intermediate_code_internal(env, tb, 1);
7712
}
7713
7714
void gen_pc_load(CPUState *env, TranslationBlock *tb,
7715
unsigned long searched_pc, int pc_pos, void *puc)
7716
{
7717
int cc_op;
7718
#ifdef DEBUG_DISAS
7719
if (loglevel & CPU_LOG_TB_OP) {
7720
int i;
7721
fprintf(logfile, "RESTORE:\n");
7722
for(i = 0;i <= pc_pos; i++) {
7723
if (gen_opc_instr_start[i]) {
7724
fprintf(logfile, "0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
7725
}
7726
}
7727
fprintf(logfile, "spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
7728
searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
7729
(uint32_t)tb->cs_base);
7730
}
7731
#endif
7732
env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
7733
cc_op = gen_opc_cc_op[pc_pos];
7734
if (cc_op != CC_OP_DYNAMIC)
7735
env->cc_op = cc_op;
7736
}
6609
return 0;
6610
}
6611
6612
int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
6613
{
6614
return gen_intermediate_code_internal(env, tb, 0);
6615
}
6616
6617
int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
6618
{
6619
return gen_intermediate_code_internal(env, tb, 1);
6620
}
6621
Loggerhead is a web-based interface for Breezy
Version: 2.0.1