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  • Committer: ths
  • Date: 2007-06-17 15:32:30 UTC
  • Revision ID: git-v1:ffb04fcf089865952592f1f8855c2848d4514a89
Allow relative paths for the interpreter prefix in linux-user emulation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2984 c046a42c-6fe2-441c-8c8c-71466251a162

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hw/piix_pci.c
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 * QEMU i440FX/PIIX3 PCI Bridge Emulation
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 *
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 * Copyright (c) 2006 Fabrice Bellard
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 *
 
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 * 
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * THE SOFTWARE.
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 */
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#include "hw.h"
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#include "pc.h"
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#include "pci.h"
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#include "vl.h"
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typedef uint32_t pci_addr_t;
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#include "pci_host.h"
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    return (irq_num + slot_addend) & 3;
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}
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static target_phys_addr_t isa_page_descs[384 / 4];
 
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static uint32_t isa_page_descs[384 / 4];
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static uint8_t smm_enabled;
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static int pci_irq_levels[4];
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static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
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{
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    switch(r) {
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    case 3:
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        /* RAM */
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        cpu_register_physical_memory(start, end - start,
 
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        cpu_register_physical_memory(start, end - start, 
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                                     start);
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        break;
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    case 1:
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        /* ROM (XXX: not quite correct) */
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        cpu_register_physical_memory(start, end - start,
 
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        cpu_register_physical_memory(start, end - start, 
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                                     start | IO_MEM_ROM);
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        break;
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    case 2:
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    case 0:
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        /* XXX: should distinguish read/write cases */
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        for(addr = start; addr < end; addr += 4096) {
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            cpu_register_physical_memory(addr, 4096,
 
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            cpu_register_physical_memory(addr, 4096, 
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                                         isa_page_descs[(addr - 0xa0000) >> 12]);
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        }
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        break;
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        cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
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    } else {
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        for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
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            cpu_register_physical_memory(addr, 4096,
 
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            cpu_register_physical_memory(addr, 4096, 
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                                         isa_page_descs[(addr - 0xa0000) >> 12]);
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        }
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    }
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    }
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}
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static void i440fx_write_config(PCIDevice *d,
 
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static void i440fx_write_config(PCIDevice *d, 
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                                uint32_t address, uint32_t val, int len)
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{
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    /* XXX: implement SMRAM.D_LOCK */
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static void i440fx_save(QEMUFile* f, void *opaque)
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{
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    PCIDevice *d = opaque;
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    int i;
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    pci_device_save(d, f);
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    qemu_put_8s(f, &smm_enabled);
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    for (i = 0; i < 4; i++)
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        qemu_put_be32(f, pci_irq_levels[i]);
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}
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static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
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{
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    PCIDevice *d = opaque;
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    int ret, i;
 
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    int ret;
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    if (version_id > 2)
 
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    if (version_id != 1)
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        return -EINVAL;
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    ret = pci_device_load(d, f);
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    if (ret < 0)
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        return ret;
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    i440fx_update_memory_mappings(d);
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    qemu_get_8s(f, &smm_enabled);
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    if (version_id >= 2)
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        for (i = 0; i < 4; i++)
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            pci_irq_levels[i] = qemu_get_be32(f);
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    return 0;
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}
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    register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
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    register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
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    d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
 
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    d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0, 
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                            NULL, i440fx_write_config);
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    d->config[0x00] = 0x86; // vendor_id
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    d->config[0x72] = 0x02; /* SMRAM */
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    register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
 
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    register_savevm("I440FX", 0, 1, i440fx_save, i440fx_load, d);
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    *pi440fx_state = d;
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    return b;
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}
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/* PIIX3 PCI to ISA bridge */
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static PCIDevice *piix3_dev;
 
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PCIDevice *piix3_dev;
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PCIDevice *piix4_dev;
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/* just used for simpler irq handling. */
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#define PCI_IRQ_WORDS   ((PCI_DEVICES_MAX + 31) / 32)
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static int pci_irq_levels[4];
 
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static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
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{
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    int i, pic_irq, pic_level;
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    pci_conf[0x4e] = 0x03;
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    pci_conf[0x4f] = 0x00;
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    pci_conf[0x60] = 0x80;
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    pci_conf[0x61] = 0x80;
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    pci_conf[0x62] = 0x80;
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    pci_conf[0x63] = 0x80;
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    pci_conf[0x69] = 0x02;
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    pci_conf[0x70] = 0x80;
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    pci_conf[0x76] = 0x0c;
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    return pci_device_load(d, f);
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}
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312
 
 
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int piix_init(PCIBus *bus, int devfn)
 
314
{
 
315
    PCIDevice *d;
 
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    uint8_t *pci_conf;
 
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    d = pci_register_device(bus, "PIIX", sizeof(PCIDevice),
 
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                                    devfn, NULL, NULL);
 
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    register_savevm("PIIX", 0, 2, piix_save, piix_load, d);
 
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    piix3_dev = d;
 
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    pci_conf = d->config;
 
324
 
 
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    pci_conf[0x00] = 0x86; // Intel
 
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    pci_conf[0x01] = 0x80;
 
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    pci_conf[0x02] = 0x2E; // 82371FB PIIX PCI-to-ISA bridge
 
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    pci_conf[0x03] = 0x12;
 
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    pci_conf[0x08] = 0x02; // Step A1
 
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    pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
 
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    pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
 
332
    pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
 
333
 
 
334
    piix3_reset(d);
 
335
    return d->devfn;
 
336
}
 
337
 
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int piix3_init(PCIBus *bus, int devfn)
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{
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    PCIDevice *d;