57
51
#define bfd_mach_m68030 5
58
52
#define bfd_mach_m68040 6
59
53
#define bfd_mach_m68060 7
60
#define bfd_mach_cpu32 8
61
#define bfd_mach_mcf5200 9
62
#define bfd_mach_mcf5206e 10
63
#define bfd_mach_mcf5307 11
64
#define bfd_mach_mcf5407 12
65
#define bfd_mach_mcf528x 13
66
#define bfd_mach_mcfv4e 14
67
#define bfd_mach_mcf521x 15
68
#define bfd_mach_mcf5249 16
69
#define bfd_mach_mcf547x 17
70
#define bfd_mach_mcf548x 18
71
bfd_arch_vax, /* DEC Vax */
54
bfd_arch_vax, /* DEC Vax */
72
55
bfd_arch_i960, /* Intel 960 */
73
56
/* The order of the following is important.
74
lower number indicates a machine type that
57
lower number indicates a machine type that
75
58
only accepts a subset of the instructions
76
59
available to machines with higher numbers.
77
60
The exception is the "ca", which is
78
incompatible with all other machines except
61
incompatible with all other machines except
81
64
#define bfd_mach_i960_core 1
122
105
bfd_arch_i386, /* Intel 386 */
123
106
#define bfd_mach_i386_i386 0
124
107
#define bfd_mach_i386_i8086 1
125
#define bfd_mach_i386_i386_intel_syntax 2
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#define bfd_mach_x86_64 3
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#define bfd_mach_x86_64_intel_syntax 4
128
108
bfd_arch_we32k, /* AT&T WE32xxx */
129
109
bfd_arch_tahoe, /* CCI/Harris Tahoe */
130
110
bfd_arch_i860, /* Intel 860 */
138
118
#define bfd_mach_h8300h 2
139
119
#define bfd_mach_h8300s 3
140
120
bfd_arch_powerpc, /* PowerPC */
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#define bfd_mach_ppc 0
142
#define bfd_mach_ppc64 1
143
#define bfd_mach_ppc_403 403
144
#define bfd_mach_ppc_403gc 4030
145
#define bfd_mach_ppc_505 505
146
#define bfd_mach_ppc_601 601
147
#define bfd_mach_ppc_602 602
148
#define bfd_mach_ppc_603 603
149
#define bfd_mach_ppc_ec603e 6031
150
#define bfd_mach_ppc_604 604
151
#define bfd_mach_ppc_620 620
152
#define bfd_mach_ppc_630 630
153
#define bfd_mach_ppc_750 750
154
#define bfd_mach_ppc_860 860
155
#define bfd_mach_ppc_a35 35
156
#define bfd_mach_ppc_rs64ii 642
157
#define bfd_mach_ppc_rs64iii 643
158
#define bfd_mach_ppc_7400 7400
159
121
bfd_arch_rs6000, /* IBM RS/6000 */
160
122
bfd_arch_hppa, /* HP PA RISC */
161
#define bfd_mach_hppa10 10
162
#define bfd_mach_hppa11 11
163
#define bfd_mach_hppa20 20
164
#define bfd_mach_hppa20w 25
165
123
bfd_arch_d10v, /* Mitsubishi D10V */
166
124
bfd_arch_z8k, /* Zilog Z8000 */
167
125
#define bfd_mach_z8001 1
168
126
#define bfd_mach_z8002 2
169
127
bfd_arch_h8500, /* Hitachi H8/500 */
170
128
bfd_arch_sh, /* Hitachi SH */
171
#define bfd_mach_sh 1
172
#define bfd_mach_sh2 0x20
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#define bfd_mach_sh_dsp 0x2d
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#define bfd_mach_sh2a 0x2a
175
#define bfd_mach_sh2a_nofpu 0x2b
176
#define bfd_mach_sh2e 0x2e
129
#define bfd_mach_sh 0
177
130
#define bfd_mach_sh3 0x30
178
#define bfd_mach_sh3_nommu 0x31
179
#define bfd_mach_sh3_dsp 0x3d
180
131
#define bfd_mach_sh3e 0x3e
181
132
#define bfd_mach_sh4 0x40
182
#define bfd_mach_sh4_nofpu 0x41
183
#define bfd_mach_sh4_nommu_nofpu 0x42
184
#define bfd_mach_sh4a 0x4a
185
#define bfd_mach_sh4a_nofpu 0x4b
186
#define bfd_mach_sh4al_dsp 0x4d
187
#define bfd_mach_sh5 0x50
188
133
bfd_arch_alpha, /* Dec Alpha */
189
#define bfd_mach_alpha 1
190
134
bfd_arch_arm, /* Advanced Risc Machines ARM */
191
#define bfd_mach_arm_unknown 0
192
#define bfd_mach_arm_2 1
193
#define bfd_mach_arm_2a 2
194
#define bfd_mach_arm_3 3
195
#define bfd_mach_arm_3M 4
196
#define bfd_mach_arm_4 5
197
#define bfd_mach_arm_4T 6
198
#define bfd_mach_arm_5 7
199
#define bfd_mach_arm_5T 8
200
#define bfd_mach_arm_5TE 9
201
#define bfd_mach_arm_XScale 10
202
#define bfd_mach_arm_ep9312 11
203
#define bfd_mach_arm_iWMMXt 12
204
#define bfd_mach_arm_iWMMXt2 13
135
#define bfd_mach_arm_2 1
136
#define bfd_mach_arm_2a 2
137
#define bfd_mach_arm_3 3
138
#define bfd_mach_arm_3M 4
139
#define bfd_mach_arm_4 5
140
#define bfd_mach_arm_4T 6
205
141
bfd_arch_ns32k, /* National Semiconductors ns32000 */
206
142
bfd_arch_w65, /* WDC 65816 */
207
143
bfd_arch_tic30, /* Texas Instruments TMS320C30 */
213
149
#define bfd_mach_m32r 0 /* backwards compatibility */
214
150
bfd_arch_mn10200, /* Matsushita MN10200 */
215
151
bfd_arch_mn10300, /* Matsushita MN10300 */
216
bfd_arch_cris, /* Axis CRIS */
217
#define bfd_mach_cris_v0_v10 255
218
#define bfd_mach_cris_v32 32
219
#define bfd_mach_cris_v10_v32 1032
222
#define bfd_mach_s390_31 31
223
#define bfd_mach_s390_64 64
225
155
typedef struct symbol_cache_entry
441
369
/* Call this macro to initialize only the internal variables for the
442
370
disassembler. Architecture dependent things such as byte order, or machine
443
371
variant are not touched by this macro. This makes things much easier for
444
GDB which must initialize these things separately. */
372
GDB which must initialize these things seperatly. */
446
374
#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
447
375
(INFO).fprintf_func = (FPRINTF_FUNC), \
448
376
(INFO).stream = (STREAM), \
449
377
(INFO).symbols = NULL, \
450
378
(INFO).num_symbols = 0, \
451
(INFO).private_data = NULL, \
452
379
(INFO).buffer = NULL, \
453
380
(INFO).buffer_vma = 0, \
454
381
(INFO).buffer_length = 0, \