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* QEMU 8253/8254 interval timer emulation
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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#include "qemu-timer.h"
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#define RW_STATE_LSB 1
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#define RW_STATE_MSB 2
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#define RW_STATE_WORD0 3
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#define RW_STATE_WORD1 4
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typedef struct PITChannelState {
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int count; /* can be 65536 */
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uint16_t latched_count;
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uint8_t count_latched;
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uint8_t status_latched;
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uint8_t bcd; /* not supported */
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uint8_t gate; /* timer start */
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int64_t count_load_time;
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int64_t next_transition_time;
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PITChannelState channels[3];
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static PITState pit_state;
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
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static int pit_get_count(PITChannelState *s)
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d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec);
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counter = (s->count - d) & 0xffff;
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/* XXX: may be incorrect for odd counts */
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counter = s->count - ((2 * d) % s->count);
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counter = s->count - (d % s->count);
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/* get pit output bit */
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static int pit_get_out1(PITChannelState *s, int64_t current_time)
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
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out = (d >= s->count);
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out = (d < s->count);
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if ((d % s->count) == 0 && d != 0)
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out = (d % s->count) < ((s->count + 1) >> 1);
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out = (d == s->count);
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int pit_get_out(PITState *pit, int channel, int64_t current_time)
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PITChannelState *s = &pit->channels[channel];
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return pit_get_out1(s, current_time);
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/* return -1 if no transition will occur. */
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static int64_t pit_get_next_transition_time(PITChannelState *s,
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int64_t current_time)
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uint64_t d, next_time, base;
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
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next_time = s->count;
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base = (d / s->count) * s->count;
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if ((d - base) == 0 && d != 0)
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next_time = base + s->count;
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next_time = base + s->count + 1;
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base = (d / s->count) * s->count;
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period2 = ((s->count + 1) >> 1);
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if ((d - base) < period2)
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next_time = base + period2;
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next_time = base + s->count;
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next_time = s->count;
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else if (d == s->count)
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next_time = s->count + 1;
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/* convert to timer units */
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next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ);
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/* fix potential rounding problems */
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/* XXX: better solution: use a clock at PIT_FREQ Hz */
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if (next_time <= current_time)
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next_time = current_time + 1;
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/* val must be 0 or 1 */
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void pit_set_gate(PITState *pit, int channel, int val)
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PITChannelState *s = &pit->channels[channel];
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/* XXX: just disable/enable counting */
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/* restart counting on rising edge */
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s->count_load_time = qemu_get_clock(vm_clock);
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pit_irq_timer_update(s, s->count_load_time);
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/* restart counting on rising edge */
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s->count_load_time = qemu_get_clock(vm_clock);
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pit_irq_timer_update(s, s->count_load_time);
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/* XXX: disable/enable counting */
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int pit_get_gate(PITState *pit, int channel)
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PITChannelState *s = &pit->channels[channel];
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int pit_get_initial_count(PITState *pit, int channel)
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PITChannelState *s = &pit->channels[channel];
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int pit_get_mode(PITState *pit, int channel)
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PITChannelState *s = &pit->channels[channel];
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static inline void pit_load_count(PITChannelState *s, int val)
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s->count_load_time = qemu_get_clock(vm_clock);
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pit_irq_timer_update(s, s->count_load_time);
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/* if already latched, do not latch again */
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static void pit_latch_count(PITChannelState *s)
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if (!s->count_latched) {
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s->latched_count = pit_get_count(s);
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s->count_latched = s->rw_mode;
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static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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PITState *pit = opaque;
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/* read back command */
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for(channel = 0; channel < 3; channel++) {
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s = &pit->channels[channel];
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if (val & (2 << channel)) {
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if (!(val & 0x10) && !s->status_latched) {
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/* XXX: add BCD and null count */
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s->status = (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) |
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s->status_latched = 1;
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s = &pit->channels[channel];
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access = (val >> 4) & 3;
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s->read_state = access;
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s->write_state = access;
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s->mode = (val >> 1) & 7;
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/* XXX: update irq timer ? */
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s = &pit->channels[addr];
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switch(s->write_state) {
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pit_load_count(s, val);
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pit_load_count(s, val << 8);
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s->write_latch = val;
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s->write_state = RW_STATE_WORD1;
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pit_load_count(s, s->write_latch | (val << 8));
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s->write_state = RW_STATE_WORD0;
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static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
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PITState *pit = opaque;
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s = &pit->channels[addr];
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if (s->status_latched) {
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s->status_latched = 0;
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} else if (s->count_latched) {
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switch(s->count_latched) {
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ret = s->latched_count & 0xff;
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s->count_latched = 0;
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ret = s->latched_count >> 8;
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s->count_latched = 0;
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ret = s->latched_count & 0xff;
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s->count_latched = RW_STATE_MSB;
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switch(s->read_state) {
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count = pit_get_count(s);
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count = pit_get_count(s);
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ret = (count >> 8) & 0xff;
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count = pit_get_count(s);
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s->read_state = RW_STATE_WORD1;
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count = pit_get_count(s);
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ret = (count >> 8) & 0xff;
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s->read_state = RW_STATE_WORD0;
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
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expire_time = pit_get_next_transition_time(s, current_time);
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irq_level = pit_get_out1(s, current_time);
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qemu_set_irq(s->irq, irq_level);
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printf("irq_level=%d next_delay=%f\n",
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(double)(expire_time - current_time) / ticks_per_sec);
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s->next_transition_time = expire_time;
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if (expire_time != -1)
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qemu_mod_timer(s->irq_timer, expire_time);
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qemu_del_timer(s->irq_timer);
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static void pit_irq_timer(void *opaque)
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PITChannelState *s = opaque;
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pit_irq_timer_update(s, s->next_transition_time);
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static void pit_save(QEMUFile *f, void *opaque)
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PITState *pit = opaque;
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for(i = 0; i < 3; i++) {
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s = &pit->channels[i];
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qemu_put_be32(f, s->count);
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qemu_put_be16s(f, &s->latched_count);
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qemu_put_8s(f, &s->count_latched);
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qemu_put_8s(f, &s->status_latched);
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qemu_put_8s(f, &s->status);
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qemu_put_8s(f, &s->read_state);
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qemu_put_8s(f, &s->write_state);
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qemu_put_8s(f, &s->write_latch);
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qemu_put_8s(f, &s->rw_mode);
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qemu_put_8s(f, &s->mode);
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qemu_put_8s(f, &s->bcd);
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qemu_put_8s(f, &s->gate);
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qemu_put_be64(f, s->count_load_time);
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qemu_put_be64(f, s->next_transition_time);
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qemu_put_timer(f, s->irq_timer);
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static int pit_load(QEMUFile *f, void *opaque, int version_id)
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PITState *pit = opaque;
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for(i = 0; i < 3; i++) {
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s = &pit->channels[i];
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s->count=qemu_get_be32(f);
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qemu_get_be16s(f, &s->latched_count);
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qemu_get_8s(f, &s->count_latched);
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qemu_get_8s(f, &s->status_latched);
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qemu_get_8s(f, &s->status);
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qemu_get_8s(f, &s->read_state);
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qemu_get_8s(f, &s->write_state);
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qemu_get_8s(f, &s->write_latch);
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qemu_get_8s(f, &s->rw_mode);
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qemu_get_8s(f, &s->mode);
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qemu_get_8s(f, &s->bcd);
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qemu_get_8s(f, &s->gate);
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s->count_load_time=qemu_get_be64(f);
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s->next_transition_time=qemu_get_be64(f);
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qemu_get_timer(f, s->irq_timer);
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static void pit_reset(void *opaque)
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PITState *pit = opaque;
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for(i = 0;i < 3; i++) {
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s = &pit->channels[i];
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pit_load_count(s, 0);
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PITState *pit_init(int base, qemu_irq irq)
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PITState *pit = &pit_state;
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s = &pit->channels[0];
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/* the timer 0 is connected to an IRQ */
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s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
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register_savevm("i8254", base, 1, pit_save, pit_load, pit);
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qemu_register_reset(pit_reset, pit);
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register_ioport_write(base, 4, 1, pit_ioport_write, pit);
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register_ioport_read(base, 3, 1, pit_ioport_read, pit);
added
removed
hw/i8254.c
