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- Committer: ths
- Date: 2007-10-08 12:45:38 UTC
- Revision ID: git-v1:450d4ff553af32fc9d83fef20d7106b0151526b8
CRIS disassembler, originally from binutils, by Edgar E. Iglesias.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3356 c046a42c-6fe2-441c-8c8c-71466251a162
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3356 c046a42c-6fe2-441c-8c8c-71466251a162
- files added:
- .cvsignore
- linux-user/ppc64
- target-arm/nwfpe
- files removed:
- .gitignore
- bsd-user
- bsd-user/freebsd
- bsd-user/netbsd
- bsd-user/openbsd
- bsd-user/sparc
- bsd-user/sparc64
- gdb-xml
- linux-user/arm/nwfpe
- linux-user/cris
- tcg
- tcg/arm
- tcg/hppa
- tcg/i386
- tcg/ppc
- tcg/ppc64
- tcg/sparc
- tcg/x86_64
- tests/alpha
- tests/cris
- files modified:
- COPYING
added
removed
target-ppc/translate.c
26
26
#include "cpu.h"
27
27
#include "exec-all.h"
28
28
#include "disas.h"
29
#include "helper.h"
30
#include "tcg-op.h"
31
#include "qemu-common.h"
32
33
#define CPU_SINGLE_STEP 0x1
34
#define CPU_BRANCH_STEP 0x2
35
#define GDBSTUB_SINGLE_STEP 0x4
36
29
37
30
/* Include definitions for instructions classes and implementations flags */
38
31
//#define DO_SINGLE_STEP
39
32
//#define PPC_DEBUG_DISAS
33
//#define DEBUG_MEMORY_ACCESSES
40
34
//#define DO_PPC_STATISTICS
41
//#define OPTIMIZE_FPRF_UPDATE
42
35
43
36
/*****************************************************************************/
44
37
/* Code translation helpers */
45
46
/* global register indexes */
47
static TCGv cpu_env;
48
static char cpu_reg_names[10*3 + 22*4 /* GPR */
49
#if !defined(TARGET_PPC64)
50
+ 10*4 + 22*5 /* SPE GPRh */
51
#endif
52
+ 10*4 + 22*5 /* FPR */
53
+ 2*(10*6 + 22*7) /* AVRh, AVRl */
54
+ 8*5 /* CRF */];
55
static TCGv cpu_gpr[32];
56
#if !defined(TARGET_PPC64)
57
static TCGv cpu_gprh[32];
58
#endif
59
static TCGv cpu_fpr[32];
60
static TCGv cpu_avrh[32], cpu_avrl[32];
61
static TCGv cpu_crf[8];
62
static TCGv cpu_nip;
63
static TCGv cpu_ctr;
64
static TCGv cpu_lr;
65
static TCGv cpu_xer;
66
static TCGv cpu_fpscr;
67
68
/* dyngen register indexes */
69
static TCGv cpu_T[3];
70
#if defined(TARGET_PPC64)
71
#define cpu_T64 cpu_T
72
#else
73
static TCGv cpu_T64[3];
74
#endif
75
static TCGv cpu_FT[3];
76
static TCGv cpu_AVRh[3], cpu_AVRl[3];
77
78
#include "gen-icount.h"
79
80
void ppc_translate_init(void)
81
{
82
int i;
83
char* p;
84
static int done_init = 0;
85
86
if (done_init)
87
return;
88
89
cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
90
#if TARGET_LONG_BITS > HOST_LONG_BITS
91
cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
92
TCG_AREG0, offsetof(CPUState, t0), "T0");
93
cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
94
TCG_AREG0, offsetof(CPUState, t1), "T1");
95
cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
96
TCG_AREG0, offsetof(CPUState, t2), "T2");
97
#else
98
cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
99
cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
100
#ifdef HOST_I386
101
/* XXX: This is a temporary workaround for i386.
102
* On i386 qemu_st32 runs out of registers.
103
* The proper fix is to remove cpu_T.
104
*/
105
cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
106
TCG_AREG0, offsetof(CPUState, t2), "T2");
107
#else
108
cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
109
#endif
110
#endif
111
#if !defined(TARGET_PPC64)
112
cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
113
TCG_AREG0, offsetof(CPUState, t0_64),
114
"T0_64");
115
cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
116
TCG_AREG0, offsetof(CPUState, t1_64),
117
"T1_64");
118
cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
119
TCG_AREG0, offsetof(CPUState, t2_64),
120
"T2_64");
121
#endif
122
123
cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
124
offsetof(CPUState, ft0), "FT0");
125
cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
126
offsetof(CPUState, ft1), "FT1");
127
cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
128
offsetof(CPUState, ft2), "FT2");
129
130
cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
131
offsetof(CPUState, avr0.u64[0]), "AVR0H");
132
cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
133
offsetof(CPUState, avr0.u64[1]), "AVR0L");
134
cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
135
offsetof(CPUState, avr1.u64[0]), "AVR1H");
136
cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
137
offsetof(CPUState, avr1.u64[1]), "AVR1L");
138
cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
139
offsetof(CPUState, avr2.u64[0]), "AVR2H");
140
cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
141
offsetof(CPUState, avr2.u64[1]), "AVR2L");
142
143
p = cpu_reg_names;
144
145
for (i = 0; i < 8; i++) {
146
sprintf(p, "crf%d", i);
147
cpu_crf[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
148
offsetof(CPUState, crf[i]), p);
149
p += 5;
150
}
151
152
for (i = 0; i < 32; i++) {
153
sprintf(p, "r%d", i);
154
cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
155
offsetof(CPUState, gpr[i]), p);
156
p += (i < 10) ? 3 : 4;
157
#if !defined(TARGET_PPC64)
158
sprintf(p, "r%dH", i);
159
cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
160
offsetof(CPUState, gprh[i]), p);
161
p += (i < 10) ? 4 : 5;
162
#endif
163
164
sprintf(p, "fp%d", i);
165
cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
166
offsetof(CPUState, fpr[i]), p);
167
p += (i < 10) ? 4 : 5;
168
169
sprintf(p, "avr%dH", i);
170
cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
171
offsetof(CPUState, avr[i].u64[0]), p);
172
p += (i < 10) ? 6 : 7;
173
174
sprintf(p, "avr%dL", i);
175
cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
176
offsetof(CPUState, avr[i].u64[1]), p);
177
p += (i < 10) ? 6 : 7;
178
}
179
180
cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
181
offsetof(CPUState, nip), "nip");
182
183
cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
184
offsetof(CPUState, ctr), "ctr");
185
186
cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
187
offsetof(CPUState, lr), "lr");
188
189
cpu_xer = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
190
offsetof(CPUState, xer), "xer");
191
192
cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
193
offsetof(CPUState, fpscr), "fpscr");
194
195
/* register helpers */
196
#undef DEF_HELPER
197
#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
198
#include "helper.h"
199
200
done_init = 1;
201
}
202
203
#if defined(OPTIMIZE_FPRF_UPDATE)
204
static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
205
static uint16_t **gen_fprf_ptr;
38
#if defined(USE_DIRECT_JUMP)
39
#define TBPARAM(x)
40
#else
41
#define TBPARAM(x) (long)(x)
42
#endif
43
44
enum {
45
#define DEF(s, n, copy_size) INDEX_op_ ## s,
46
#include "opc.h"
47
#undef DEF
48
NB_OPS,
49
};
50
51
static uint16_t *gen_opc_ptr;
52
static uint32_t *gen_opparam_ptr;
53
54
#include "gen-op.h"
55
56
static always_inline void gen_set_T0 (target_ulong val)
57
{
58
#if defined(TARGET_PPC64)
59
if (val >> 32)
60
gen_op_set_T0_64(val >> 32, val);
61
else
62
#endif
63
gen_op_set_T0(val);
64
}
65
66
static always_inline void gen_set_T1 (target_ulong val)
67
{
68
#if defined(TARGET_PPC64)
69
if (val >> 32)
70
gen_op_set_T1_64(val >> 32, val);
71
else
72
#endif
73
gen_op_set_T1(val);
74
}
75
76
#define GEN8(func, NAME) \
77
static GenOpFunc *NAME ## _table [8] = { \
78
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
79
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
80
}; \
81
static always_inline void func (int n) \
82
{ \
83
NAME ## _table[n](); \
84
}
85
86
#define GEN16(func, NAME) \
87
static GenOpFunc *NAME ## _table [16] = { \
88
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
89
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
90
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
91
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
92
}; \
93
static always_inline void func (int n) \
94
{ \
95
NAME ## _table[n](); \
96
}
97
98
#define GEN32(func, NAME) \
99
static GenOpFunc *NAME ## _table [32] = { \
100
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
101
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
102
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
103
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
104
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
105
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
106
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
107
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
108
}; \
109
static always_inline void func (int n) \
110
{ \
111
NAME ## _table[n](); \
112
}
113
114
/* Condition register moves */
115
GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
116
GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
117
GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
118
GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
119
120
/* Floating point condition and status register moves */
121
GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
122
GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
123
GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
124
static always_inline void gen_op_store_T0_fpscri (int n, uint8_t param)
125
{
126
gen_op_set_T0(param);
127
gen_op_store_T0_fpscr(n);
128
}
129
130
/* General purpose registers moves */
131
GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
132
GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
133
GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
134
135
GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
136
GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
137
#if 0 // unused
138
GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
139
#endif
140
141
/* floating point registers moves */
142
GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
143
GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
144
GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
145
GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
146
GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
147
#if 0 // unused
148
GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
206
149
#endif
207
150
208
151
/* internal defines */
222
165
#endif
223
166
int fpu_enabled;
224
167
int altivec_enabled;
168
#if defined(TARGET_PPCEMB)
225
169
int spe_enabled;
170
#endif
226
171
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
227
172
int singlestep_enabled;
228
173
int dcache_line_size;
236
181
/* handler */
237
182
void (*handler)(DisasContext *ctx);
238
183
#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
239
const char *oname;
184
const unsigned char *oname;
240
185
#endif
241
186
#if defined(DO_PPC_STATISTICS)
242
187
uint64_t count;
243
188
#endif
244
189
};
245
190
246
static always_inline void gen_reset_fpstatus (void)
247
{
248
#ifdef CONFIG_SOFTFLOAT
249
gen_op_reset_fpstatus();
250
#endif
251
}
252
253
static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
254
{
255
if (set_fprf != 0) {
256
/* This case might be optimized later */
257
#if defined(OPTIMIZE_FPRF_UPDATE)
258
*gen_fprf_ptr++ = gen_opc_ptr;
259
#endif
260
gen_op_compute_fprf(1);
261
if (unlikely(set_rc))
262
tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
263
gen_op_float_check_status();
264
} else if (unlikely(set_rc)) {
265
/* We always need to compute fpcc */
266
gen_op_compute_fprf(0);
267
tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
268
if (set_fprf)
269
gen_op_float_check_status();
270
}
271
}
272
273
static always_inline void gen_optimize_fprf (void)
274
{
275
#if defined(OPTIMIZE_FPRF_UPDATE)
276
uint16_t **ptr;
277
278
for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
279
*ptr = INDEX_op_nop1;
280
gen_fprf_ptr = gen_fprf_buf;
281
#endif
191
static always_inline void gen_set_Rc0 (DisasContext *ctx)
192
{
193
#if defined(TARGET_PPC64)
194
if (ctx->sf_mode)
195
gen_op_cmpi_64(0);
196
else
197
#endif
198
gen_op_cmpi(0);
199
gen_op_set_Rc0();
282
200
}
283
201
284
202
static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
285
203
{
286
204
#if defined(TARGET_PPC64)
287
205
if (ctx->sf_mode)
288
tcg_gen_movi_tl(cpu_nip, nip);
206
gen_op_update_nip_64(nip >> 32, nip);
289
207
else
290
208
#endif
291
tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
209
gen_op_update_nip(nip);
292
210
}
293
211
294
212
#define GEN_EXCP(ctx, excp, error) \
339
257
GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
340
258
static void gen_##name (DisasContext *ctx)
341
259
342
#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
343
static void gen_##name (DisasContext *ctx); \
344
GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
345
static void gen_##name (DisasContext *ctx)
346
347
260
typedef struct opcode_t {
348
261
unsigned char opc1, opc2, opc3;
349
#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
262
#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
350
263
unsigned char pad[5];
351
264
#else
352
265
unsigned char pad[1];
353
266
#endif
354
267
opc_handler_t handler;
355
const char *oname;
268
const unsigned char *oname;
356
269
} opcode_t;
357
270
358
271
/*****************************************************************************/
421
334
EXTRACT_HELPER(CRM, 12, 8);
422
335
EXTRACT_HELPER(FM, 17, 8);
423
336
EXTRACT_HELPER(SR, 16, 4);
424
EXTRACT_HELPER(FPIMM, 12, 4);
337
EXTRACT_HELPER(FPIMM, 20, 4);
425
338
426
339
/*** Jump target decoding ***/
427
340
/* Displacement */
451
364
452
365
#if defined(TARGET_PPC64)
453
366
if (likely(start == 0)) {
454
ret = UINT64_MAX << (63 - end);
367
ret = (uint64_t)(-1ULL) << (63 - end);
455
368
} else if (likely(end == 63)) {
456
ret = UINT64_MAX >> start;
369
ret = (uint64_t)(-1ULL) >> start;
457
370
}
458
371
#else
459
372
if (likely(start == 0)) {
460
ret = UINT32_MAX << (31 - end);
373
ret = (uint32_t)(-1ULL) << (31 - end);
461
374
} else if (likely(end == 31)) {
462
ret = UINT32_MAX >> start;
375
ret = (uint32_t)(-1ULL) >> start;
463
376
}
464
377
#endif
465
378
else {
475
388
/*****************************************************************************/
476
389
/* PowerPC Instructions types definitions */
477
390
enum {
478
PPC_NONE = 0x0000000000000000ULL,
391
PPC_NONE = 0x0000000000000000ULL,
479
392
/* PowerPC base instructions set */
480
PPC_INSNS_BASE = 0x0000000000000001ULL,
481
/* integer operations instructions */
393
PPC_INSNS_BASE = 0x0000000000000001ULL,
394
/* integer operations instructions */
482
395
#define PPC_INTEGER PPC_INSNS_BASE
483
/* flow control instructions */
396
/* flow control instructions */
484
397
#define PPC_FLOW PPC_INSNS_BASE
485
/* virtual memory instructions */
398
/* virtual memory instructions */
486
399
#define PPC_MEM PPC_INSNS_BASE
487
/* ld/st with reservation instructions */
400
/* ld/st with reservation instructions */
488
401
#define PPC_RES PPC_INSNS_BASE
489
/* spr/msr access instructions */
402
/* cache control instructions */
403
#define PPC_CACHE PPC_INSNS_BASE
404
/* spr/msr access instructions */
490
405
#define PPC_MISC PPC_INSNS_BASE
491
/* Deprecated instruction sets */
492
/* Original POWER instruction set */
493
PPC_POWER = 0x0000000000000002ULL,
494
/* POWER2 instruction set extension */
495
PPC_POWER2 = 0x0000000000000004ULL,
496
/* Power RTC support */
497
PPC_POWER_RTC = 0x0000000000000008ULL,
498
/* Power-to-PowerPC bridge (601) */
499
PPC_POWER_BR = 0x0000000000000010ULL,
500
/* 64 bits PowerPC instruction set */
501
PPC_64B = 0x0000000000000020ULL,
502
/* New 64 bits extensions (PowerPC 2.0x) */
503
PPC_64BX = 0x0000000000000040ULL,
504
/* 64 bits hypervisor extensions */
505
PPC_64H = 0x0000000000000080ULL,
506
/* New wait instruction (PowerPC 2.0x) */
507
PPC_WAIT = 0x0000000000000100ULL,
508
/* Time base mftb instruction */
509
PPC_MFTB = 0x0000000000000200ULL,
510
511
/* Fixed-point unit extensions */
512
/* PowerPC 602 specific */
513
PPC_602_SPEC = 0x0000000000000400ULL,
514
/* isel instruction */
515
PPC_ISEL = 0x0000000000000800ULL,
516
/* popcntb instruction */
517
PPC_POPCNTB = 0x0000000000001000ULL,
518
/* string load / store */
519
PPC_STRING = 0x0000000000002000ULL,
520
521
/* Floating-point unit extensions */
522
/* Optional floating point instructions */
523
PPC_FLOAT = 0x0000000000010000ULL,
524
/* New floating-point extensions (PowerPC 2.0x) */
525
PPC_FLOAT_EXT = 0x0000000000020000ULL,
526
PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
527
PPC_FLOAT_FRES = 0x0000000000080000ULL,
528
PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
529
PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
530
PPC_FLOAT_FSEL = 0x0000000000400000ULL,
531
PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
532
533
/* Vector/SIMD extensions */
534
/* Altivec support */
535
PPC_ALTIVEC = 0x0000000001000000ULL,
536
/* PowerPC 2.03 SPE extension */
537
PPC_SPE = 0x0000000002000000ULL,
538
/* PowerPC 2.03 SPE floating-point extension */
539
PPC_SPEFPU = 0x0000000004000000ULL,
540
406
/* Optional floating point instructions */
407
PPC_FLOAT = 0x0000000000000002ULL,
408
PPC_FLOAT_FSQRT = 0x0000000000000004ULL,
409
PPC_FLOAT_FRES = 0x0000000000000008ULL,
410
PPC_FLOAT_FRSQRTE = 0x0000000000000010ULL,
411
PPC_FLOAT_FSEL = 0x0000000000000020ULL,
412
PPC_FLOAT_STFIWX = 0x0000000000000040ULL,
413
/* external control instructions */
414
PPC_EXTERN = 0x0000000000000080ULL,
415
/* segment register access instructions */
416
PPC_SEGMENT = 0x0000000000000100ULL,
417
/* Optional cache control instruction */
418
PPC_CACHE_DCBA = 0x0000000000000200ULL,
541
419
/* Optional memory control instructions */
542
PPC_MEM_TLBIA = 0x0000000010000000ULL,
543
PPC_MEM_TLBIE = 0x0000000020000000ULL,
544
PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
545
/* sync instruction */
546
PPC_MEM_SYNC = 0x0000000080000000ULL,
547
/* eieio instruction */
548
PPC_MEM_EIEIO = 0x0000000100000000ULL,
549
550
/* Cache control instructions */
551
PPC_CACHE = 0x0000000200000000ULL,
552
/* icbi instruction */
553
PPC_CACHE_ICBI = 0x0000000400000000ULL,
554
/* dcbz instruction with fixed cache line size */
555
PPC_CACHE_DCBZ = 0x0000000800000000ULL,
556
/* dcbz instruction with tunable cache line size */
557
PPC_CACHE_DCBZT = 0x0000001000000000ULL,
558
/* dcba instruction */
559
PPC_CACHE_DCBA = 0x0000002000000000ULL,
560
/* Freescale cache locking instructions */
561
PPC_CACHE_LOCK = 0x0000004000000000ULL,
562
563
/* MMU related extensions */
564
/* external control instructions */
565
PPC_EXTERN = 0x0000010000000000ULL,
566
/* segment register access instructions */
567
PPC_SEGMENT = 0x0000020000000000ULL,
568
/* PowerPC 6xx TLB management instructions */
569
PPC_6xx_TLB = 0x0000040000000000ULL,
570
/* PowerPC 74xx TLB management instructions */
571
PPC_74xx_TLB = 0x0000080000000000ULL,
572
/* PowerPC 40x TLB management instructions */
573
PPC_40x_TLB = 0x0000100000000000ULL,
574
/* segment register access instructions for PowerPC 64 "bridge" */
575
PPC_SEGMENT_64B = 0x0000200000000000ULL,
576
/* SLB management */
577
PPC_SLBI = 0x0000400000000000ULL,
578
420
PPC_MEM_TLBIA = 0x0000000000000400ULL,
421
PPC_MEM_TLBIE = 0x0000000000000800ULL,
422
PPC_MEM_TLBSYNC = 0x0000000000001000ULL,
423
/* eieio & sync */
424
PPC_MEM_SYNC = 0x0000000000002000ULL,
425
/* PowerPC 6xx TLB management instructions */
426
PPC_6xx_TLB = 0x0000000000004000ULL,
427
/* Altivec support */
428
PPC_ALTIVEC = 0x0000000000008000ULL,
429
/* Time base mftb instruction */
430
PPC_MFTB = 0x0000000000010000ULL,
579
431
/* Embedded PowerPC dedicated instructions */
580
PPC_WRTEE = 0x0001000000000000ULL,
432
PPC_EMB_COMMON = 0x0000000000020000ULL,
581
433
/* PowerPC 40x exception model */
582
PPC_40x_EXCP = 0x0002000000000000ULL,
434
PPC_40x_EXCP = 0x0000000000040000ULL,
435
/* PowerPC 40x TLB management instructions */
436
PPC_40x_TLB = 0x0000000000080000ULL,
583
437
/* PowerPC 405 Mac instructions */
584
PPC_405_MAC = 0x0004000000000000ULL,
438
PPC_405_MAC = 0x0000000000100000ULL,
585
439
/* PowerPC 440 specific instructions */
586
PPC_440_SPEC = 0x0008000000000000ULL,
440
PPC_440_SPEC = 0x0000000000200000ULL,
441
/* Power-to-PowerPC bridge (601) */
442
PPC_POWER_BR = 0x0000000000400000ULL,
443
/* PowerPC 602 specific */
444
PPC_602_SPEC = 0x0000000000800000ULL,
445
/* Deprecated instructions */
446
/* Original POWER instruction set */
447
PPC_POWER = 0x0000000001000000ULL,
448
/* POWER2 instruction set extension */
449
PPC_POWER2 = 0x0000000002000000ULL,
450
/* Power RTC support */
451
PPC_POWER_RTC = 0x0000000004000000ULL,
452
/* 64 bits PowerPC instruction set */
453
PPC_64B = 0x0000000008000000ULL,
454
/* 64 bits hypervisor extensions */
455
PPC_64H = 0x0000000010000000ULL,
456
/* segment register access instructions for PowerPC 64 "bridge" */
457
PPC_SEGMENT_64B = 0x0000000020000000ULL,
587
458
/* BookE (embedded) PowerPC specification */
588
PPC_BOOKE = 0x0010000000000000ULL,
589
/* mfapidi instruction */
590
PPC_MFAPIDI = 0x0020000000000000ULL,
591
/* tlbiva instruction */
592
PPC_TLBIVA = 0x0040000000000000ULL,
593
/* tlbivax instruction */
594
PPC_TLBIVAX = 0x0080000000000000ULL,
459
PPC_BOOKE = 0x0000000040000000ULL,
460
/* eieio */
461
PPC_MEM_EIEIO = 0x0000000080000000ULL,
462
/* e500 vector instructions */
463
PPC_E500_VECTOR = 0x0000000100000000ULL,
595
464
/* PowerPC 4xx dedicated instructions */
596
PPC_4xx_COMMON = 0x0100000000000000ULL,
465
PPC_4xx_COMMON = 0x0000000200000000ULL,
466
/* PowerPC 2.03 specification extensions */
467
PPC_203 = 0x0000000400000000ULL,
468
/* PowerPC 2.03 SPE extension */
469
PPC_SPE = 0x0000000800000000ULL,
470
/* PowerPC 2.03 SPE floating-point extension */
471
PPC_SPEFPU = 0x0000001000000000ULL,
472
/* SLB management */
473
PPC_SLBI = 0x0000002000000000ULL,
597
474
/* PowerPC 40x ibct instructions */
598
PPC_40x_ICBT = 0x0200000000000000ULL,
475
PPC_40x_ICBT = 0x0000004000000000ULL,
476
/* PowerPC 74xx TLB management instructions */
477
PPC_74xx_TLB = 0x0000008000000000ULL,
478
/* More BookE (embedded) instructions... */
479
PPC_BOOKE_EXT = 0x0000010000000000ULL,
599
480
/* rfmci is not implemented in all BookE PowerPC */
600
PPC_RFMCI = 0x0400000000000000ULL,
601
/* rfdi instruction */
602
PPC_RFDI = 0x0800000000000000ULL,
603
/* DCR accesses */
604
PPC_DCR = 0x1000000000000000ULL,
605
/* DCR extended accesse */
606
PPC_DCRX = 0x2000000000000000ULL,
481
PPC_RFMCI = 0x0000020000000000ULL,
607
482
/* user-mode DCR access, implemented in PowerPC 460 */
608
PPC_DCRUX = 0x4000000000000000ULL,
483
PPC_DCRUX = 0x0000040000000000ULL,
484
/* New floating-point extensions (PowerPC 2.0x) */
485
PPC_FLOAT_EXT = 0x0000080000000000ULL,
486
/* New wait instruction (PowerPC 2.0x) */
487
PPC_WAIT = 0x0000100000000000ULL,
488
/* New 64 bits extensions (PowerPC 2.0x) */
489
PPC_64BX = 0x0000200000000000ULL,
490
/* dcbz instruction with fixed cache line size */
491
PPC_CACHE_DCBZ = 0x0000400000000000ULL,
492
/* dcbz instruction with tunable cache line size */
493
PPC_CACHE_DCBZT = 0x0000800000000000ULL,
609
494
};
610
495
611
496
/*****************************************************************************/
638
523
}, \
639
524
.oname = stringify(name), \
640
525
}
641
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
642
OPCODES_SECTION opcode_t opc_##name = { \
643
.opc1 = op1, \
644
.opc2 = op2, \
645
.opc3 = op3, \
646
.pad = { 0, }, \
647
.handler = { \
648
.inval = invl, \
649
.type = _typ, \
650
.handler = &gen_##name, \
651
.oname = onam, \
652
}, \
653
.oname = onam, \
654
}
655
526
#else
656
527
#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
657
528
OPCODES_SECTION opcode_t opc_##name = { \
666
537
}, \
667
538
.oname = stringify(name), \
668
539
}
669
#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
670
OPCODES_SECTION opcode_t opc_##name = { \
671
.opc1 = op1, \
672
.opc2 = op2, \
673
.opc3 = op3, \
674
.pad = { 0, }, \
675
.handler = { \
676
.inval = invl, \
677
.type = _typ, \
678
.handler = &gen_##name, \
679
}, \
680
.oname = onam, \
681
}
682
540
#endif
683
541
684
542
#define GEN_OPCODE_MARK(name) \
710
568
.handler = gen_invalid,
711
569
};
712
570
713
/*** Integer comparison ***/
714
715
static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
716
{
717
int l1, l2, l3;
718
719
tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
720
tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
721
tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
722
723
l1 = gen_new_label();
724
l2 = gen_new_label();
725
l3 = gen_new_label();
726
if (s) {
727
tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
728
tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
729
} else {
730
tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
731
tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
732
}
733
tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
734
tcg_gen_br(l3);
735
gen_set_label(l1);
736
tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
737
tcg_gen_br(l3);
738
gen_set_label(l2);
739
tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
740
gen_set_label(l3);
741
}
742
743
static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
744
{
745
TCGv t0 = tcg_const_local_tl(arg1);
746
gen_op_cmp(arg0, t0, s, crf);
747
tcg_temp_free(t0);
748
}
749
750
#if defined(TARGET_PPC64)
751
static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
752
{
753
TCGv t0, t1;
754
t0 = tcg_temp_local_new(TCG_TYPE_TL);
755
t1 = tcg_temp_local_new(TCG_TYPE_TL);
756
if (s) {
757
tcg_gen_ext32s_tl(t0, arg0);
758
tcg_gen_ext32s_tl(t1, arg1);
759
} else {
760
tcg_gen_ext32u_tl(t0, arg0);
761
tcg_gen_ext32u_tl(t1, arg1);
762
}
763
gen_op_cmp(t0, t1, s, crf);
764
tcg_temp_free(t1);
765
tcg_temp_free(t0);
766
}
767
768
static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
769
{
770
TCGv t0 = tcg_const_local_tl(arg1);
771
gen_op_cmp32(arg0, t0, s, crf);
772
tcg_temp_free(t0);
773
}
774
#endif
775
776
static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
777
{
778
#if defined(TARGET_PPC64)
779
if (!(ctx->sf_mode))
780
gen_op_cmpi32(reg, 0, 1, 0);
781
else
782
#endif
783
gen_op_cmpi(reg, 0, 1, 0);
784
}
785
786
/* cmp */
787
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
788
{
789
#if defined(TARGET_PPC64)
790
if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
791
gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
792
1, crfD(ctx->opcode));
793
else
794
#endif
795
gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
796
1, crfD(ctx->opcode));
797
}
798
799
/* cmpi */
800
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
801
{
802
#if defined(TARGET_PPC64)
803
if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
804
gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
805
1, crfD(ctx->opcode));
806
else
807
#endif
808
gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
809
1, crfD(ctx->opcode));
810
}
811
812
/* cmpl */
813
GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
814
{
815
#if defined(TARGET_PPC64)
816
if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
817
gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
818
0, crfD(ctx->opcode));
819
else
820
#endif
821
gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
822
0, crfD(ctx->opcode));
823
}
824
825
/* cmpli */
826
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
827
{
828
#if defined(TARGET_PPC64)
829
if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
830
gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
831
0, crfD(ctx->opcode));
832
else
833
#endif
834
gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
835
0, crfD(ctx->opcode));
836
}
837
838
/* isel (PowerPC 2.03 specification) */
839
GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
840
{
841
int l1, l2;
842
uint32_t bi = rC(ctx->opcode);
843
uint32_t mask;
844
TCGv t0;
845
846
l1 = gen_new_label();
847
l2 = gen_new_label();
848
849
mask = 1 << (3 - (bi & 0x03));
850
t0 = tcg_temp_new(TCG_TYPE_I32);
851
tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
852
tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
853
if (rA(ctx->opcode) == 0)
854
tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
855
else
856
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
857
tcg_gen_br(l2);
858
gen_set_label(l1);
859
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
860
gen_set_label(l2);
861
tcg_temp_free(t0);
862
}
863
864
571
/*** Integer arithmetic ***/
865
866
static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
867
{
868
int l1;
869
TCGv t0;
870
871
l1 = gen_new_label();
872
/* Start with XER OV disabled, the most likely case */
873
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
874
t0 = tcg_temp_local_new(TCG_TYPE_TL);
875
tcg_gen_xor_tl(t0, arg0, arg1);
876
#if defined(TARGET_PPC64)
877
if (!ctx->sf_mode)
878
tcg_gen_ext32s_tl(t0, t0);
879
#endif
880
if (sub)
881
tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
882
else
883
tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
884
tcg_gen_xor_tl(t0, arg1, arg2);
885
#if defined(TARGET_PPC64)
886
if (!ctx->sf_mode)
887
tcg_gen_ext32s_tl(t0, t0);
888
#endif
889
if (sub)
890
tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
891
else
892
tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
893
tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
894
gen_set_label(l1);
895
tcg_temp_free(t0);
896
}
897
898
static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
899
{
900
int l1 = gen_new_label();
901
902
#if defined(TARGET_PPC64)
903
if (!(ctx->sf_mode)) {
904
TCGv t0, t1;
905
t0 = tcg_temp_new(TCG_TYPE_TL);
906
t1 = tcg_temp_new(TCG_TYPE_TL);
907
908
tcg_gen_ext32u_tl(t0, arg1);
909
tcg_gen_ext32u_tl(t1, arg2);
910
if (sub) {
911
tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
912
} else {
913
tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
914
}
915
tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
916
gen_set_label(l1);
917
tcg_temp_free(t0);
918
tcg_temp_free(t1);
919
} else
920
#endif
921
{
922
if (sub) {
923
tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
924
} else {
925
tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
926
}
927
tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
928
gen_set_label(l1);
929
}
930
}
931
932
/* Common add function */
933
static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
934
int add_ca, int compute_ca, int compute_ov)
935
{
936
TCGv t0, t1;
937
938
if ((!compute_ca && !compute_ov) ||
939
(GET_TCGV(ret) != GET_TCGV(arg1) && GET_TCGV(ret) != GET_TCGV(arg2))) {
940
t0 = ret;
941
} else {
942
t0 = tcg_temp_local_new(TCG_TYPE_TL);
943
}
944
945
if (add_ca) {
946
t1 = tcg_temp_local_new(TCG_TYPE_TL);
947
tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
948
tcg_gen_shri_tl(t1, t1, XER_CA);
949
}
950
951
if (compute_ca && compute_ov) {
952
/* Start with XER CA and OV disabled, the most likely case */
953
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
954
} else if (compute_ca) {
955
/* Start with XER CA disabled, the most likely case */
956
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
957
} else if (compute_ov) {
958
/* Start with XER OV disabled, the most likely case */
959
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
960
}
961
962
tcg_gen_add_tl(t0, arg1, arg2);
963
964
if (compute_ca) {
965
gen_op_arith_compute_ca(ctx, t0, arg1, 0);
966
}
967
if (add_ca) {
968
tcg_gen_add_tl(t0, t0, t1);
969
gen_op_arith_compute_ca(ctx, t0, t1, 0);
970
tcg_temp_free(t1);
971
}
972
if (compute_ov) {
973
gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
974
}
975
976
if (unlikely(Rc(ctx->opcode) != 0))
977
gen_set_Rc0(ctx, t0);
978
979
if (GET_TCGV(t0) != GET_TCGV(ret)) {
980
tcg_gen_mov_tl(ret, t0);
981
tcg_temp_free(t0);
982
}
983
}
984
/* Add functions with two operands */
985
#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
986
GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
987
{ \
988
gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
989
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
990
add_ca, compute_ca, compute_ov); \
991
}
992
/* Add functions with one operand and one immediate */
993
#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
994
add_ca, compute_ca, compute_ov) \
995
GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
996
{ \
997
TCGv t0 = tcg_const_local_tl(const_val); \
998
gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
999
cpu_gpr[rA(ctx->opcode)], t0, \
1000
add_ca, compute_ca, compute_ov); \
1001
tcg_temp_free(t0); \
1002
}
1003
1004
/* add add. addo addo. */
1005
GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1006
GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1007
/* addc addc. addco addco. */
1008
GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1009
GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1010
/* adde adde. addeo addeo. */
1011
GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1012
GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
572
#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
573
GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
574
{ \
575
gen_op_load_gpr_T0(rA(ctx->opcode)); \
576
gen_op_load_gpr_T1(rB(ctx->opcode)); \
577
gen_op_##name(); \
578
gen_op_store_T0_gpr(rD(ctx->opcode)); \
579
if (unlikely(Rc(ctx->opcode) != 0)) \
580
gen_set_Rc0(ctx); \
581
}
582
583
#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
584
GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
585
{ \
586
gen_op_load_gpr_T0(rA(ctx->opcode)); \
587
gen_op_load_gpr_T1(rB(ctx->opcode)); \
588
gen_op_##name(); \
589
gen_op_store_T0_gpr(rD(ctx->opcode)); \
590
if (unlikely(Rc(ctx->opcode) != 0)) \
591
gen_set_Rc0(ctx); \
592
}
593
594
#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
595
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
596
{ \
597
gen_op_load_gpr_T0(rA(ctx->opcode)); \
598
gen_op_##name(); \
599
gen_op_store_T0_gpr(rD(ctx->opcode)); \
600
if (unlikely(Rc(ctx->opcode) != 0)) \
601
gen_set_Rc0(ctx); \
602
}
603
#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
604
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
605
{ \
606
gen_op_load_gpr_T0(rA(ctx->opcode)); \
607
gen_op_##name(); \
608
gen_op_store_T0_gpr(rD(ctx->opcode)); \
609
if (unlikely(Rc(ctx->opcode) != 0)) \
610
gen_set_Rc0(ctx); \
611
}
612
613
/* Two operands arithmetic functions */
614
#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
615
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
616
__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
617
618
/* Two operands arithmetic functions with no overflow allowed */
619
#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
620
__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
621
622
/* One operand arithmetic functions */
623
#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
624
__GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
625
__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
626
627
#if defined(TARGET_PPC64)
628
#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
629
GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
630
{ \
631
gen_op_load_gpr_T0(rA(ctx->opcode)); \
632
gen_op_load_gpr_T1(rB(ctx->opcode)); \
633
if (ctx->sf_mode) \
634
gen_op_##name##_64(); \
635
else \
636
gen_op_##name(); \
637
gen_op_store_T0_gpr(rD(ctx->opcode)); \
638
if (unlikely(Rc(ctx->opcode) != 0)) \
639
gen_set_Rc0(ctx); \
640
}
641
642
#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
643
GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
644
{ \
645
gen_op_load_gpr_T0(rA(ctx->opcode)); \
646
gen_op_load_gpr_T1(rB(ctx->opcode)); \
647
if (ctx->sf_mode) \
648
gen_op_##name##_64(); \
649
else \
650
gen_op_##name(); \
651
gen_op_store_T0_gpr(rD(ctx->opcode)); \
652
if (unlikely(Rc(ctx->opcode) != 0)) \
653
gen_set_Rc0(ctx); \
654
}
655
656
#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
657
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
658
{ \
659
gen_op_load_gpr_T0(rA(ctx->opcode)); \
660
if (ctx->sf_mode) \
661
gen_op_##name##_64(); \
662
else \
663
gen_op_##name(); \
664
gen_op_store_T0_gpr(rD(ctx->opcode)); \
665
if (unlikely(Rc(ctx->opcode) != 0)) \
666
gen_set_Rc0(ctx); \
667
}
668
#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
669
GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
670
{ \
671
gen_op_load_gpr_T0(rA(ctx->opcode)); \
672
if (ctx->sf_mode) \
673
gen_op_##name##_64(); \
674
else \
675
gen_op_##name(); \
676
gen_op_store_T0_gpr(rD(ctx->opcode)); \
677
if (unlikely(Rc(ctx->opcode) != 0)) \
678
gen_set_Rc0(ctx); \
679
}
680
681
/* Two operands arithmetic functions */
682
#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
683
__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
684
__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
685
686
/* Two operands arithmetic functions with no overflow allowed */
687
#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
688
__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
689
690
/* One operand arithmetic functions */
691
#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
692
__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
693
__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
694
#else
695
#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
696
#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
697
#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
698
#endif
699
700
/* add add. addo addo. */
701
static always_inline void gen_op_addo (void)
702
{
703
gen_op_move_T2_T0();
704
gen_op_add();
705
gen_op_check_addo();
706
}
707
#if defined(TARGET_PPC64)
708
#define gen_op_add_64 gen_op_add
709
static always_inline void gen_op_addo_64 (void)
710
{
711
gen_op_move_T2_T0();
712
gen_op_add();
713
gen_op_check_addo_64();
714
}
715
#endif
716
GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
717
/* addc addc. addco addco. */
718
static always_inline void gen_op_addc (void)
719
{
720
gen_op_move_T2_T0();
721
gen_op_add();
722
gen_op_check_addc();
723
}
724
static always_inline void gen_op_addco (void)
725
{
726
gen_op_move_T2_T0();
727
gen_op_add();
728
gen_op_check_addc();
729
gen_op_check_addo();
730
}
731
#if defined(TARGET_PPC64)
732
static always_inline void gen_op_addc_64 (void)
733
{
734
gen_op_move_T2_T0();
735
gen_op_add();
736
gen_op_check_addc_64();
737
}
738
static always_inline void gen_op_addco_64 (void)
739
{
740
gen_op_move_T2_T0();
741
gen_op_add();
742
gen_op_check_addc_64();
743
gen_op_check_addo_64();
744
}
745
#endif
746
GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
747
/* adde adde. addeo addeo. */
748
static always_inline void gen_op_addeo (void)
749
{
750
gen_op_move_T2_T0();
751
gen_op_adde();
752
gen_op_check_addo();
753
}
754
#if defined(TARGET_PPC64)
755
static always_inline void gen_op_addeo_64 (void)
756
{
757
gen_op_move_T2_T0();
758
gen_op_adde_64();
759
gen_op_check_addo_64();
760
}
761
#endif
762
GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
1013
763
/* addme addme. addmeo addmeo. */
1014
GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1015
GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1016
/* addze addze. addzeo addzeo.*/
1017
GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1018
GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
764
static always_inline void gen_op_addme (void)
765
{
766
gen_op_move_T1_T0();
767
gen_op_add_me();
768
}
769
#if defined(TARGET_PPC64)
770
static always_inline void gen_op_addme_64 (void)
771
{
772
gen_op_move_T1_T0();
773
gen_op_add_me_64();
774
}
775
#endif
776
GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
777
/* addze addze. addzeo addzeo. */
778
static always_inline void gen_op_addze (void)
779
{
780
gen_op_move_T2_T0();
781
gen_op_add_ze();
782
gen_op_check_addc();
783
}
784
static always_inline void gen_op_addzeo (void)
785
{
786
gen_op_move_T2_T0();
787
gen_op_add_ze();
788
gen_op_check_addc();
789
gen_op_check_addo();
790
}
791
#if defined(TARGET_PPC64)
792
static always_inline void gen_op_addze_64 (void)
793
{
794
gen_op_move_T2_T0();
795
gen_op_add_ze();
796
gen_op_check_addc_64();
797
}
798
static always_inline void gen_op_addzeo_64 (void)
799
{
800
gen_op_move_T2_T0();
801
gen_op_add_ze();
802
gen_op_check_addc_64();
803
gen_op_check_addo_64();
804
}
805
#endif
806
GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
807
/* divw divw. divwo divwo. */
808
GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
809
/* divwu divwu. divwuo divwuo. */
810
GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
811
/* mulhw mulhw. */
812
GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
813
/* mulhwu mulhwu. */
814
GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
815
/* mullw mullw. mullwo mullwo. */
816
GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
817
/* neg neg. nego nego. */
818
GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
819
/* subf subf. subfo subfo. */
820
static always_inline void gen_op_subfo (void)
821
{
822
gen_op_move_T2_T0();
823
gen_op_subf();
824
gen_op_check_subfo();
825
}
826
#if defined(TARGET_PPC64)
827
#define gen_op_subf_64 gen_op_subf
828
static always_inline void gen_op_subfo_64 (void)
829
{
830
gen_op_move_T2_T0();
831
gen_op_subf();
832
gen_op_check_subfo_64();
833
}
834
#endif
835
GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
836
/* subfc subfc. subfco subfco. */
837
static always_inline void gen_op_subfc (void)
838
{
839
gen_op_subf();
840
gen_op_check_subfc();
841
}
842
static always_inline void gen_op_subfco (void)
843
{
844
gen_op_move_T2_T0();
845
gen_op_subf();
846
gen_op_check_subfc();
847
gen_op_check_subfo();
848
}
849
#if defined(TARGET_PPC64)
850
static always_inline void gen_op_subfc_64 (void)
851
{
852
gen_op_subf();
853
gen_op_check_subfc_64();
854
}
855
static always_inline void gen_op_subfco_64 (void)
856
{
857
gen_op_move_T2_T0();
858
gen_op_subf();
859
gen_op_check_subfc_64();
860
gen_op_check_subfo_64();
861
}
862
#endif
863
GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
864
/* subfe subfe. subfeo subfeo. */
865
static always_inline void gen_op_subfeo (void)
866
{
867
gen_op_move_T2_T0();
868
gen_op_subfe();
869
gen_op_check_subfo();
870
}
871
#if defined(TARGET_PPC64)
872
#define gen_op_subfe_64 gen_op_subfe
873
static always_inline void gen_op_subfeo_64 (void)
874
{
875
gen_op_move_T2_T0();
876
gen_op_subfe_64();
877
gen_op_check_subfo_64();
878
}
879
#endif
880
GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
881
/* subfme subfme. subfmeo subfmeo. */
882
GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
883
/* subfze subfze. subfzeo subfzeo. */
884
GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
1019
885
/* addi */
1020
886
GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1021
887
{
1023
889
1024
890
if (rA(ctx->opcode) == 0) {
1025
891
/* li case */
1026
tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1027
} else {
1028
tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1029
}
1030
}
1031
/* addic addic.*/
1032
static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1033
int compute_Rc0)
1034
{
1035
target_long simm = SIMM(ctx->opcode);
1036
1037
/* Start with XER CA and OV disabled, the most likely case */
1038
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1039
1040
if (likely(simm != 0)) {
1041
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1042
tcg_gen_addi_tl(t0, arg1, simm);
1043
gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1044
tcg_gen_mov_tl(ret, t0);
1045
tcg_temp_free(t0);
1046
} else {
1047
tcg_gen_mov_tl(ret, arg1);
1048
}
1049
if (compute_Rc0) {
1050
gen_set_Rc0(ctx, ret);
1051
}
1052
}
892
gen_set_T0(simm);
893
} else {
894
gen_op_load_gpr_T0(rA(ctx->opcode));
895
if (likely(simm != 0))
896
gen_op_addi(simm);
897
}
898
gen_op_store_T0_gpr(rD(ctx->opcode));
899
}
900
/* addic */
1053
901
GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1054
902
{
1055
gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
903
target_long simm = SIMM(ctx->opcode);
904
905
gen_op_load_gpr_T0(rA(ctx->opcode));
906
if (likely(simm != 0)) {
907
gen_op_move_T2_T0();
908
gen_op_addi(simm);
909
#if defined(TARGET_PPC64)
910
if (ctx->sf_mode)
911
gen_op_check_addc_64();
912
else
913
#endif
914
gen_op_check_addc();
915
} else {
916
gen_op_clear_xer_ca();
917
}
918
gen_op_store_T0_gpr(rD(ctx->opcode));
1056
919
}
1057
GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
920
/* addic. */
921
GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1058
922
{
1059
gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
923
target_long simm = SIMM(ctx->opcode);
924
925
gen_op_load_gpr_T0(rA(ctx->opcode));
926
if (likely(simm != 0)) {
927
gen_op_move_T2_T0();
928
gen_op_addi(simm);
929
#if defined(TARGET_PPC64)
930
if (ctx->sf_mode)
931
gen_op_check_addc_64();
932
else
933
#endif
934
gen_op_check_addc();
935
} else {
936
gen_op_clear_xer_ca();
937
}
938
gen_op_store_T0_gpr(rD(ctx->opcode));
939
gen_set_Rc0(ctx);
1060
940
}
1061
941
/* addis */
1062
942
GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1065
945
1066
946
if (rA(ctx->opcode) == 0) {
1067
947
/* lis case */
1068
tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1069
} else {
1070
tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1071
}
1072
}
1073
1074
static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1075
int sign, int compute_ov)
1076
{
1077
int l1 = gen_new_label();
1078
int l2 = gen_new_label();
1079
TCGv t0 = tcg_temp_local_new(TCG_TYPE_I32);
1080
TCGv t1 = tcg_temp_local_new(TCG_TYPE_I32);
1081
1082
tcg_gen_trunc_tl_i32(t0, arg1);
1083
tcg_gen_trunc_tl_i32(t1, arg2);
1084
tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1085
if (sign) {
1086
int l3 = gen_new_label();
1087
tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1088
tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1089
gen_set_label(l3);
1090
tcg_gen_div_i32(t0, t0, t1);
1091
} else {
1092
tcg_gen_divu_i32(t0, t0, t1);
1093
}
1094
if (compute_ov) {
1095
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1096
}
1097
tcg_gen_br(l2);
1098
gen_set_label(l1);
1099
if (sign) {
1100
tcg_gen_sari_i32(t0, t0, 31);
1101
} else {
1102
tcg_gen_movi_i32(t0, 0);
1103
}
1104
if (compute_ov) {
1105
tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1106
}
1107
gen_set_label(l2);
1108
tcg_gen_extu_i32_tl(ret, t0);
1109
tcg_temp_free(t0);
1110
tcg_temp_free(t1);
1111
if (unlikely(Rc(ctx->opcode) != 0))
1112
gen_set_Rc0(ctx, ret);
1113
}
1114
/* Div functions */
1115
#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1116
GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1117
{ \
1118
gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1119
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1120
sign, compute_ov); \
1121
}
1122
/* divwu divwu. divwuo divwuo. */
1123
GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1124
GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1125
/* divw divw. divwo divwo. */
1126
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1127
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1128
#if defined(TARGET_PPC64)
1129
static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1130
int sign, int compute_ov)
1131
{
1132
int l1 = gen_new_label();
1133
int l2 = gen_new_label();
1134
1135
tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1136
if (sign) {
1137
int l3 = gen_new_label();
1138
tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1139
tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1140
gen_set_label(l3);
1141
tcg_gen_div_i64(ret, arg1, arg2);
1142
} else {
1143
tcg_gen_divu_i64(ret, arg1, arg2);
1144
}
1145
if (compute_ov) {
1146
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1147
}
1148
tcg_gen_br(l2);
1149
gen_set_label(l1);
1150
if (sign) {
1151
tcg_gen_sari_i64(ret, arg1, 63);
1152
} else {
1153
tcg_gen_movi_i64(ret, 0);
1154
}
1155
if (compute_ov) {
1156
tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1157
}
1158
gen_set_label(l2);
1159
if (unlikely(Rc(ctx->opcode) != 0))
1160
gen_set_Rc0(ctx, ret);
1161
}
1162
#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1163
GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1164
{ \
1165
gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1166
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1167
sign, compute_ov); \
1168
}
1169
/* divwu divwu. divwuo divwuo. */
1170
GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1171
GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1172
/* divw divw. divwo divwo. */
1173
GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1174
GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1175
#endif
1176
1177
/* mulhw mulhw. */
1178
GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
1179
{
1180
TCGv t0, t1;
1181
1182
t0 = tcg_temp_new(TCG_TYPE_I64);
1183
t1 = tcg_temp_new(TCG_TYPE_I64);
1184
#if defined(TARGET_PPC64)
1185
tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1186
tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1187
tcg_gen_mul_i64(t0, t0, t1);
1188
tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1189
#else
1190
tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1191
tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1192
tcg_gen_mul_i64(t0, t0, t1);
1193
tcg_gen_shri_i64(t0, t0, 32);
1194
tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1195
#endif
1196
tcg_temp_free(t0);
1197
tcg_temp_free(t1);
1198
if (unlikely(Rc(ctx->opcode) != 0))
1199
gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1200
}
1201
/* mulhwu mulhwu. */
1202
GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
1203
{
1204
TCGv t0, t1;
1205
1206
t0 = tcg_temp_new(TCG_TYPE_I64);
1207
t1 = tcg_temp_new(TCG_TYPE_I64);
1208
#if defined(TARGET_PPC64)
1209
tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1210
tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1211
tcg_gen_mul_i64(t0, t0, t1);
1212
tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1213
#else
1214
tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1215
tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1216
tcg_gen_mul_i64(t0, t0, t1);
1217
tcg_gen_shri_i64(t0, t0, 32);
1218
tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1219
#endif
1220
tcg_temp_free(t0);
1221
tcg_temp_free(t1);
1222
if (unlikely(Rc(ctx->opcode) != 0))
1223
gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1224
}
1225
/* mullw mullw. */
1226
GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
1227
{
1228
tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1229
cpu_gpr[rB(ctx->opcode)]);
1230
tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1231
if (unlikely(Rc(ctx->opcode) != 0))
1232
gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1233
}
1234
/* mullwo mullwo. */
1235
GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
1236
{
1237
int l1;
1238
TCGv t0, t1;
1239
1240
t0 = tcg_temp_new(TCG_TYPE_I64);
1241
t1 = tcg_temp_new(TCG_TYPE_I64);
1242
l1 = gen_new_label();
1243
/* Start with XER OV disabled, the most likely case */
1244
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1245
#if defined(TARGET_PPC64)
1246
tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1247
tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1248
#else
1249
tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1250
tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1251
#endif
1252
tcg_gen_mul_i64(t0, t0, t1);
1253
#if defined(TARGET_PPC64)
1254
tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1255
tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1256
#else
1257
tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1258
tcg_gen_ext32s_i64(t1, t0);
1259
tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1260
#endif
1261
tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1262
gen_set_label(l1);
1263
tcg_temp_free(t0);
1264
tcg_temp_free(t1);
1265
if (unlikely(Rc(ctx->opcode) != 0))
1266
gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
948
gen_set_T0(simm << 16);
949
} else {
950
gen_op_load_gpr_T0(rA(ctx->opcode));
951
if (likely(simm != 0))
952
gen_op_addi(simm << 16);
953
}
954
gen_op_store_T0_gpr(rD(ctx->opcode));
1267
955
}
1268
956
/* mulli */
1269
957
GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1270
958
{
1271
tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1272
SIMM(ctx->opcode));
1273
}
1274
#if defined(TARGET_PPC64)
1275
#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1276
GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1277
{ \
1278
tcg_gen_helper_1_2(helper_##name, cpu_gpr[rD(ctx->opcode)], \
1279
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1280
if (unlikely(Rc(ctx->opcode) != 0)) \
1281
gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1282
}
1283
/* mulhd mulhd. */
1284
GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1285
/* mulhdu mulhdu. */
1286
GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1287
/* mulld mulld. */
1288
GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
1289
{
1290
tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1291
cpu_gpr[rB(ctx->opcode)]);
1292
if (unlikely(Rc(ctx->opcode) != 0))
1293
gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1294
}
1295
/* mulldo mulldo. */
1296
GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1297
#endif
1298
1299
/* neg neg. nego nego. */
1300
static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1301
{
1302
int l1 = gen_new_label();
1303
int l2 = gen_new_label();
1304
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1305
#if defined(TARGET_PPC64)
1306
if (ctx->sf_mode) {
1307
tcg_gen_mov_tl(t0, arg1);
1308
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1309
} else
1310
#endif
1311
{
1312
tcg_gen_ext32s_tl(t0, arg1);
1313
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1314
}
1315
tcg_gen_neg_tl(ret, arg1);
1316
if (ov_check) {
1317
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1318
}
1319
tcg_gen_br(l2);
1320
gen_set_label(l1);
1321
tcg_gen_mov_tl(ret, t0);
1322
if (ov_check) {
1323
tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1324
}
1325
gen_set_label(l2);
1326
tcg_temp_free(t0);
1327
if (unlikely(Rc(ctx->opcode) != 0))
1328
gen_set_Rc0(ctx, ret);
1329
}
1330
GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1331
{
1332
gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1333
}
1334
GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1335
{
1336
gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1337
}
1338
1339
/* Common subf function */
1340
static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1341
int add_ca, int compute_ca, int compute_ov)
1342
{
1343
TCGv t0, t1;
1344
1345
if ((!compute_ca && !compute_ov) ||
1346
(GET_TCGV(ret) != GET_TCGV(arg1) && GET_TCGV(ret) != GET_TCGV(arg2))) {
1347
t0 = ret;
1348
} else {
1349
t0 = tcg_temp_local_new(TCG_TYPE_TL);
1350
}
1351
1352
if (add_ca) {
1353
t1 = tcg_temp_local_new(TCG_TYPE_TL);
1354
tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1355
tcg_gen_shri_tl(t1, t1, XER_CA);
1356
}
1357
1358
if (compute_ca && compute_ov) {
1359
/* Start with XER CA and OV disabled, the most likely case */
1360
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1361
} else if (compute_ca) {
1362
/* Start with XER CA disabled, the most likely case */
1363
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1364
} else if (compute_ov) {
1365
/* Start with XER OV disabled, the most likely case */
1366
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1367
}
1368
1369
if (add_ca) {
1370
tcg_gen_not_tl(t0, arg1);
1371
tcg_gen_add_tl(t0, t0, arg2);
1372
gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1373
tcg_gen_add_tl(t0, t0, t1);
1374
gen_op_arith_compute_ca(ctx, t0, t1, 0);
1375
tcg_temp_free(t1);
1376
} else {
1377
tcg_gen_sub_tl(t0, arg2, arg1);
1378
if (compute_ca) {
1379
gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1380
}
1381
}
1382
if (compute_ov) {
1383
gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1384
}
1385
1386
if (unlikely(Rc(ctx->opcode) != 0))
1387
gen_set_Rc0(ctx, t0);
1388
1389
if (GET_TCGV(t0) != GET_TCGV(ret)) {
1390
tcg_gen_mov_tl(ret, t0);
1391
tcg_temp_free(t0);
1392
}
1393
}
1394
/* Sub functions with Two operands functions */
1395
#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1396
GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1397
{ \
1398
gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1399
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1400
add_ca, compute_ca, compute_ov); \
1401
}
1402
/* Sub functions with one operand and one immediate */
1403
#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1404
add_ca, compute_ca, compute_ov) \
1405
GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1406
{ \
1407
TCGv t0 = tcg_const_local_tl(const_val); \
1408
gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1409
cpu_gpr[rA(ctx->opcode)], t0, \
1410
add_ca, compute_ca, compute_ov); \
1411
tcg_temp_free(t0); \
1412
}
1413
/* subf subf. subfo subfo. */
1414
GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1415
GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1416
/* subfc subfc. subfco subfco. */
1417
GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1418
GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1419
/* subfe subfe. subfeo subfo. */
1420
GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1421
GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1422
/* subfme subfme. subfmeo subfmeo. */
1423
GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1424
GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1425
/* subfze subfze. subfzeo subfzeo.*/
1426
GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1427
GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
959
gen_op_load_gpr_T0(rA(ctx->opcode));
960
gen_op_mulli(SIMM(ctx->opcode));
961
gen_op_store_T0_gpr(rD(ctx->opcode));
962
}
1428
963
/* subfic */
1429
964
GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1430
965
{
1431
/* Start with XER CA and OV disabled, the most likely case */
1432
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1433
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1434
TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1435
tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1436
gen_op_arith_compute_ca(ctx, t0, t1, 1);
1437
tcg_temp_free(t1);
1438
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1439
tcg_temp_free(t0);
966
gen_op_load_gpr_T0(rA(ctx->opcode));
967
#if defined(TARGET_PPC64)
968
if (ctx->sf_mode)
969
gen_op_subfic_64(SIMM(ctx->opcode));
970
else
971
#endif
972
gen_op_subfic(SIMM(ctx->opcode));
973
gen_op_store_T0_gpr(rD(ctx->opcode));
974
}
975
976
#if defined(TARGET_PPC64)
977
/* mulhd mulhd. */
978
GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
979
/* mulhdu mulhdu. */
980
GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
981
/* mulld mulld. mulldo mulldo. */
982
GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
983
/* divd divd. divdo divdo. */
984
GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
985
/* divdu divdu. divduo divduo. */
986
GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
987
#endif
988
989
/*** Integer comparison ***/
990
#if defined(TARGET_PPC64)
991
#define GEN_CMP(name, opc, type) \
992
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
993
{ \
994
gen_op_load_gpr_T0(rA(ctx->opcode)); \
995
gen_op_load_gpr_T1(rB(ctx->opcode)); \
996
if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
997
gen_op_##name##_64(); \
998
else \
999
gen_op_##name(); \
1000
gen_op_store_T0_crf(crfD(ctx->opcode)); \
1001
}
1002
#else
1003
#define GEN_CMP(name, opc, type) \
1004
GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1005
{ \
1006
gen_op_load_gpr_T0(rA(ctx->opcode)); \
1007
gen_op_load_gpr_T1(rB(ctx->opcode)); \
1008
gen_op_##name(); \
1009
gen_op_store_T0_crf(crfD(ctx->opcode)); \
1010
}
1011
#endif
1012
1013
/* cmp */
1014
GEN_CMP(cmp, 0x00, PPC_INTEGER);
1015
/* cmpi */
1016
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1017
{
1018
gen_op_load_gpr_T0(rA(ctx->opcode));
1019
#if defined(TARGET_PPC64)
1020
if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1021
gen_op_cmpi_64(SIMM(ctx->opcode));
1022
else
1023
#endif
1024
gen_op_cmpi(SIMM(ctx->opcode));
1025
gen_op_store_T0_crf(crfD(ctx->opcode));
1026
}
1027
/* cmpl */
1028
GEN_CMP(cmpl, 0x01, PPC_INTEGER);
1029
/* cmpli */
1030
GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1031
{
1032
gen_op_load_gpr_T0(rA(ctx->opcode));
1033
#if defined(TARGET_PPC64)
1034
if (ctx->sf_mode && (ctx->opcode & 0x00200000))
1035
gen_op_cmpli_64(UIMM(ctx->opcode));
1036
else
1037
#endif
1038
gen_op_cmpli(UIMM(ctx->opcode));
1039
gen_op_store_T0_crf(crfD(ctx->opcode));
1040
}
1041
1042
/* isel (PowerPC 2.03 specification) */
1043
GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203)
1044
{
1045
uint32_t bi = rC(ctx->opcode);
1046
uint32_t mask;
1047
1048
if (rA(ctx->opcode) == 0) {
1049
gen_set_T0(0);
1050
} else {
1051
gen_op_load_gpr_T1(rA(ctx->opcode));
1052
}
1053
gen_op_load_gpr_T2(rB(ctx->opcode));
1054
mask = 1 << (3 - (bi & 0x03));
1055
gen_op_load_crf_T0(bi >> 2);
1056
gen_op_test_true(mask);
1057
gen_op_isel();
1058
gen_op_store_T0_gpr(rD(ctx->opcode));
1440
1059
}
1441
1060
1442
1061
/*** Integer logical ***/
1443
#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1444
GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
1062
#define __GEN_LOGICAL2(name, opc2, opc3, type) \
1063
GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
1445
1064
{ \
1446
tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1447
cpu_gpr[rB(ctx->opcode)]); \
1065
gen_op_load_gpr_T0(rS(ctx->opcode)); \
1066
gen_op_load_gpr_T1(rB(ctx->opcode)); \
1067
gen_op_##name(); \
1068
gen_op_store_T0_gpr(rA(ctx->opcode)); \
1448
1069
if (unlikely(Rc(ctx->opcode) != 0)) \
1449
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1070
gen_set_Rc0(ctx); \
1450
1071
}
1072
#define GEN_LOGICAL2(name, opc, type) \
1073
__GEN_LOGICAL2(name, 0x1C, opc, type)
1451
1074
1452
#define GEN_LOGICAL1(name, tcg_op, opc, type) \
1075
#define GEN_LOGICAL1(name, opc, type) \
1453
1076
GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
1454
1077
{ \
1455
tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1078
gen_op_load_gpr_T0(rS(ctx->opcode)); \
1079
gen_op_##name(); \
1080
gen_op_store_T0_gpr(rA(ctx->opcode)); \
1456
1081
if (unlikely(Rc(ctx->opcode) != 0)) \
1457
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1082
gen_set_Rc0(ctx); \
1458
1083
}
1459
1084
1460
1085
/* and & and. */
1461
GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1086
GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
1462
1087
/* andc & andc. */
1463
GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1088
GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
1464
1089
/* andi. */
1465
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1090
GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1466
1091
{
1467
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1468
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1092
gen_op_load_gpr_T0(rS(ctx->opcode));
1093
gen_op_andi_T0(UIMM(ctx->opcode));
1094
gen_op_store_T0_gpr(rA(ctx->opcode));
1095
gen_set_Rc0(ctx);
1469
1096
}
1470
1097
/* andis. */
1471
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1098
GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1472
1099
{
1473
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1474
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1100
gen_op_load_gpr_T0(rS(ctx->opcode));
1101
gen_op_andi_T0(UIMM(ctx->opcode) << 16);
1102
gen_op_store_T0_gpr(rA(ctx->opcode));
1103
gen_set_Rc0(ctx);
1475
1104
}
1105
1476
1106
/* cntlzw */
1477
GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1478
{
1479
tcg_gen_helper_1_1(helper_cntlzw, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1480
if (unlikely(Rc(ctx->opcode) != 0))
1481
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1482
}
1107
GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
1483
1108
/* eqv & eqv. */
1484
GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1109
GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
1485
1110
/* extsb & extsb. */
1486
GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1111
GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
1487
1112
/* extsh & extsh. */
1488
GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1113
GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
1489
1114
/* nand & nand. */
1490
GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1115
GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
1491
1116
/* nor & nor. */
1492
GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1117
GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
1118
1493
1119
/* or & or. */
1494
1120
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1495
1121
{
1500
1126
rb = rB(ctx->opcode);
1501
1127
/* Optimisation for mr. ri case */
1502
1128
if (rs != ra || rs != rb) {
1503
if (rs != rb)
1504
tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1505
else
1506
tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1129
gen_op_load_gpr_T0(rs);
1130
if (rs != rb) {
1131
gen_op_load_gpr_T1(rb);
1132
gen_op_or();
1133
}
1134
gen_op_store_T0_gpr(ra);
1507
1135
if (unlikely(Rc(ctx->opcode) != 0))
1508
gen_set_Rc0(ctx, cpu_gpr[ra]);
1136
gen_set_Rc0(ctx);
1509
1137
} else if (unlikely(Rc(ctx->opcode) != 0)) {
1510
gen_set_Rc0(ctx, cpu_gpr[rs]);
1138
gen_op_load_gpr_T0(rs);
1139
gen_set_Rc0(ctx);
1511
1140
#if defined(TARGET_PPC64)
1512
1141
} else {
1513
int prio = 0;
1514
1515
1142
switch (rs) {
1516
1143
case 1:
1517
1144
/* Set process priority to low */
1518
prio = 2;
1145
gen_op_store_pri(2);
1519
1146
break;
1520
1147
case 6:
1521
1148
/* Set process priority to medium-low */
1522
prio = 3;
1149
gen_op_store_pri(3);
1523
1150
break;
1524
1151
case 2:
1525
1152
/* Set process priority to normal */
1526
prio = 4;
1153
gen_op_store_pri(4);
1527
1154
break;
1528
1155
#if !defined(CONFIG_USER_ONLY)
1529
1156
case 31:
1530
1157
if (ctx->supervisor > 0) {
1531
1158
/* Set process priority to very low */
1532
prio = 1;
1159
gen_op_store_pri(1);
1533
1160
}
1534
1161
break;
1535
1162
case 5:
1536
1163
if (ctx->supervisor > 0) {
1537
1164
/* Set process priority to medium-hight */
1538
prio = 5;
1165
gen_op_store_pri(5);
1539
1166
}
1540
1167
break;
1541
1168
case 3:
1542
1169
if (ctx->supervisor > 0) {
1543
1170
/* Set process priority to high */
1544
prio = 6;
1171
gen_op_store_pri(6);
1545
1172
}
1546
1173
break;
1174
#if defined(TARGET_PPC64H)
1547
1175
case 7:
1548
1176
if (ctx->supervisor > 1) {
1549
1177
/* Set process priority to very high */
1550
prio = 7;
1178
gen_op_store_pri(7);
1551
1179
}
1552
1180
break;
1553
1181
#endif
1182
#endif
1554
1183
default:
1555
1184
/* nop */
1556
1185
break;
1557
1186
}
1558
if (prio) {
1559
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1560
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1561
tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1562
tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1563
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1564
tcg_temp_free(t0);
1565
}
1566
1187
#endif
1567
1188
}
1568
1189
}
1190
1569
1191
/* orc & orc. */
1570
GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1192
GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
1571
1193
/* xor & xor. */
1572
1194
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1573
1195
{
1196
gen_op_load_gpr_T0(rS(ctx->opcode));
1574
1197
/* Optimisation for "set to zero" case */
1575
if (rS(ctx->opcode) != rB(ctx->opcode))
1576
tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1577
else
1578
tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1198
if (rS(ctx->opcode) != rB(ctx->opcode)) {
1199
gen_op_load_gpr_T1(rB(ctx->opcode));
1200
gen_op_xor();
1201
} else {
1202
gen_op_reset_T0();
1203
}
1204
gen_op_store_T0_gpr(rA(ctx->opcode));
1579
1205
if (unlikely(Rc(ctx->opcode) != 0))
1580
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1206
gen_set_Rc0(ctx);
1581
1207
}
1582
1208
/* ori */
1583
1209
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1589
1215
/* XXX: should handle special NOPs for POWER series */
1590
1216
return;
1591
1217
}
1592
tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1218
gen_op_load_gpr_T0(rS(ctx->opcode));
1219
if (likely(uimm != 0))
1220
gen_op_ori(uimm);
1221
gen_op_store_T0_gpr(rA(ctx->opcode));
1593
1222
}
1594
1223
/* oris */
1595
1224
GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1600
1229
/* NOP */
1601
1230
return;
1602
1231
}
1603
tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1232
gen_op_load_gpr_T0(rS(ctx->opcode));
1233
if (likely(uimm != 0))
1234
gen_op_ori(uimm << 16);
1235
gen_op_store_T0_gpr(rA(ctx->opcode));
1604
1236
}
1605
1237
/* xori */
1606
1238
GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1611
1243
/* NOP */
1612
1244
return;
1613
1245
}
1614
tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1246
gen_op_load_gpr_T0(rS(ctx->opcode));
1247
if (likely(uimm != 0))
1248
gen_op_xori(uimm);
1249
gen_op_store_T0_gpr(rA(ctx->opcode));
1615
1250
}
1251
1616
1252
/* xoris */
1617
1253
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1618
1254
{
1622
1258
/* NOP */
1623
1259
return;
1624
1260
}
1625
tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1261
gen_op_load_gpr_T0(rS(ctx->opcode));
1262
if (likely(uimm != 0))
1263
gen_op_xori(uimm << 16);
1264
gen_op_store_T0_gpr(rA(ctx->opcode));
1626
1265
}
1266
1627
1267
/* popcntb : PowerPC 2.03 specification */
1628
GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
1268
GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203)
1629
1269
{
1270
gen_op_load_gpr_T0(rS(ctx->opcode));
1630
1271
#if defined(TARGET_PPC64)
1631
1272
if (ctx->sf_mode)
1632
tcg_gen_helper_1_1(helper_popcntb_64, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1273
gen_op_popcntb_64();
1633
1274
else
1634
1275
#endif
1635
tcg_gen_helper_1_1(helper_popcntb, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1276
gen_op_popcntb();
1277
gen_op_store_T0_gpr(rA(ctx->opcode));
1636
1278
}
1637
1279
1638
1280
#if defined(TARGET_PPC64)
1639
1281
/* extsw & extsw. */
1640
GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1282
GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1641
1283
/* cntlzd */
1642
GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1643
{
1644
tcg_gen_helper_1_1(helper_cntlzd, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1645
if (unlikely(Rc(ctx->opcode) != 0))
1646
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1647
}
1284
GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1648
1285
#endif
1649
1286
1650
1287
/*** Integer rotate ***/
1651
1288
/* rlwimi & rlwimi. */
1652
1289
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1653
1290
{
1291
target_ulong mask;
1654
1292
uint32_t mb, me, sh;
1655
1293
1656
1294
mb = MB(ctx->opcode);
1657
1295
me = ME(ctx->opcode);
1658
1296
sh = SH(ctx->opcode);
1659
if (likely(sh == 0 && mb == 0 && me == 31)) {
1660
tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1661
} else {
1662
TCGv t0, t1;
1663
target_ulong mask;
1664
1665
t0 = tcg_temp_new(TCG_TYPE_TL);
1666
#if defined(TARGET_PPC64)
1667
t1 = tcg_temp_new(TCG_TYPE_I32);
1668
tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1669
tcg_gen_rotli_i32(t1, t1, sh);
1670
tcg_gen_extu_i32_i64(t0, t1);
1671
tcg_temp_free(t1);
1672
#else
1673
tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1674
#endif
1675
#if defined(TARGET_PPC64)
1676
mb += 32;
1677
me += 32;
1678
#endif
1679
mask = MASK(mb, me);
1680
t1 = tcg_temp_new(TCG_TYPE_TL);
1681
tcg_gen_andi_tl(t0, t0, mask);
1682
tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1683
tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1684
tcg_temp_free(t0);
1685
tcg_temp_free(t1);
1297
if (likely(sh == 0)) {
1298
if (likely(mb == 0 && me == 31)) {
1299
gen_op_load_gpr_T0(rS(ctx->opcode));
1300
goto do_store;
1301
} else if (likely(mb == 31 && me == 0)) {
1302
gen_op_load_gpr_T0(rA(ctx->opcode));
1303
goto do_store;
1304
}
1305
gen_op_load_gpr_T0(rS(ctx->opcode));
1306
gen_op_load_gpr_T1(rA(ctx->opcode));
1307
goto do_mask;
1686
1308
}
1309
gen_op_load_gpr_T0(rS(ctx->opcode));
1310
gen_op_load_gpr_T1(rA(ctx->opcode));
1311
gen_op_rotli32_T0(SH(ctx->opcode));
1312
do_mask:
1313
#if defined(TARGET_PPC64)
1314
mb += 32;
1315
me += 32;
1316
#endif
1317
mask = MASK(mb, me);
1318
gen_op_andi_T0(mask);
1319
gen_op_andi_T1(~mask);
1320
gen_op_or();
1321
do_store:
1322
gen_op_store_T0_gpr(rA(ctx->opcode));
1687
1323
if (unlikely(Rc(ctx->opcode) != 0))
1688
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1324
gen_set_Rc0(ctx);
1689
1325
}
1690
1326
/* rlwinm & rlwinm. */
1691
1327
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1695
1331
sh = SH(ctx->opcode);
1696
1332
mb = MB(ctx->opcode);
1697
1333
me = ME(ctx->opcode);
1698
1699
if (likely(mb == 0 && me == (31 - sh))) {
1700
if (likely(sh == 0)) {
1701
tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1702
} else {
1703
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1704
tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1705
tcg_gen_shli_tl(t0, t0, sh);
1706
tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1707
tcg_temp_free(t0);
1708
}
1709
} else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1710
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1711
tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1712
tcg_gen_shri_tl(t0, t0, mb);
1713
tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1714
tcg_temp_free(t0);
1715
} else {
1716
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1717
#if defined(TARGET_PPC64)
1718
TCGv t1 = tcg_temp_new(TCG_TYPE_I32);
1719
tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1720
tcg_gen_rotli_i32(t1, t1, sh);
1721
tcg_gen_extu_i32_i64(t0, t1);
1722
tcg_temp_free(t1);
1723
#else
1724
tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1725
#endif
1726
#if defined(TARGET_PPC64)
1727
mb += 32;
1728
me += 32;
1729
#endif
1730
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1731
tcg_temp_free(t0);
1732
}
1334
gen_op_load_gpr_T0(rS(ctx->opcode));
1335
if (likely(sh == 0)) {
1336
goto do_mask;
1337
}
1338
if (likely(mb == 0)) {
1339
if (likely(me == 31)) {
1340
gen_op_rotli32_T0(sh);
1341
goto do_store;
1342
} else if (likely(me == (31 - sh))) {
1343
gen_op_sli_T0(sh);
1344
goto do_store;
1345
}
1346
} else if (likely(me == 31)) {
1347
if (likely(sh == (32 - mb))) {
1348
gen_op_srli_T0(mb);
1349
goto do_store;
1350
}
1351
}
1352
gen_op_rotli32_T0(sh);
1353
do_mask:
1354
#if defined(TARGET_PPC64)
1355
mb += 32;
1356
me += 32;
1357
#endif
1358
gen_op_andi_T0(MASK(mb, me));
1359
do_store:
1360
gen_op_store_T0_gpr(rA(ctx->opcode));
1733
1361
if (unlikely(Rc(ctx->opcode) != 0))
1734
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1362
gen_set_Rc0(ctx);
1735
1363
}
1736
1364
/* rlwnm & rlwnm. */
1737
1365
GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1738
1366
{
1739
1367
uint32_t mb, me;
1740
TCGv t0;
1741
#if defined(TARGET_PPC64)
1742
TCGv t1, t2;
1743
#endif
1744
1368
1745
1369
mb = MB(ctx->opcode);
1746
1370
me = ME(ctx->opcode);
1747
t0 = tcg_temp_new(TCG_TYPE_TL);
1748
tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1749
#if defined(TARGET_PPC64)
1750
t1 = tcg_temp_new(TCG_TYPE_I32);
1751
t2 = tcg_temp_new(TCG_TYPE_I32);
1752
tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1753
tcg_gen_trunc_i64_i32(t2, t0);
1754
tcg_gen_rotl_i32(t1, t1, t2);
1755
tcg_gen_extu_i32_i64(t0, t1);
1756
tcg_temp_free(t1);
1757
tcg_temp_free(t2);
1758
#else
1759
tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1760
#endif
1371
gen_op_load_gpr_T0(rS(ctx->opcode));
1372
gen_op_load_gpr_T1(rB(ctx->opcode));
1373
gen_op_rotl32_T0_T1();
1761
1374
if (unlikely(mb != 0 || me != 31)) {
1762
1375
#if defined(TARGET_PPC64)
1763
1376
mb += 32;
1764
1377
me += 32;
1765
1378
#endif
1766
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1767
} else {
1768
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1379
gen_op_andi_T0(MASK(mb, me));
1769
1380
}
1770
tcg_temp_free(t0);
1381
gen_op_store_T0_gpr(rA(ctx->opcode));
1771
1382
if (unlikely(Rc(ctx->opcode) != 0))
1772
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1383
gen_set_Rc0(ctx);
1773
1384
}
1774
1385
1775
1386
#if defined(TARGET_PPC64)
1776
1387
#define GEN_PPC64_R2(name, opc1, opc2) \
1777
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1388
GEN_HANDLER(name##0, opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1778
1389
{ \
1779
1390
gen_##name(ctx, 0); \
1780
1391
} \
1781
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1782
PPC_64B) \
1392
GEN_HANDLER(name##1, opc1, opc2 | 0x10, 0xFF, 0x00000000, PPC_64B) \
1783
1393
{ \
1784
1394
gen_##name(ctx, 1); \
1785
1395
}
1786
1396
#define GEN_PPC64_R4(name, opc1, opc2) \
1787
GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1397
GEN_HANDLER(name##0, opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
1788
1398
{ \
1789
1399
gen_##name(ctx, 0, 0); \
1790
1400
} \
1791
GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1792
PPC_64B) \
1401
GEN_HANDLER(name##1, opc1, opc2 | 0x01, 0xFF, 0x00000000, PPC_64B) \
1793
1402
{ \
1794
1403
gen_##name(ctx, 0, 1); \
1795
1404
} \
1796
GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1797
PPC_64B) \
1405
GEN_HANDLER(name##2, opc1, opc2 | 0x10, 0xFF, 0x00000000, PPC_64B) \
1798
1406
{ \
1799
1407
gen_##name(ctx, 1, 0); \
1800
1408
} \
1801
GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1802
PPC_64B) \
1409
GEN_HANDLER(name##3, opc1, opc2 | 0x11, 0xFF, 0x00000000, PPC_64B) \
1803
1410
{ \
1804
1411
gen_##name(ctx, 1, 1); \
1805
1412
}
1806
1413
1414
static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
1415
{
1416
if (mask >> 32)
1417
gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1418
else
1419
gen_op_andi_T0(mask);
1420
}
1421
1422
static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
1423
{
1424
if (mask >> 32)
1425
gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1426
else
1427
gen_op_andi_T1(mask);
1428
}
1429
1807
1430
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1808
1431
uint32_t me, uint32_t sh)
1809
1432
{
1810
if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1811
tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1812
} else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1813
tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1814
} else {
1815
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1816
tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1817
if (likely(mb == 0 && me == 63)) {
1818
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1819
} else {
1820
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1821
}
1822
tcg_temp_free(t0);
1823
}
1433
gen_op_load_gpr_T0(rS(ctx->opcode));
1434
if (likely(sh == 0)) {
1435
goto do_mask;
1436
}
1437
if (likely(mb == 0)) {
1438
if (likely(me == 63)) {
1439
gen_op_rotli64_T0(sh);
1440
goto do_store;
1441
} else if (likely(me == (63 - sh))) {
1442
gen_op_sli_T0(sh);
1443
goto do_store;
1444
}
1445
} else if (likely(me == 63)) {
1446
if (likely(sh == (64 - mb))) {
1447
gen_op_srli_T0_64(mb);
1448
goto do_store;
1449
}
1450
}
1451
gen_op_rotli64_T0(sh);
1452
do_mask:
1453
gen_andi_T0_64(ctx, MASK(mb, me));
1454
do_store:
1455
gen_op_store_T0_gpr(rA(ctx->opcode));
1824
1456
if (unlikely(Rc(ctx->opcode) != 0))
1825
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1457
gen_set_Rc0(ctx);
1826
1458
}
1827
1459
/* rldicl - rldicl. */
1828
1460
static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
1858
1490
static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1859
1491
uint32_t me)
1860
1492
{
1861
TCGv t0;
1862
1863
mb = MB(ctx->opcode);
1864
me = ME(ctx->opcode);
1865
t0 = tcg_temp_new(TCG_TYPE_TL);
1866
tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1867
tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1493
gen_op_load_gpr_T0(rS(ctx->opcode));
1494
gen_op_load_gpr_T1(rB(ctx->opcode));
1495
gen_op_rotl64_T0_T1();
1868
1496
if (unlikely(mb != 0 || me != 63)) {
1869
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1870
} else {
1871
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1497
gen_andi_T0_64(ctx, MASK(mb, me));
1872
1498
}
1873
tcg_temp_free(t0);
1499
gen_op_store_T0_gpr(rA(ctx->opcode));
1874
1500
if (unlikely(Rc(ctx->opcode) != 0))
1875
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1501
gen_set_Rc0(ctx);
1876
1502
}
1877
1503
1878
1504
/* rldcl - rldcl. */
1896
1522
/* rldimi - rldimi. */
1897
1523
static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
1898
1524
{
1899
uint32_t sh, mb, me;
1525
uint64_t mask;
1526
uint32_t sh, mb;
1900
1527
1901
1528
sh = SH(ctx->opcode) | (shn << 5);
1902
1529
mb = MB(ctx->opcode) | (mbn << 5);
1903
me = 63 - sh;
1904
if (unlikely(sh == 0 && mb == 0)) {
1905
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1906
} else {
1907
TCGv t0, t1;
1908
target_ulong mask;
1909
1910
t0 = tcg_temp_new(TCG_TYPE_TL);
1911
tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1912
t1 = tcg_temp_new(TCG_TYPE_TL);
1913
mask = MASK(mb, me);
1914
tcg_gen_andi_tl(t0, t0, mask);
1915
tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1916
tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1917
tcg_temp_free(t0);
1918
tcg_temp_free(t1);
1530
if (likely(sh == 0)) {
1531
if (likely(mb == 0)) {
1532
gen_op_load_gpr_T0(rS(ctx->opcode));
1533
goto do_store;
1534
} else if (likely(mb == 63)) {
1535
gen_op_load_gpr_T0(rA(ctx->opcode));
1536
goto do_store;
1537
}
1538
gen_op_load_gpr_T0(rS(ctx->opcode));
1539
gen_op_load_gpr_T1(rA(ctx->opcode));
1540
goto do_mask;
1919
1541
}
1542
gen_op_load_gpr_T0(rS(ctx->opcode));
1543
gen_op_load_gpr_T1(rA(ctx->opcode));
1544
gen_op_rotli64_T0(sh);
1545
do_mask:
1546
mask = MASK(mb, 63 - sh);
1547
gen_andi_T0_64(ctx, mask);
1548
gen_andi_T1_64(ctx, ~mask);
1549
gen_op_or();
1550
do_store:
1551
gen_op_store_T0_gpr(rA(ctx->opcode));
1920
1552
if (unlikely(Rc(ctx->opcode) != 0))
1921
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1553
gen_set_Rc0(ctx);
1922
1554
}
1923
1555
GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1924
1556
#endif
1925
1557
1926
1558
/*** Integer shift ***/
1927
1559
/* slw & slw. */
1928
GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1929
{
1930
TCGv t0;
1931
int l1, l2;
1932
l1 = gen_new_label();
1933
l2 = gen_new_label();
1934
1935
t0 = tcg_temp_local_new(TCG_TYPE_TL);
1936
tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1937
tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1938
tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1939
tcg_gen_br(l2);
1940
gen_set_label(l1);
1941
tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
1942
tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1943
gen_set_label(l2);
1944
tcg_temp_free(t0);
1945
if (unlikely(Rc(ctx->opcode) != 0))
1946
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1947
}
1560
__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
1948
1561
/* sraw & sraw. */
1949
GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1950
{
1951
tcg_gen_helper_1_2(helper_sraw, cpu_gpr[rA(ctx->opcode)],
1952
cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1953
if (unlikely(Rc(ctx->opcode) != 0))
1954
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1955
}
1562
__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
1956
1563
/* srawi & srawi. */
1957
1564
GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1958
1565
{
1959
int sh = SH(ctx->opcode);
1960
if (sh != 0) {
1961
int l1, l2;
1962
TCGv t0;
1963
l1 = gen_new_label();
1964
l2 = gen_new_label();
1965
t0 = tcg_temp_local_new(TCG_TYPE_TL);
1966
tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1967
tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1968
tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1969
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1970
tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1971
tcg_gen_br(l2);
1972
gen_set_label(l1);
1973
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1974
gen_set_label(l2);
1975
tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1976
tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1977
tcg_temp_free(t0);
1978
} else {
1979
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1980
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1566
int mb, me;
1567
gen_op_load_gpr_T0(rS(ctx->opcode));
1568
if (SH(ctx->opcode) != 0) {
1569
gen_op_move_T1_T0();
1570
mb = 32 - SH(ctx->opcode);
1571
me = 31;
1572
#if defined(TARGET_PPC64)
1573
mb += 32;
1574
me += 32;
1575
#endif
1576
gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1981
1577
}
1578
gen_op_store_T0_gpr(rA(ctx->opcode));
1982
1579
if (unlikely(Rc(ctx->opcode) != 0))
1983
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1580
gen_set_Rc0(ctx);
1984
1581
}
1985
1582
/* srw & srw. */
1986
GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1987
{
1988
TCGv t0, t1;
1989
int l1, l2;
1990
l1 = gen_new_label();
1991
l2 = gen_new_label();
1583
__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1992
1584
1993
t0 = tcg_temp_local_new(TCG_TYPE_TL);
1994
tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1995
tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
1996
tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1997
tcg_gen_br(l2);
1998
gen_set_label(l1);
1999
t1 = tcg_temp_new(TCG_TYPE_TL);
2000
tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
2001
tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
2002
tcg_temp_free(t1);
2003
gen_set_label(l2);
2004
tcg_temp_free(t0);
2005
if (unlikely(Rc(ctx->opcode) != 0))
2006
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2007
}
2008
1585
#if defined(TARGET_PPC64)
2009
1586
/* sld & sld. */
2010
GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2011
{
2012
TCGv t0;
2013
int l1, l2;
2014
l1 = gen_new_label();
2015
l2 = gen_new_label();
2016
2017
t0 = tcg_temp_local_new(TCG_TYPE_TL);
2018
tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2019
tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2020
tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2021
tcg_gen_br(l2);
2022
gen_set_label(l1);
2023
tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2024
gen_set_label(l2);
2025
tcg_temp_free(t0);
2026
if (unlikely(Rc(ctx->opcode) != 0))
2027
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2028
}
1587
__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
2029
1588
/* srad & srad. */
2030
GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2031
{
2032
tcg_gen_helper_1_2(helper_srad, cpu_gpr[rA(ctx->opcode)],
2033
cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2034
if (unlikely(Rc(ctx->opcode) != 0))
2035
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2036
}
1589
__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
2037
1590
/* sradi & sradi. */
2038
1591
static always_inline void gen_sradi (DisasContext *ctx, int n)
2039
1592
{
2040
int sh = SH(ctx->opcode) + (n << 5);
1593
uint64_t mask;
1594
int sh, mb, me;
1595
1596
gen_op_load_gpr_T0(rS(ctx->opcode));
1597
sh = SH(ctx->opcode) + (n << 5);
2041
1598
if (sh != 0) {
2042
int l1, l2;
2043
TCGv t0;
2044
l1 = gen_new_label();
2045
l2 = gen_new_label();
2046
t0 = tcg_temp_local_new(TCG_TYPE_TL);
2047
tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
2048
tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2049
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2050
tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
2051
tcg_gen_br(l2);
2052
gen_set_label(l1);
2053
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
2054
gen_set_label(l2);
2055
tcg_temp_free(t0);
2056
tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2057
} else {
2058
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
2059
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1599
gen_op_move_T1_T0();
1600
mb = 64 - SH(ctx->opcode);
1601
me = 63;
1602
mask = MASK(mb, me);
1603
gen_op_sradi(sh, mask >> 32, mask);
2060
1604
}
1605
gen_op_store_T0_gpr(rA(ctx->opcode));
2061
1606
if (unlikely(Rc(ctx->opcode) != 0))
2062
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1607
gen_set_Rc0(ctx);
2063
1608
}
2064
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
1609
GEN_HANDLER(sradi0, 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
2065
1610
{
2066
1611
gen_sradi(ctx, 0);
2067
1612
}
2068
GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
1613
GEN_HANDLER(sradi1, 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
2069
1614
{
2070
1615
gen_sradi(ctx, 1);
2071
1616
}
2072
1617
/* srd & srd. */
2073
GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2074
{
2075
TCGv t0;
2076
int l1, l2;
2077
l1 = gen_new_label();
2078
l2 = gen_new_label();
2079
2080
t0 = tcg_temp_local_new(TCG_TYPE_TL);
2081
tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2082
tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
2083
tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2084
tcg_gen_br(l2);
2085
gen_set_label(l1);
2086
tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
2087
gen_set_label(l2);
2088
tcg_temp_free(t0);
2089
if (unlikely(Rc(ctx->opcode) != 0))
2090
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2091
}
1618
__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
2092
1619
#endif
2093
1620
2094
1621
/*** Floating-Point arithmetic ***/
2095
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1622
#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, type) \
2096
1623
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
2097
1624
{ \
2098
1625
if (unlikely(!ctx->fpu_enabled)) { \
2099
1626
GEN_EXCP_NO_FP(ctx); \
2100
1627
return; \
2101
1628
} \
2102
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
2103
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
2104
tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
2105
gen_reset_fpstatus(); \
2106
gen_op_f##op(); \
2107
if (isfloat) { \
2108
gen_op_frsp(); \
2109
} \
2110
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2111
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
2112
}
2113
2114
#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2115
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2116
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2117
2118
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2119
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2120
{ \
2121
if (unlikely(!ctx->fpu_enabled)) { \
2122
GEN_EXCP_NO_FP(ctx); \
2123
return; \
2124
} \
2125
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
2126
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
2127
gen_reset_fpstatus(); \
2128
gen_op_f##op(); \
2129
if (isfloat) { \
2130
gen_op_frsp(); \
2131
} \
2132
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2133
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
2134
}
2135
#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2136
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2137
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2138
2139
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2140
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
2141
{ \
2142
if (unlikely(!ctx->fpu_enabled)) { \
2143
GEN_EXCP_NO_FP(ctx); \
2144
return; \
2145
} \
2146
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
2147
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
2148
gen_reset_fpstatus(); \
2149
gen_op_f##op(); \
2150
if (isfloat) { \
2151
gen_op_frsp(); \
2152
} \
2153
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2154
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
2155
}
2156
#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2157
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2158
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2159
2160
#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1629
gen_op_reset_scrfx(); \
1630
gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1631
gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1632
gen_op_load_fpr_FT2(rB(ctx->opcode)); \
1633
gen_op_f##op(); \
1634
if (isfloat) { \
1635
gen_op_frsp(); \
1636
} \
1637
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1638
if (unlikely(Rc(ctx->opcode) != 0)) \
1639
gen_op_set_Rc1(); \
1640
}
1641
1642
#define GEN_FLOAT_ACB(name, op2, type) \
1643
_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, type); \
1644
_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, type);
1645
1646
#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat) \
1647
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
1648
{ \
1649
if (unlikely(!ctx->fpu_enabled)) { \
1650
GEN_EXCP_NO_FP(ctx); \
1651
return; \
1652
} \
1653
gen_op_reset_scrfx(); \
1654
gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1655
gen_op_load_fpr_FT1(rB(ctx->opcode)); \
1656
gen_op_f##op(); \
1657
if (isfloat) { \
1658
gen_op_frsp(); \
1659
} \
1660
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1661
if (unlikely(Rc(ctx->opcode) != 0)) \
1662
gen_op_set_Rc1(); \
1663
}
1664
#define GEN_FLOAT_AB(name, op2, inval) \
1665
_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0); \
1666
_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1);
1667
1668
#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat) \
1669
GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
1670
{ \
1671
if (unlikely(!ctx->fpu_enabled)) { \
1672
GEN_EXCP_NO_FP(ctx); \
1673
return; \
1674
} \
1675
gen_op_reset_scrfx(); \
1676
gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1677
gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1678
gen_op_f##op(); \
1679
if (isfloat) { \
1680
gen_op_frsp(); \
1681
} \
1682
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1683
if (unlikely(Rc(ctx->opcode) != 0)) \
1684
gen_op_set_Rc1(); \
1685
}
1686
#define GEN_FLOAT_AC(name, op2, inval) \
1687
_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0); \
1688
_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1);
1689
1690
#define GEN_FLOAT_B(name, op2, op3, type) \
2161
1691
GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
2162
1692
{ \
2163
1693
if (unlikely(!ctx->fpu_enabled)) { \
2164
1694
GEN_EXCP_NO_FP(ctx); \
2165
1695
return; \
2166
1696
} \
2167
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
2168
gen_reset_fpstatus(); \
1697
gen_op_reset_scrfx(); \
1698
gen_op_load_fpr_FT0(rB(ctx->opcode)); \
2169
1699
gen_op_f##name(); \
2170
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2171
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1700
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1701
if (unlikely(Rc(ctx->opcode) != 0)) \
1702
gen_op_set_Rc1(); \
2172
1703
}
2173
1704
2174
#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
1705
#define GEN_FLOAT_BS(name, op1, op2, type) \
2175
1706
GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
2176
1707
{ \
2177
1708
if (unlikely(!ctx->fpu_enabled)) { \
2178
1709
GEN_EXCP_NO_FP(ctx); \
2179
1710
return; \
2180
1711
} \
2181
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
2182
gen_reset_fpstatus(); \
1712
gen_op_reset_scrfx(); \
1713
gen_op_load_fpr_FT0(rB(ctx->opcode)); \
2183
1714
gen_op_f##name(); \
2184
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2185
gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
1715
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
1716
if (unlikely(Rc(ctx->opcode) != 0)) \
1717
gen_op_set_Rc1(); \
2186
1718
}
2187
1719
2188
1720
/* fadd - fadds */
2189
GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
1721
GEN_FLOAT_AB(add, 0x15, 0x000007C0);
2190
1722
/* fdiv - fdivs */
2191
GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
1723
GEN_FLOAT_AB(div, 0x12, 0x000007C0);
2192
1724
/* fmul - fmuls */
2193
GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
1725
GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
2194
1726
2195
1727
/* fre */
2196
GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
1728
GEN_FLOAT_BS(re, 0x3F, 0x18, PPC_FLOAT_EXT);
2197
1729
2198
1730
/* fres */
2199
GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
1731
GEN_FLOAT_BS(res, 0x3B, 0x18, PPC_FLOAT_FRES);
2200
1732
2201
1733
/* frsqrte */
2202
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2203
2204
/* frsqrtes */
2205
static always_inline void gen_op_frsqrtes (void)
2206
{
2207
gen_op_frsqrte();
2208
gen_op_frsp();
2209
}
2210
GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
1734
GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, PPC_FLOAT_FRSQRTE);
2211
1735
2212
1736
/* fsel */
2213
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
1737
_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, PPC_FLOAT_FSEL);
2214
1738
/* fsub - fsubs */
2215
GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
1739
GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
2216
1740
/* Optional: */
2217
1741
/* fsqrt */
2218
1742
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2221
1745
GEN_EXCP_NO_FP(ctx);
2222
1746
return;
2223
1747
}
2224
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2225
gen_reset_fpstatus();
1748
gen_op_reset_scrfx();
1749
gen_op_load_fpr_FT0(rB(ctx->opcode));
2226
1750
gen_op_fsqrt();
2227
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
2228
gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1751
gen_op_store_FT0_fpr(rD(ctx->opcode));
1752
if (unlikely(Rc(ctx->opcode) != 0))
1753
gen_op_set_Rc1();
2229
1754
}
2230
1755
2231
1756
GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
2234
1759
GEN_EXCP_NO_FP(ctx);
2235
1760
return;
2236
1761
}
2237
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2238
gen_reset_fpstatus();
1762
gen_op_reset_scrfx();
1763
gen_op_load_fpr_FT0(rB(ctx->opcode));
2239
1764
gen_op_fsqrt();
2240
1765
gen_op_frsp();
2241
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
2242
gen_compute_fprf(1, Rc(ctx->opcode) != 0);
1766
gen_op_store_FT0_fpr(rD(ctx->opcode));
1767
if (unlikely(Rc(ctx->opcode) != 0))
1768
gen_op_set_Rc1();
2243
1769
}
2244
1770
2245
1771
/*** Floating-Point multiply-and-add ***/
2246
1772
/* fmadd - fmadds */
2247
GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
1773
GEN_FLOAT_ACB(madd, 0x1D, PPC_FLOAT);
2248
1774
/* fmsub - fmsubs */
2249
GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
1775
GEN_FLOAT_ACB(msub, 0x1C, PPC_FLOAT);
2250
1776
/* fnmadd - fnmadds */
2251
GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
1777
GEN_FLOAT_ACB(nmadd, 0x1F, PPC_FLOAT);
2252
1778
/* fnmsub - fnmsubs */
2253
GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
1779
GEN_FLOAT_ACB(nmsub, 0x1E, PPC_FLOAT);
2254
1780
2255
1781
/*** Floating-Point round & convert ***/
2256
1782
/* fctiw */
2257
GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
1783
GEN_FLOAT_B(ctiw, 0x0E, 0x00, PPC_FLOAT);
2258
1784
/* fctiwz */
2259
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
1785
GEN_FLOAT_B(ctiwz, 0x0F, 0x00, PPC_FLOAT);
2260
1786
/* frsp */
2261
GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
1787
GEN_FLOAT_B(rsp, 0x0C, 0x00, PPC_FLOAT);
2262
1788
#if defined(TARGET_PPC64)
2263
1789
/* fcfid */
2264
GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
1790
GEN_FLOAT_B(cfid, 0x0E, 0x1A, PPC_64B);
2265
1791
/* fctid */
2266
GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
1792
GEN_FLOAT_B(ctid, 0x0E, 0x19, PPC_64B);
2267
1793
/* fctidz */
2268
GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
1794
GEN_FLOAT_B(ctidz, 0x0F, 0x19, PPC_64B);
2269
1795
#endif
2270
1796
2271
1797
/* frin */
2272
GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
1798
GEN_FLOAT_B(rin, 0x08, 0x0C, PPC_FLOAT_EXT);
2273
1799
/* friz */
2274
GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
1800
GEN_FLOAT_B(riz, 0x08, 0x0D, PPC_FLOAT_EXT);
2275
1801
/* frip */
2276
GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
1802
GEN_FLOAT_B(rip, 0x08, 0x0E, PPC_FLOAT_EXT);
2277
1803
/* frim */
2278
GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
1804
GEN_FLOAT_B(rim, 0x08, 0x0F, PPC_FLOAT_EXT);
2279
1805
2280
1806
/*** Floating-Point compare ***/
2281
1807
/* fcmpo */
2285
1811
GEN_EXCP_NO_FP(ctx);
2286
1812
return;
2287
1813
}
2288
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2289
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
2290
gen_reset_fpstatus();
2291
tcg_gen_helper_1_0(helper_fcmpo, cpu_crf[crfD(ctx->opcode)]);
2292
gen_op_float_check_status();
1814
gen_op_reset_scrfx();
1815
gen_op_load_fpr_FT0(rA(ctx->opcode));
1816
gen_op_load_fpr_FT1(rB(ctx->opcode));
1817
gen_op_fcmpo();
1818
gen_op_store_T0_crf(crfD(ctx->opcode));
2293
1819
}
2294
1820
2295
1821
/* fcmpu */
2299
1825
GEN_EXCP_NO_FP(ctx);
2300
1826
return;
2301
1827
}
2302
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2303
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
2304
gen_reset_fpstatus();
2305
tcg_gen_helper_1_0(helper_fcmpu, cpu_crf[crfD(ctx->opcode)]);
2306
gen_op_float_check_status();
1828
gen_op_reset_scrfx();
1829
gen_op_load_fpr_FT0(rA(ctx->opcode));
1830
gen_op_load_fpr_FT1(rB(ctx->opcode));
1831
gen_op_fcmpu();
1832
gen_op_store_T0_crf(crfD(ctx->opcode));
2307
1833
}
2308
1834
2309
1835
/*** Floating-point move ***/
2310
1836
/* fabs */
2311
/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2312
GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
1837
GEN_FLOAT_B(abs, 0x08, 0x08, PPC_FLOAT);
2313
1838
2314
1839
/* fmr - fmr. */
2315
/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2316
1840
GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2317
1841
{
2318
1842
if (unlikely(!ctx->fpu_enabled)) {
2319
1843
GEN_EXCP_NO_FP(ctx);
2320
1844
return;
2321
1845
}
2322
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2323
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
2324
gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1846
gen_op_reset_scrfx();
1847
gen_op_load_fpr_FT0(rB(ctx->opcode));
1848
gen_op_store_FT0_fpr(rD(ctx->opcode));
1849
if (unlikely(Rc(ctx->opcode) != 0))
1850
gen_op_set_Rc1();
2325
1851
}
2326
1852
2327
1853
/* fnabs */
2328
/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2329
GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
1854
GEN_FLOAT_B(nabs, 0x08, 0x04, PPC_FLOAT);
2330
1855
/* fneg */
2331
/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2332
GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
1856
GEN_FLOAT_B(neg, 0x08, 0x01, PPC_FLOAT);
2333
1857
2334
1858
/*** Floating-Point status & ctrl register ***/
2335
1859
/* mcrfs */
2336
1860
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2337
1861
{
2338
int bfa;
2339
2340
1862
if (unlikely(!ctx->fpu_enabled)) {
2341
1863
GEN_EXCP_NO_FP(ctx);
2342
1864
return;
2343
1865
}
2344
gen_optimize_fprf();
2345
bfa = 4 * (7 - crfS(ctx->opcode));
2346
tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2347
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2348
gen_op_fpscr_resetbit(~(0xF << bfa));
1866
gen_op_load_fpscr_T0(crfS(ctx->opcode));
1867
gen_op_store_T0_crf(crfD(ctx->opcode));
1868
gen_op_clear_fpscr(crfS(ctx->opcode));
2349
1869
}
2350
1870
2351
1871
/* mffs */
2355
1875
GEN_EXCP_NO_FP(ctx);
2356
1876
return;
2357
1877
}
2358
gen_optimize_fprf();
2359
gen_reset_fpstatus();
2360
gen_op_load_fpscr_FT0();
2361
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
2362
gen_compute_fprf(0, Rc(ctx->opcode) != 0);
1878
gen_op_load_fpscr();
1879
gen_op_store_FT0_fpr(rD(ctx->opcode));
1880
if (unlikely(Rc(ctx->opcode) != 0))
1881
gen_op_set_Rc1();
2363
1882
}
2364
1883
2365
1884
/* mtfsb0 */
2371
1890
GEN_EXCP_NO_FP(ctx);
2372
1891
return;
2373
1892
}
2374
crb = 32 - (crbD(ctx->opcode) >> 2);
2375
gen_optimize_fprf();
2376
gen_reset_fpstatus();
2377
if (likely(crb != 30 && crb != 29))
2378
gen_op_fpscr_resetbit(~(1 << crb));
2379
if (unlikely(Rc(ctx->opcode) != 0)) {
2380
tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2381
}
1893
crb = crbD(ctx->opcode) >> 2;
1894
gen_op_load_fpscr_T0(crb);
1895
gen_op_andi_T0(~(1 << (crbD(ctx->opcode) & 0x03)));
1896
gen_op_store_T0_fpscr(crb);
1897
if (unlikely(Rc(ctx->opcode) != 0))
1898
gen_op_set_Rc1();
2382
1899
}
2383
1900
2384
1901
/* mtfsb1 */
2390
1907
GEN_EXCP_NO_FP(ctx);
2391
1908
return;
2392
1909
}
2393
crb = 32 - (crbD(ctx->opcode) >> 2);
2394
gen_optimize_fprf();
2395
gen_reset_fpstatus();
2396
/* XXX: we pretend we can only do IEEE floating-point computations */
2397
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2398
gen_op_fpscr_setbit(crb);
2399
if (unlikely(Rc(ctx->opcode) != 0)) {
2400
tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2401
}
2402
/* We can raise a differed exception */
2403
gen_op_float_check_status();
1910
crb = crbD(ctx->opcode) >> 2;
1911
gen_op_load_fpscr_T0(crb);
1912
gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
1913
gen_op_store_T0_fpscr(crb);
1914
if (unlikely(Rc(ctx->opcode) != 0))
1915
gen_op_set_Rc1();
2404
1916
}
2405
1917
2406
1918
/* mtfsf */
2410
1922
GEN_EXCP_NO_FP(ctx);
2411
1923
return;
2412
1924
}
2413
gen_optimize_fprf();
2414
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2415
gen_reset_fpstatus();
1925
gen_op_load_fpr_FT0(rB(ctx->opcode));
2416
1926
gen_op_store_fpscr(FM(ctx->opcode));
2417
if (unlikely(Rc(ctx->opcode) != 0)) {
2418
tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2419
}
2420
/* We can raise a differed exception */
2421
gen_op_float_check_status();
1927
if (unlikely(Rc(ctx->opcode) != 0))
1928
gen_op_set_Rc1();
2422
1929
}
2423
1930
2424
1931
/* mtfsfi */
2425
1932
GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2426
1933
{
2427
int bf, sh;
2428
2429
1934
if (unlikely(!ctx->fpu_enabled)) {
2430
1935
GEN_EXCP_NO_FP(ctx);
2431
1936
return;
2432
1937
}
2433
bf = crbD(ctx->opcode) >> 2;
2434
sh = 7 - bf;
2435
gen_optimize_fprf();
2436
tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh));
2437
gen_reset_fpstatus();
2438
gen_op_store_fpscr(1 << sh);
2439
if (unlikely(Rc(ctx->opcode) != 0)) {
2440
tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
2441
}
2442
/* We can raise a differed exception */
2443
gen_op_float_check_status();
1938
gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
1939
if (unlikely(Rc(ctx->opcode) != 0))
1940
gen_op_set_Rc1();
2444
1941
}
2445
1942
2446
1943
/*** Addressing modes ***/
2447
1944
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
2448
static always_inline void gen_addr_imm_index (TCGv EA,
2449
DisasContext *ctx,
1945
static always_inline void gen_addr_imm_index (DisasContext *ctx,
2450
1946
target_long maskl)
2451
1947
{
2452
1948
target_long simm = SIMM(ctx->opcode);
2453
1949
2454
1950
simm &= ~maskl;
2455
if (rA(ctx->opcode) == 0)
2456
tcg_gen_movi_tl(EA, simm);
2457
else if (likely(simm != 0))
2458
tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2459
else
2460
tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2461
}
2462
2463
static always_inline void gen_addr_reg_index (TCGv EA,
2464
DisasContext *ctx)
2465
{
2466
if (rA(ctx->opcode) == 0)
2467
tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2468
else
2469
tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2470
}
2471
2472
static always_inline void gen_addr_register (TCGv EA,
2473
DisasContext *ctx)
2474
{
2475
if (rA(ctx->opcode) == 0)
2476
tcg_gen_movi_tl(EA, 0);
2477
else
2478
tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2479
}
2480
2481
#if defined(TARGET_PPC64)
2482
#define _GEN_MEM_FUNCS(name, mode) \
2483
&gen_op_##name##_##mode, \
2484
&gen_op_##name##_le_##mode, \
2485
&gen_op_##name##_64_##mode, \
2486
&gen_op_##name##_le_64_##mode
2487
#else
2488
#define _GEN_MEM_FUNCS(name, mode) \
2489
&gen_op_##name##_##mode, \
2490
&gen_op_##name##_le_##mode
2491
#endif
2492
#if defined(CONFIG_USER_ONLY)
2493
#if defined(TARGET_PPC64)
2494
#define NB_MEM_FUNCS 4
2495
#else
2496
#define NB_MEM_FUNCS 2
2497
#endif
2498
#define GEN_MEM_FUNCS(name) \
2499
_GEN_MEM_FUNCS(name, raw)
2500
#else
2501
#if defined(TARGET_PPC64)
2502
#define NB_MEM_FUNCS 12
2503
#else
2504
#define NB_MEM_FUNCS 6
2505
#endif
2506
#define GEN_MEM_FUNCS(name) \
2507
_GEN_MEM_FUNCS(name, user), \
2508
_GEN_MEM_FUNCS(name, kernel), \
2509
_GEN_MEM_FUNCS(name, hypv)
2510
#endif
1951
if (rA(ctx->opcode) == 0) {
1952
gen_set_T0(simm);
1953
} else {
1954
gen_op_load_gpr_T0(rA(ctx->opcode));
1955
if (likely(simm != 0))
1956
gen_op_addi(simm);
1957
}
1958
#ifdef DEBUG_MEMORY_ACCESSES
1959
gen_op_print_mem_EA();
1960
#endif
1961
}
1962
1963
static always_inline void gen_addr_reg_index (DisasContext *ctx)
1964
{
1965
if (rA(ctx->opcode) == 0) {
1966
gen_op_load_gpr_T0(rB(ctx->opcode));
1967
} else {
1968
gen_op_load_gpr_T0(rA(ctx->opcode));
1969
gen_op_load_gpr_T1(rB(ctx->opcode));
1970
gen_op_add();
1971
}
1972
#ifdef DEBUG_MEMORY_ACCESSES
1973
gen_op_print_mem_EA();
1974
#endif
1975
}
1976
1977
static always_inline void gen_addr_register (DisasContext *ctx)
1978
{
1979
if (rA(ctx->opcode) == 0) {
1980
gen_op_reset_T0();
1981
} else {
1982
gen_op_load_gpr_T0(rA(ctx->opcode));
1983
}
1984
#ifdef DEBUG_MEMORY_ACCESSES
1985
gen_op_print_mem_EA();
1986
#endif
1987
}
2511
1988
2512
1989
/*** Integer load ***/
2513
1990
#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
2514
#define OP_LD_TABLE(width) \
2515
static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2516
GEN_MEM_FUNCS(l##width), \
2517
};
2518
#define OP_ST_TABLE(width) \
2519
static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2520
GEN_MEM_FUNCS(st##width), \
2521
};
2522
2523
2524
#if defined(TARGET_PPC64)
2525
#define GEN_QEMU_LD_PPC64(width) \
2526
static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2527
{ \
2528
if (likely(flags & 2)) \
2529
tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2530
else { \
2531
TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2532
tcg_gen_ext32u_tl(addr, t1); \
2533
tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2534
tcg_temp_free(addr); \
2535
} \
2536
}
2537
GEN_QEMU_LD_PPC64(8u)
2538
GEN_QEMU_LD_PPC64(8s)
2539
GEN_QEMU_LD_PPC64(16u)
2540
GEN_QEMU_LD_PPC64(16s)
2541
GEN_QEMU_LD_PPC64(32u)
2542
GEN_QEMU_LD_PPC64(32s)
2543
GEN_QEMU_LD_PPC64(64)
2544
2545
#define GEN_QEMU_ST_PPC64(width) \
2546
static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2547
{ \
2548
if (likely(flags & 2)) \
2549
tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2550
else { \
2551
TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2552
tcg_gen_ext32u_tl(addr, t1); \
2553
tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2554
tcg_temp_free(addr); \
2555
} \
2556
}
2557
GEN_QEMU_ST_PPC64(8)
2558
GEN_QEMU_ST_PPC64(16)
2559
GEN_QEMU_ST_PPC64(32)
2560
GEN_QEMU_ST_PPC64(64)
2561
2562
static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
2563
{
2564
gen_qemu_ld8u_ppc64(arg0, arg1, flags);
2565
}
2566
2567
static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
2568
{
2569
gen_qemu_ld8s_ppc64(arg0, arg1, flags);
2570
}
2571
2572
static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
2573
{
2574
if (unlikely(flags & 1)) {
2575
TCGv t0;
2576
gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2577
t0 = tcg_temp_new(TCG_TYPE_I32);
2578
tcg_gen_trunc_tl_i32(t0, arg0);
2579
tcg_gen_bswap16_i32(t0, t0);
2580
tcg_gen_extu_i32_tl(arg0, t0);
2581
tcg_temp_free(t0);
2582
} else
2583
gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2584
}
2585
2586
static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
2587
{
2588
if (unlikely(flags & 1)) {
2589
TCGv t0;
2590
gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2591
t0 = tcg_temp_new(TCG_TYPE_I32);
2592
tcg_gen_trunc_tl_i32(t0, arg0);
2593
tcg_gen_bswap16_i32(t0, t0);
2594
tcg_gen_extu_i32_tl(arg0, t0);
2595
tcg_gen_ext16s_tl(arg0, arg0);
2596
tcg_temp_free(t0);
2597
} else
2598
gen_qemu_ld16s_ppc64(arg0, arg1, flags);
2599
}
2600
2601
static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
2602
{
2603
if (unlikely(flags & 1)) {
2604
TCGv t0;
2605
gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2606
t0 = tcg_temp_new(TCG_TYPE_I32);
2607
tcg_gen_trunc_tl_i32(t0, arg0);
2608
tcg_gen_bswap_i32(t0, t0);
2609
tcg_gen_extu_i32_tl(arg0, t0);
2610
tcg_temp_free(t0);
2611
} else
2612
gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2613
}
2614
2615
static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
2616
{
2617
if (unlikely(flags & 1)) {
2618
TCGv t0;
2619
gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2620
t0 = tcg_temp_new(TCG_TYPE_I32);
2621
tcg_gen_trunc_tl_i32(t0, arg0);
2622
tcg_gen_bswap_i32(t0, t0);
2623
tcg_gen_ext_i32_tl(arg0, t0);
2624
tcg_temp_free(t0);
2625
} else
2626
gen_qemu_ld32s_ppc64(arg0, arg1, flags);
2627
}
2628
2629
static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
2630
{
2631
gen_qemu_ld64_ppc64(arg0, arg1, flags);
2632
if (unlikely(flags & 1))
2633
tcg_gen_bswap_i64(arg0, arg0);
2634
}
2635
2636
static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
2637
{
2638
gen_qemu_st8_ppc64(arg0, arg1, flags);
2639
}
2640
2641
static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
2642
{
2643
if (unlikely(flags & 1)) {
2644
TCGv t0, t1;
2645
t0 = tcg_temp_new(TCG_TYPE_I32);
2646
tcg_gen_trunc_tl_i32(t0, arg0);
2647
tcg_gen_ext16u_i32(t0, t0);
2648
tcg_gen_bswap16_i32(t0, t0);
2649
t1 = tcg_temp_new(TCG_TYPE_I64);
2650
tcg_gen_extu_i32_tl(t1, t0);
2651
tcg_temp_free(t0);
2652
gen_qemu_st16_ppc64(t1, arg1, flags);
2653
tcg_temp_free(t1);
2654
} else
2655
gen_qemu_st16_ppc64(arg0, arg1, flags);
2656
}
2657
2658
static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
2659
{
2660
if (unlikely(flags & 1)) {
2661
TCGv t0, t1;
2662
t0 = tcg_temp_new(TCG_TYPE_I32);
2663
tcg_gen_trunc_tl_i32(t0, arg0);
2664
tcg_gen_bswap_i32(t0, t0);
2665
t1 = tcg_temp_new(TCG_TYPE_I64);
2666
tcg_gen_extu_i32_tl(t1, t0);
2667
tcg_temp_free(t0);
2668
gen_qemu_st32_ppc64(t1, arg1, flags);
2669
tcg_temp_free(t1);
2670
} else
2671
gen_qemu_st32_ppc64(arg0, arg1, flags);
2672
}
2673
2674
static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
2675
{
2676
if (unlikely(flags & 1)) {
2677
TCGv t0 = tcg_temp_new(TCG_TYPE_I64);
2678
tcg_gen_bswap_i64(t0, arg0);
2679
gen_qemu_st64_ppc64(t0, arg1, flags);
2680
tcg_temp_free(t0);
2681
} else
2682
gen_qemu_st64_ppc64(arg0, arg1, flags);
2683
}
2684
2685
2686
#else /* defined(TARGET_PPC64) */
2687
#define GEN_QEMU_LD_PPC32(width) \
2688
static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
2689
{ \
2690
tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
2691
}
2692
GEN_QEMU_LD_PPC32(8u)
2693
GEN_QEMU_LD_PPC32(8s)
2694
GEN_QEMU_LD_PPC32(16u)
2695
GEN_QEMU_LD_PPC32(16s)
2696
GEN_QEMU_LD_PPC32(32u)
2697
GEN_QEMU_LD_PPC32(32s)
2698
GEN_QEMU_LD_PPC32(64)
2699
2700
#define GEN_QEMU_ST_PPC32(width) \
2701
static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
2702
{ \
2703
tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
2704
}
2705
GEN_QEMU_ST_PPC32(8)
2706
GEN_QEMU_ST_PPC32(16)
2707
GEN_QEMU_ST_PPC32(32)
2708
GEN_QEMU_ST_PPC32(64)
2709
2710
static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
2711
{
2712
gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
2713
}
2714
2715
static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
2716
{
2717
gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
2718
}
2719
2720
static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
2721
{
2722
gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
2723
if (unlikely(flags & 1))
2724
tcg_gen_bswap16_i32(arg0, arg0);
2725
}
2726
2727
static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
2728
{
2729
if (unlikely(flags & 1)) {
2730
gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2731
tcg_gen_bswap16_i32(arg0, arg0);
2732
tcg_gen_ext16s_i32(arg0, arg0);
2733
} else
2734
gen_qemu_ld16s_ppc32(arg0, arg1, flags);
2735
}
2736
2737
static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
2738
{
2739
gen_qemu_ld32u_ppc32(arg0, arg1, flags);
2740
if (unlikely(flags & 1))
2741
tcg_gen_bswap_i32(arg0, arg0);
2742
}
2743
2744
static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
2745
{
2746
gen_qemu_ld64_ppc32(arg0, arg1, flags);
2747
if (unlikely(flags & 1))
2748
tcg_gen_bswap_i64(arg0, arg0);
2749
}
2750
2751
static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
2752
{
2753
gen_qemu_st8_ppc32(arg0, arg1, flags);
2754
}
2755
2756
static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
2757
{
2758
if (unlikely(flags & 1)) {
2759
TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2760
tcg_gen_ext16u_i32(temp, arg0);
2761
tcg_gen_bswap16_i32(temp, temp);
2762
gen_qemu_st16_ppc32(temp, arg1, flags);
2763
tcg_temp_free(temp);
2764
} else
2765
gen_qemu_st16_ppc32(arg0, arg1, flags);
2766
}
2767
2768
static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
2769
{
2770
if (unlikely(flags & 1)) {
2771
TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2772
tcg_gen_bswap_i32(temp, arg0);
2773
gen_qemu_st32_ppc32(temp, arg1, flags);
2774
tcg_temp_free(temp);
2775
} else
2776
gen_qemu_st32_ppc32(arg0, arg1, flags);
2777
}
2778
2779
static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
2780
{
2781
if (unlikely(flags & 1)) {
2782
TCGv temp = tcg_temp_new(TCG_TYPE_I64);
2783
tcg_gen_bswap_i64(temp, arg0);
2784
gen_qemu_st64_ppc32(temp, arg1, flags);
2785
tcg_temp_free(temp);
2786
} else
2787
gen_qemu_st64_ppc32(arg0, arg1, flags);
2788
}
2789
1991
#if defined(CONFIG_USER_ONLY)
1992
#if defined(TARGET_PPC64)
1993
/* User mode only - 64 bits */
1994
#define OP_LD_TABLE(width) \
1995
static GenOpFunc *gen_op_l##width[] = { \
1996
&gen_op_l##width##_raw, \
1997
&gen_op_l##width##_le_raw, \
1998
&gen_op_l##width##_64_raw, \
1999
&gen_op_l##width##_le_64_raw, \
2000
};
2001
#define OP_ST_TABLE(width) \
2002
static GenOpFunc *gen_op_st##width[] = { \
2003
&gen_op_st##width##_raw, \
2004
&gen_op_st##width##_le_raw, \
2005
&gen_op_st##width##_64_raw, \
2006
&gen_op_st##width##_le_64_raw, \
2007
};
2008
/* Byte access routine are endian safe */
2009
#define gen_op_stb_le_64_raw gen_op_stb_64_raw
2010
#define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2011
#else
2012
/* User mode only - 32 bits */
2013
#define OP_LD_TABLE(width) \
2014
static GenOpFunc *gen_op_l##width[] = { \
2015
&gen_op_l##width##_raw, \
2016
&gen_op_l##width##_le_raw, \
2017
};
2018
#define OP_ST_TABLE(width) \
2019
static GenOpFunc *gen_op_st##width[] = { \
2020
&gen_op_st##width##_raw, \
2021
&gen_op_st##width##_le_raw, \
2022
};
2023
#endif
2024
/* Byte access routine are endian safe */
2025
#define gen_op_stb_le_raw gen_op_stb_raw
2026
#define gen_op_lbz_le_raw gen_op_lbz_raw
2027
#else
2028
#if defined(TARGET_PPC64)
2029
#if defined(TARGET_PPC64H)
2030
/* Full system - 64 bits with hypervisor mode */
2031
#define OP_LD_TABLE(width) \
2032
static GenOpFunc *gen_op_l##width[] = { \
2033
&gen_op_l##width##_user, \
2034
&gen_op_l##width##_le_user, \
2035
&gen_op_l##width##_64_user, \
2036
&gen_op_l##width##_le_64_user, \
2037
&gen_op_l##width##_kernel, \
2038
&gen_op_l##width##_le_kernel, \
2039
&gen_op_l##width##_64_kernel, \
2040
&gen_op_l##width##_le_64_kernel, \
2041
&gen_op_l##width##_hypv, \
2042
&gen_op_l##width##_le_hypv, \
2043
&gen_op_l##width##_64_hypv, \
2044
&gen_op_l##width##_le_64_hypv, \
2045
};
2046
#define OP_ST_TABLE(width) \
2047
static GenOpFunc *gen_op_st##width[] = { \
2048
&gen_op_st##width##_user, \
2049
&gen_op_st##width##_le_user, \
2050
&gen_op_st##width##_64_user, \
2051
&gen_op_st##width##_le_64_user, \
2052
&gen_op_st##width##_kernel, \
2053
&gen_op_st##width##_le_kernel, \
2054
&gen_op_st##width##_64_kernel, \
2055
&gen_op_st##width##_le_64_kernel, \
2056
&gen_op_st##width##_hypv, \
2057
&gen_op_st##width##_le_hypv, \
2058
&gen_op_st##width##_64_hypv, \
2059
&gen_op_st##width##_le_64_hypv, \
2060
};
2061
/* Byte access routine are endian safe */
2062
#define gen_op_stb_le_hypv gen_op_stb_64_hypv
2063
#define gen_op_lbz_le_hypv gen_op_lbz_64_hypv
2064
#define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
2065
#define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2066
#else
2067
/* Full system - 64 bits */
2068
#define OP_LD_TABLE(width) \
2069
static GenOpFunc *gen_op_l##width[] = { \
2070
&gen_op_l##width##_user, \
2071
&gen_op_l##width##_le_user, \
2072
&gen_op_l##width##_64_user, \
2073
&gen_op_l##width##_le_64_user, \
2074
&gen_op_l##width##_kernel, \
2075
&gen_op_l##width##_le_kernel, \
2076
&gen_op_l##width##_64_kernel, \
2077
&gen_op_l##width##_le_64_kernel, \
2078
};
2079
#define OP_ST_TABLE(width) \
2080
static GenOpFunc *gen_op_st##width[] = { \
2081
&gen_op_st##width##_user, \
2082
&gen_op_st##width##_le_user, \
2083
&gen_op_st##width##_64_user, \
2084
&gen_op_st##width##_le_64_user, \
2085
&gen_op_st##width##_kernel, \
2086
&gen_op_st##width##_le_kernel, \
2087
&gen_op_st##width##_64_kernel, \
2088
&gen_op_st##width##_le_64_kernel, \
2089
};
2090
#endif
2091
/* Byte access routine are endian safe */
2092
#define gen_op_stb_le_64_user gen_op_stb_64_user
2093
#define gen_op_lbz_le_64_user gen_op_lbz_64_user
2094
#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2095
#define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2096
#else
2097
/* Full system - 32 bits */
2098
#define OP_LD_TABLE(width) \
2099
static GenOpFunc *gen_op_l##width[] = { \
2100
&gen_op_l##width##_user, \
2101
&gen_op_l##width##_le_user, \
2102
&gen_op_l##width##_kernel, \
2103
&gen_op_l##width##_le_kernel, \
2104
};
2105
#define OP_ST_TABLE(width) \
2106
static GenOpFunc *gen_op_st##width[] = { \
2107
&gen_op_st##width##_user, \
2108
&gen_op_st##width##_le_user, \
2109
&gen_op_st##width##_kernel, \
2110
&gen_op_st##width##_le_kernel, \
2111
};
2112
#endif
2113
/* Byte access routine are endian safe */
2114
#define gen_op_stb_le_user gen_op_stb_user
2115
#define gen_op_lbz_le_user gen_op_lbz_user
2116
#define gen_op_stb_le_kernel gen_op_stb_kernel
2117
#define gen_op_lbz_le_kernel gen_op_lbz_kernel
2790
2118
#endif
2791
2119
2792
2120
#define GEN_LD(width, opc, type) \
2793
2121
GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2794
2122
{ \
2795
TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2796
gen_addr_imm_index(EA, ctx, 0); \
2797
gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2798
tcg_temp_free(EA); \
2123
gen_addr_imm_index(ctx, 0); \
2124
op_ldst(l##width); \
2125
gen_op_store_T1_gpr(rD(ctx->opcode)); \
2799
2126
}
2800
2127
2801
2128
#define GEN_LDU(width, opc, type) \
2802
2129
GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2803
2130
{ \
2804
TCGv EA; \
2805
2131
if (unlikely(rA(ctx->opcode) == 0 || \
2806
2132
rA(ctx->opcode) == rD(ctx->opcode))) { \
2807
2133
GEN_EXCP_INVAL(ctx); \
2808
2134
return; \
2809
2135
} \
2810
EA = tcg_temp_new(TCG_TYPE_TL); \
2811
2136
if (type == PPC_64B) \
2812
gen_addr_imm_index(EA, ctx, 0x03); \
2137
gen_addr_imm_index(ctx, 0x03); \
2813
2138
else \
2814
gen_addr_imm_index(EA, ctx, 0); \
2815
gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2816
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2817
tcg_temp_free(EA); \
2139
gen_addr_imm_index(ctx, 0); \
2140
op_ldst(l##width); \
2141
gen_op_store_T1_gpr(rD(ctx->opcode)); \
2142
gen_op_store_T0_gpr(rA(ctx->opcode)); \
2818
2143
}
2819
2144
2820
2145
#define GEN_LDUX(width, opc2, opc3, type) \
2821
2146
GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2822
2147
{ \
2823
TCGv EA; \
2824
2148
if (unlikely(rA(ctx->opcode) == 0 || \
2825
2149
rA(ctx->opcode) == rD(ctx->opcode))) { \
2826
2150
GEN_EXCP_INVAL(ctx); \
2827
2151
return; \
2828
2152
} \
2829
EA = tcg_temp_new(TCG_TYPE_TL); \
2830
gen_addr_reg_index(EA, ctx); \
2831
gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2832
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2833
tcg_temp_free(EA); \
2153
gen_addr_reg_index(ctx); \
2154
op_ldst(l##width); \
2155
gen_op_store_T1_gpr(rD(ctx->opcode)); \
2156
gen_op_store_T0_gpr(rA(ctx->opcode)); \
2834
2157
}
2835
2158
2836
2159
#define GEN_LDX(width, opc2, opc3, type) \
2837
2160
GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2838
2161
{ \
2839
TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2840
gen_addr_reg_index(EA, ctx); \
2841
gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2842
tcg_temp_free(EA); \
2162
gen_addr_reg_index(ctx); \
2163
op_ldst(l##width); \
2164
gen_op_store_T1_gpr(rD(ctx->opcode)); \
2843
2165
}
2844
2166
2845
2167
#define GEN_LDS(width, op, type) \
2168
OP_LD_TABLE(width); \
2846
2169
GEN_LD(width, op | 0x20, type); \
2847
2170
GEN_LDU(width, op | 0x21, type); \
2848
2171
GEN_LDUX(width, 0x17, op | 0x01, type); \
2849
2172
GEN_LDX(width, 0x17, op | 0x00, type)
2850
2173
2851
2174
/* lbz lbzu lbzux lbzx */
2852
GEN_LDS(8u, 0x02, PPC_INTEGER);
2175
GEN_LDS(bz, 0x02, PPC_INTEGER);
2853
2176
/* lha lhau lhaux lhax */
2854
GEN_LDS(16s, 0x0A, PPC_INTEGER);
2177
GEN_LDS(ha, 0x0A, PPC_INTEGER);
2855
2178
/* lhz lhzu lhzux lhzx */
2856
GEN_LDS(16u, 0x08, PPC_INTEGER);
2179
GEN_LDS(hz, 0x08, PPC_INTEGER);
2857
2180
/* lwz lwzu lwzux lwzx */
2858
GEN_LDS(32u, 0x00, PPC_INTEGER);
2181
GEN_LDS(wz, 0x00, PPC_INTEGER);
2859
2182
#if defined(TARGET_PPC64)
2183
OP_LD_TABLE(wa);
2184
OP_LD_TABLE(d);
2860
2185
/* lwaux */
2861
GEN_LDUX(32s, 0x15, 0x0B, PPC_64B);
2186
GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2862
2187
/* lwax */
2863
GEN_LDX(32s, 0x15, 0x0A, PPC_64B);
2188
GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2864
2189
/* ldux */
2865
GEN_LDUX(64, 0x15, 0x01, PPC_64B);
2190
GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2866
2191
/* ldx */
2867
GEN_LDX(64, 0x15, 0x00, PPC_64B);
2192
GEN_LDX(d, 0x15, 0x00, PPC_64B);
2868
2193
GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2869
2194
{
2870
TCGv EA;
2871
2195
if (Rc(ctx->opcode)) {
2872
2196
if (unlikely(rA(ctx->opcode) == 0 ||
2873
2197
rA(ctx->opcode) == rD(ctx->opcode))) {
2875
2199
return;
2876
2200
}
2877
2201
}
2878
EA = tcg_temp_new(TCG_TYPE_TL);
2879
gen_addr_imm_index(EA, ctx, 0x03);
2202
gen_addr_imm_index(ctx, 0x03);
2880
2203
if (ctx->opcode & 0x02) {
2881
2204
/* lwa (lwau is undefined) */
2882
gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
2205
op_ldst(lwa);
2883
2206
} else {
2884
2207
/* ld - ldu */
2885
gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
2208
op_ldst(ld);
2886
2209
}
2210
gen_op_store_T1_gpr(rD(ctx->opcode));
2887
2211
if (Rc(ctx->opcode))
2888
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2889
tcg_temp_free(EA);
2212
gen_op_store_T0_gpr(rA(ctx->opcode));
2890
2213
}
2891
2214
/* lq */
2892
2215
GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2895
2218
GEN_EXCP_PRIVOPC(ctx);
2896
2219
#else
2897
2220
int ra, rd;
2898
TCGv EA;
2899
2221
2900
2222
/* Restore CPU state */
2901
2223
if (unlikely(ctx->supervisor == 0)) {
2913
2235
GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2914
2236
return;
2915
2237
}
2916
EA = tcg_temp_new(TCG_TYPE_TL);
2917
gen_addr_imm_index(EA, ctx, 0x0F);
2918
gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2919
tcg_gen_addi_tl(EA, EA, 8);
2920
gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2921
tcg_temp_free(EA);
2238
gen_addr_imm_index(ctx, 0x0F);
2239
op_ldst(ld);
2240
gen_op_store_T1_gpr(rd);
2241
gen_op_addi(8);
2242
op_ldst(ld);
2243
gen_op_store_T1_gpr(rd + 1);
2922
2244
#endif
2923
2245
}
2924
2246
#endif
2927
2249
#define GEN_ST(width, opc, type) \
2928
2250
GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
2929
2251
{ \
2930
TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2931
gen_addr_imm_index(EA, ctx, 0); \
2932
gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2933
tcg_temp_free(EA); \
2252
gen_addr_imm_index(ctx, 0); \
2253
gen_op_load_gpr_T1(rS(ctx->opcode)); \
2254
op_ldst(st##width); \
2934
2255
}
2935
2256
2936
2257
#define GEN_STU(width, opc, type) \
2937
2258
GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
2938
2259
{ \
2939
TCGv EA; \
2940
2260
if (unlikely(rA(ctx->opcode) == 0)) { \
2941
2261
GEN_EXCP_INVAL(ctx); \
2942
2262
return; \
2943
2263
} \
2944
EA = tcg_temp_new(TCG_TYPE_TL); \
2945
2264
if (type == PPC_64B) \
2946
gen_addr_imm_index(EA, ctx, 0x03); \
2265
gen_addr_imm_index(ctx, 0x03); \
2947
2266
else \
2948
gen_addr_imm_index(EA, ctx, 0); \
2949
gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2950
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2951
tcg_temp_free(EA); \
2267
gen_addr_imm_index(ctx, 0); \
2268
gen_op_load_gpr_T1(rS(ctx->opcode)); \
2269
op_ldst(st##width); \
2270
gen_op_store_T0_gpr(rA(ctx->opcode)); \
2952
2271
}
2953
2272
2954
2273
#define GEN_STUX(width, opc2, opc3, type) \
2955
2274
GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
2956
2275
{ \
2957
TCGv EA; \
2958
2276
if (unlikely(rA(ctx->opcode) == 0)) { \
2959
2277
GEN_EXCP_INVAL(ctx); \
2960
2278
return; \
2961
2279
} \
2962
EA = tcg_temp_new(TCG_TYPE_TL); \
2963
gen_addr_reg_index(EA, ctx); \
2964
gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2965
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2966
tcg_temp_free(EA); \
2280
gen_addr_reg_index(ctx); \
2281
gen_op_load_gpr_T1(rS(ctx->opcode)); \
2282
op_ldst(st##width); \
2283
gen_op_store_T0_gpr(rA(ctx->opcode)); \
2967
2284
}
2968
2285
2969
2286
#define GEN_STX(width, opc2, opc3, type) \
2970
2287
GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
2971
2288
{ \
2972
TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2973
gen_addr_reg_index(EA, ctx); \
2974
gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2975
tcg_temp_free(EA); \
2289
gen_addr_reg_index(ctx); \
2290
gen_op_load_gpr_T1(rS(ctx->opcode)); \
2291
op_ldst(st##width); \
2976
2292
}
2977
2293
2978
2294
#define GEN_STS(width, op, type) \
2295
OP_ST_TABLE(width); \
2979
2296
GEN_ST(width, op | 0x20, type); \
2980
2297
GEN_STU(width, op | 0x21, type); \
2981
2298
GEN_STUX(width, 0x17, op | 0x01, type); \
2982
2299
GEN_STX(width, 0x17, op | 0x00, type)
2983
2300
2984
2301
/* stb stbu stbux stbx */
2985
GEN_STS(8, 0x06, PPC_INTEGER);
2302
GEN_STS(b, 0x06, PPC_INTEGER);
2986
2303
/* sth sthu sthux sthx */
2987
GEN_STS(16, 0x0C, PPC_INTEGER);
2304
GEN_STS(h, 0x0C, PPC_INTEGER);
2988
2305
/* stw stwu stwux stwx */
2989
GEN_STS(32, 0x04, PPC_INTEGER);
2306
GEN_STS(w, 0x04, PPC_INTEGER);
2990
2307
#if defined(TARGET_PPC64)
2991
GEN_STUX(64, 0x15, 0x05, PPC_64B);
2992
GEN_STX(64, 0x15, 0x04, PPC_64B);
2308
OP_ST_TABLE(d);
2309
GEN_STUX(d, 0x15, 0x05, PPC_64B);
2310
GEN_STX(d, 0x15, 0x04, PPC_64B);
2993
2311
GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
2994
2312
{
2995
2313
int rs;
2996
TCGv EA;
2997
2314
2998
2315
rs = rS(ctx->opcode);
2999
2316
if ((ctx->opcode & 0x3) == 0x2) {
3014
2331
GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3015
2332
return;
3016
2333
}
3017
EA = tcg_temp_new(TCG_TYPE_TL);
3018
gen_addr_imm_index(EA, ctx, 0x03);
3019
gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3020
tcg_gen_addi_tl(EA, EA, 8);
3021
gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
3022
tcg_temp_free(EA);
2334
gen_addr_imm_index(ctx, 0x03);
2335
gen_op_load_gpr_T1(rs);
2336
op_ldst(std);
2337
gen_op_addi(8);
2338
gen_op_load_gpr_T1(rs + 1);
2339
op_ldst(std);
3023
2340
#endif
3024
2341
} else {
3025
2342
/* std / stdu */
3029
2346
return;
3030
2347
}
3031
2348
}
3032
EA = tcg_temp_new(TCG_TYPE_TL);
3033
gen_addr_imm_index(EA, ctx, 0x03);
3034
gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
2349
gen_addr_imm_index(ctx, 0x03);
2350
gen_op_load_gpr_T1(rs);
2351
op_ldst(std);
3035
2352
if (Rc(ctx->opcode))
3036
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3037
tcg_temp_free(EA);
2353
gen_op_store_T0_gpr(rA(ctx->opcode));
3038
2354
}
3039
2355
}
3040
2356
#endif
3041
2357
/*** Integer load and store with byte reverse ***/
3042
2358
/* lhbrx */
3043
void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3044
{
3045
TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3046
gen_qemu_ld16u(temp, t1, flags);
3047
tcg_gen_bswap16_i32(temp, temp);
3048
tcg_gen_extu_i32_tl(t0, temp);
3049
tcg_temp_free(temp);
3050
}
3051
GEN_LDX(16ur, 0x16, 0x18, PPC_INTEGER);
3052
2359
OP_LD_TABLE(hbr);
2360
GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
3053
2361
/* lwbrx */
3054
void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3055
{
3056
TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3057
gen_qemu_ld32u(temp, t1, flags);
3058
tcg_gen_bswap_i32(temp, temp);
3059
tcg_gen_extu_i32_tl(t0, temp);
3060
tcg_temp_free(temp);
3061
}
3062
GEN_LDX(32ur, 0x16, 0x10, PPC_INTEGER);
3063
2362
OP_LD_TABLE(wbr);
2363
GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
3064
2364
/* sthbrx */
3065
void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3066
{
3067
TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3068
tcg_gen_trunc_tl_i32(temp, t0);
3069
tcg_gen_ext16u_i32(temp, temp);
3070
tcg_gen_bswap16_i32(temp, temp);
3071
gen_qemu_st16(temp, t1, flags);
3072
tcg_temp_free(temp);
3073
}
3074
GEN_STX(16r, 0x16, 0x1C, PPC_INTEGER);
3075
2365
OP_ST_TABLE(hbr);
2366
GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
3076
2367
/* stwbrx */
3077
void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3078
{
3079
TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3080
tcg_gen_trunc_tl_i32(temp, t0);
3081
tcg_gen_bswap_i32(temp, temp);
3082
gen_qemu_st32(temp, t1, flags);
3083
tcg_temp_free(temp);
3084
}
3085
GEN_STX(32r, 0x16, 0x14, PPC_INTEGER);
2368
OP_ST_TABLE(wbr);
2369
GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
3086
2370
3087
2371
/*** Integer load and store multiple ***/
3088
2372
#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
3089
static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
3090
GEN_MEM_FUNCS(lmw),
3091
};
3092
static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
3093
GEN_MEM_FUNCS(stmw),
3094
};
2373
#if defined(CONFIG_USER_ONLY)
2374
/* User-mode only */
2375
static GenOpFunc1 *gen_op_lmw[] = {
2376
&gen_op_lmw_raw,
2377
&gen_op_lmw_le_raw,
2378
#if defined(TARGET_PPC64)
2379
&gen_op_lmw_64_raw,
2380
&gen_op_lmw_le_64_raw,
2381
#endif
2382
};
2383
static GenOpFunc1 *gen_op_stmw[] = {
2384
&gen_op_stmw_raw,
2385
&gen_op_stmw_le_raw,
2386
#if defined(TARGET_PPC64)
2387
&gen_op_stmw_64_raw,
2388
&gen_op_stmw_le_64_raw,
2389
#endif
2390
};
2391
#else
2392
#if defined(TARGET_PPC64)
2393
/* Full system - 64 bits mode */
2394
static GenOpFunc1 *gen_op_lmw[] = {
2395
&gen_op_lmw_user,
2396
&gen_op_lmw_le_user,
2397
&gen_op_lmw_64_user,
2398
&gen_op_lmw_le_64_user,
2399
&gen_op_lmw_kernel,
2400
&gen_op_lmw_le_kernel,
2401
&gen_op_lmw_64_kernel,
2402
&gen_op_lmw_le_64_kernel,
2403
#if defined(TARGET_PPC64H)
2404
&gen_op_lmw_hypv,
2405
&gen_op_lmw_le_hypv,
2406
&gen_op_lmw_64_hypv,
2407
&gen_op_lmw_le_64_hypv,
2408
#endif
2409
};
2410
static GenOpFunc1 *gen_op_stmw[] = {
2411
&gen_op_stmw_user,
2412
&gen_op_stmw_le_user,
2413
&gen_op_stmw_64_user,
2414
&gen_op_stmw_le_64_user,
2415
&gen_op_stmw_kernel,
2416
&gen_op_stmw_le_kernel,
2417
&gen_op_stmw_64_kernel,
2418
&gen_op_stmw_le_64_kernel,
2419
#if defined(TARGET_PPC64H)
2420
&gen_op_stmw_hypv,
2421
&gen_op_stmw_le_hypv,
2422
&gen_op_stmw_64_hypv,
2423
&gen_op_stmw_le_64_hypv,
2424
#endif
2425
};
2426
#else
2427
/* Full system - 32 bits mode */
2428
static GenOpFunc1 *gen_op_lmw[] = {
2429
&gen_op_lmw_user,
2430
&gen_op_lmw_le_user,
2431
&gen_op_lmw_kernel,
2432
&gen_op_lmw_le_kernel,
2433
};
2434
static GenOpFunc1 *gen_op_stmw[] = {
2435
&gen_op_stmw_user,
2436
&gen_op_stmw_le_user,
2437
&gen_op_stmw_kernel,
2438
&gen_op_stmw_le_kernel,
2439
};
2440
#endif
2441
#endif
3095
2442
3096
2443
/* lmw */
3097
2444
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3098
2445
{
3099
2446
/* NIP cannot be restored if the memory exception comes from an helper */
3100
2447
gen_update_nip(ctx, ctx->nip - 4);
3101
gen_addr_imm_index(cpu_T[0], ctx, 0);
2448
gen_addr_imm_index(ctx, 0);
3102
2449
op_ldstm(lmw, rD(ctx->opcode));
3103
2450
}
3104
2451
3107
2454
{
3108
2455
/* NIP cannot be restored if the memory exception comes from an helper */
3109
2456
gen_update_nip(ctx, ctx->nip - 4);
3110
gen_addr_imm_index(cpu_T[0], ctx, 0);
2457
gen_addr_imm_index(ctx, 0);
3111
2458
op_ldstm(stmw, rS(ctx->opcode));
3112
2459
}
3113
2460
3114
2461
/*** Integer load and store strings ***/
3115
2462
#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
3116
2463
#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
3117
/* string load & stores are by definition endian-safe */
3118
#define gen_op_lswi_le_raw gen_op_lswi_raw
3119
#define gen_op_lswi_le_user gen_op_lswi_user
3120
#define gen_op_lswi_le_kernel gen_op_lswi_kernel
3121
#define gen_op_lswi_le_hypv gen_op_lswi_hypv
3122
#define gen_op_lswi_le_64_raw gen_op_lswi_raw
3123
#define gen_op_lswi_le_64_user gen_op_lswi_user
3124
#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
3125
#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
3126
static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
3127
GEN_MEM_FUNCS(lswi),
3128
};
3129
#define gen_op_lswx_le_raw gen_op_lswx_raw
3130
#define gen_op_lswx_le_user gen_op_lswx_user
3131
#define gen_op_lswx_le_kernel gen_op_lswx_kernel
3132
#define gen_op_lswx_le_hypv gen_op_lswx_hypv
3133
#define gen_op_lswx_le_64_raw gen_op_lswx_raw
3134
#define gen_op_lswx_le_64_user gen_op_lswx_user
3135
#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
3136
#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
3137
static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
3138
GEN_MEM_FUNCS(lswx),
3139
};
3140
#define gen_op_stsw_le_raw gen_op_stsw_raw
3141
#define gen_op_stsw_le_user gen_op_stsw_user
3142
#define gen_op_stsw_le_kernel gen_op_stsw_kernel
3143
#define gen_op_stsw_le_hypv gen_op_stsw_hypv
3144
#define gen_op_stsw_le_64_raw gen_op_stsw_raw
3145
#define gen_op_stsw_le_64_user gen_op_stsw_user
3146
#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
3147
#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
3148
static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
3149
GEN_MEM_FUNCS(stsw),
3150
};
2464
#if defined(CONFIG_USER_ONLY)
2465
/* User-mode only */
2466
static GenOpFunc1 *gen_op_lswi[] = {
2467
&gen_op_lswi_raw,
2468
&gen_op_lswi_le_raw,
2469
#if defined(TARGET_PPC64)
2470
&gen_op_lswi_64_raw,
2471
&gen_op_lswi_le_64_raw,
2472
#endif
2473
};
2474
static GenOpFunc3 *gen_op_lswx[] = {
2475
&gen_op_lswx_raw,
2476
&gen_op_lswx_le_raw,
2477
#if defined(TARGET_PPC64)
2478
&gen_op_lswx_64_raw,
2479
&gen_op_lswx_le_64_raw,
2480
#endif
2481
};
2482
static GenOpFunc1 *gen_op_stsw[] = {
2483
&gen_op_stsw_raw,
2484
&gen_op_stsw_le_raw,
2485
#if defined(TARGET_PPC64)
2486
&gen_op_stsw_64_raw,
2487
&gen_op_stsw_le_64_raw,
2488
#endif
2489
};
2490
#else
2491
#if defined(TARGET_PPC64)
2492
/* Full system - 64 bits mode */
2493
static GenOpFunc1 *gen_op_lswi[] = {
2494
&gen_op_lswi_user,
2495
&gen_op_lswi_le_user,
2496
&gen_op_lswi_64_user,
2497
&gen_op_lswi_le_64_user,
2498
&gen_op_lswi_kernel,
2499
&gen_op_lswi_le_kernel,
2500
&gen_op_lswi_64_kernel,
2501
&gen_op_lswi_le_64_kernel,
2502
#if defined(TARGET_PPC64H)
2503
&gen_op_lswi_hypv,
2504
&gen_op_lswi_le_hypv,
2505
&gen_op_lswi_64_hypv,
2506
&gen_op_lswi_le_64_hypv,
2507
#endif
2508
};
2509
static GenOpFunc3 *gen_op_lswx[] = {
2510
&gen_op_lswx_user,
2511
&gen_op_lswx_le_user,
2512
&gen_op_lswx_64_user,
2513
&gen_op_lswx_le_64_user,
2514
&gen_op_lswx_kernel,
2515
&gen_op_lswx_le_kernel,
2516
&gen_op_lswx_64_kernel,
2517
&gen_op_lswx_le_64_kernel,
2518
#if defined(TARGET_PPC64H)
2519
&gen_op_lswx_hypv,
2520
&gen_op_lswx_le_hypv,
2521
&gen_op_lswx_64_hypv,
2522
&gen_op_lswx_le_64_hypv,
2523
#endif
2524
};
2525
static GenOpFunc1 *gen_op_stsw[] = {
2526
&gen_op_stsw_user,
2527
&gen_op_stsw_le_user,
2528
&gen_op_stsw_64_user,
2529
&gen_op_stsw_le_64_user,
2530
&gen_op_stsw_kernel,
2531
&gen_op_stsw_le_kernel,
2532
&gen_op_stsw_64_kernel,
2533
&gen_op_stsw_le_64_kernel,
2534
#if defined(TARGET_PPC64H)
2535
&gen_op_stsw_hypv,
2536
&gen_op_stsw_le_hypv,
2537
&gen_op_stsw_64_hypv,
2538
&gen_op_stsw_le_64_hypv,
2539
#endif
2540
};
2541
#else
2542
/* Full system - 32 bits mode */
2543
static GenOpFunc1 *gen_op_lswi[] = {
2544
&gen_op_lswi_user,
2545
&gen_op_lswi_le_user,
2546
&gen_op_lswi_kernel,
2547
&gen_op_lswi_le_kernel,
2548
};
2549
static GenOpFunc3 *gen_op_lswx[] = {
2550
&gen_op_lswx_user,
2551
&gen_op_lswx_le_user,
2552
&gen_op_lswx_kernel,
2553
&gen_op_lswx_le_kernel,
2554
};
2555
static GenOpFunc1 *gen_op_stsw[] = {
2556
&gen_op_stsw_user,
2557
&gen_op_stsw_le_user,
2558
&gen_op_stsw_kernel,
2559
&gen_op_stsw_le_kernel,
2560
};
2561
#endif
2562
#endif
3151
2563
3152
2564
/* lswi */
3153
2565
/* PowerPC32 specification says we must generate an exception if
3155
2567
* In an other hand, IBM says this is valid, but rA won't be loaded.
3156
2568
* For now, I'll follow the spec...
3157
2569
*/
3158
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
2570
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
3159
2571
{
3160
2572
int nb = NB(ctx->opcode);
3161
2573
int start = rD(ctx->opcode);
3174
2586
}
3175
2587
/* NIP cannot be restored if the memory exception comes from an helper */
3176
2588
gen_update_nip(ctx, ctx->nip - 4);
3177
gen_addr_register(cpu_T[0], ctx);
3178
tcg_gen_movi_tl(cpu_T[1], nb);
2589
gen_addr_register(ctx);
2590
gen_op_set_T1(nb);
3179
2591
op_ldsts(lswi, start);
3180
2592
}
3181
2593
3182
2594
/* lswx */
3183
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
2595
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
3184
2596
{
3185
2597
int ra = rA(ctx->opcode);
3186
2598
int rb = rB(ctx->opcode);
3187
2599
3188
2600
/* NIP cannot be restored if the memory exception comes from an helper */
3189
2601
gen_update_nip(ctx, ctx->nip - 4);
3190
gen_addr_reg_index(cpu_T[0], ctx);
2602
gen_addr_reg_index(ctx);
3191
2603
if (ra == 0) {
3192
2604
ra = rb;
3193
2605
}
3194
tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
2606
gen_op_load_xer_bc();
3195
2607
op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
3196
2608
}
3197
2609
3198
2610
/* stswi */
3199
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
2611
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
3200
2612
{
3201
2613
int nb = NB(ctx->opcode);
3202
2614
3203
2615
/* NIP cannot be restored if the memory exception comes from an helper */
3204
2616
gen_update_nip(ctx, ctx->nip - 4);
3205
gen_addr_register(cpu_T[0], ctx);
2617
gen_addr_register(ctx);
3206
2618
if (nb == 0)
3207
2619
nb = 32;
3208
tcg_gen_movi_tl(cpu_T[1], nb);
2620
gen_op_set_T1(nb);
3209
2621
op_ldsts(stsw, rS(ctx->opcode));
3210
2622
}
3211
2623
3212
2624
/* stswx */
3213
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
2625
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
3214
2626
{
3215
2627
/* NIP cannot be restored if the memory exception comes from an helper */
3216
2628
gen_update_nip(ctx, ctx->nip - 4);
3217
gen_addr_reg_index(cpu_T[0], ctx);
3218
tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
2629
gen_addr_reg_index(ctx);
2630
gen_op_load_xer_bc();
3219
2631
op_ldsts(stsw, rS(ctx->opcode));
3220
2632
}
3221
2633
3233
2645
3234
2646
#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
3235
2647
#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
3236
static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
3237
GEN_MEM_FUNCS(lwarx),
3238
};
3239
static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
3240
GEN_MEM_FUNCS(stwcx),
3241
};
2648
#if defined(CONFIG_USER_ONLY)
2649
/* User-mode only */
2650
static GenOpFunc *gen_op_lwarx[] = {
2651
&gen_op_lwarx_raw,
2652
&gen_op_lwarx_le_raw,
2653
#if defined(TARGET_PPC64)
2654
&gen_op_lwarx_64_raw,
2655
&gen_op_lwarx_le_64_raw,
2656
#endif
2657
};
2658
static GenOpFunc *gen_op_stwcx[] = {
2659
&gen_op_stwcx_raw,
2660
&gen_op_stwcx_le_raw,
2661
#if defined(TARGET_PPC64)
2662
&gen_op_stwcx_64_raw,
2663
&gen_op_stwcx_le_64_raw,
2664
#endif
2665
};
2666
#else
2667
#if defined(TARGET_PPC64)
2668
/* Full system - 64 bits mode */
2669
static GenOpFunc *gen_op_lwarx[] = {
2670
&gen_op_lwarx_user,
2671
&gen_op_lwarx_le_user,
2672
&gen_op_lwarx_64_user,
2673
&gen_op_lwarx_le_64_user,
2674
&gen_op_lwarx_kernel,
2675
&gen_op_lwarx_le_kernel,
2676
&gen_op_lwarx_64_kernel,
2677
&gen_op_lwarx_le_64_kernel,
2678
#if defined(TARGET_PPC64H)
2679
&gen_op_lwarx_hypv,
2680
&gen_op_lwarx_le_hypv,
2681
&gen_op_lwarx_64_hypv,
2682
&gen_op_lwarx_le_64_hypv,
2683
#endif
2684
};
2685
static GenOpFunc *gen_op_stwcx[] = {
2686
&gen_op_stwcx_user,
2687
&gen_op_stwcx_le_user,
2688
&gen_op_stwcx_64_user,
2689
&gen_op_stwcx_le_64_user,
2690
&gen_op_stwcx_kernel,
2691
&gen_op_stwcx_le_kernel,
2692
&gen_op_stwcx_64_kernel,
2693
&gen_op_stwcx_le_64_kernel,
2694
#if defined(TARGET_PPC64H)
2695
&gen_op_stwcx_hypv,
2696
&gen_op_stwcx_le_hypv,
2697
&gen_op_stwcx_64_hypv,
2698
&gen_op_stwcx_le_64_hypv,
2699
#endif
2700
};
2701
#else
2702
/* Full system - 32 bits mode */
2703
static GenOpFunc *gen_op_lwarx[] = {
2704
&gen_op_lwarx_user,
2705
&gen_op_lwarx_le_user,
2706
&gen_op_lwarx_kernel,
2707
&gen_op_lwarx_le_kernel,
2708
};
2709
static GenOpFunc *gen_op_stwcx[] = {
2710
&gen_op_stwcx_user,
2711
&gen_op_stwcx_le_user,
2712
&gen_op_stwcx_kernel,
2713
&gen_op_stwcx_le_kernel,
2714
};
2715
#endif
2716
#endif
3242
2717
3243
2718
/* lwarx */
3244
2719
GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
3245
2720
{
3246
2721
/* NIP cannot be restored if the memory exception comes from an helper */
3247
2722
gen_update_nip(ctx, ctx->nip - 4);
3248
gen_addr_reg_index(cpu_T[0], ctx);
2723
gen_addr_reg_index(ctx);
3249
2724
op_lwarx();
3250
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
2725
gen_op_store_T1_gpr(rD(ctx->opcode));
3251
2726
}
3252
2727
3253
2728
/* stwcx. */
3254
GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
2729
GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
3255
2730
{
3256
2731
/* NIP cannot be restored if the memory exception comes from an helper */
3257
2732
gen_update_nip(ctx, ctx->nip - 4);
3258
gen_addr_reg_index(cpu_T[0], ctx);
3259
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
2733
gen_addr_reg_index(ctx);
2734
gen_op_load_gpr_T1(rS(ctx->opcode));
3260
2735
op_stwcx();
3261
2736
}
3262
2737
3263
2738
#if defined(TARGET_PPC64)
3264
2739
#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
3265
2740
#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
3266
static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
3267
GEN_MEM_FUNCS(ldarx),
3268
};
3269
static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
3270
GEN_MEM_FUNCS(stdcx),
3271
};
2741
#if defined(CONFIG_USER_ONLY)
2742
/* User-mode only */
2743
static GenOpFunc *gen_op_ldarx[] = {
2744
&gen_op_ldarx_raw,
2745
&gen_op_ldarx_le_raw,
2746
&gen_op_ldarx_64_raw,
2747
&gen_op_ldarx_le_64_raw,
2748
};
2749
static GenOpFunc *gen_op_stdcx[] = {
2750
&gen_op_stdcx_raw,
2751
&gen_op_stdcx_le_raw,
2752
&gen_op_stdcx_64_raw,
2753
&gen_op_stdcx_le_64_raw,
2754
};
2755
#else
2756
/* Full system */
2757
static GenOpFunc *gen_op_ldarx[] = {
2758
&gen_op_ldarx_user,
2759
&gen_op_ldarx_le_user,
2760
&gen_op_ldarx_64_user,
2761
&gen_op_ldarx_le_64_user,
2762
&gen_op_ldarx_kernel,
2763
&gen_op_ldarx_le_kernel,
2764
&gen_op_ldarx_64_kernel,
2765
&gen_op_ldarx_le_64_kernel,
2766
#if defined(TARGET_PPC64H)
2767
&gen_op_ldarx_hypv,
2768
&gen_op_ldarx_le_hypv,
2769
&gen_op_ldarx_64_hypv,
2770
&gen_op_ldarx_le_64_hypv,
2771
#endif
2772
};
2773
static GenOpFunc *gen_op_stdcx[] = {
2774
&gen_op_stdcx_user,
2775
&gen_op_stdcx_le_user,
2776
&gen_op_stdcx_64_user,
2777
&gen_op_stdcx_le_64_user,
2778
&gen_op_stdcx_kernel,
2779
&gen_op_stdcx_le_kernel,
2780
&gen_op_stdcx_64_kernel,
2781
&gen_op_stdcx_le_64_kernel,
2782
#if defined(TARGET_PPC64H)
2783
&gen_op_stdcx_hypv,
2784
&gen_op_stdcx_le_hypv,
2785
&gen_op_stdcx_64_hypv,
2786
&gen_op_stdcx_le_64_hypv,
2787
#endif
2788
};
2789
#endif
3272
2790
3273
2791
/* ldarx */
3274
2792
GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
3275
2793
{
3276
2794
/* NIP cannot be restored if the memory exception comes from an helper */
3277
2795
gen_update_nip(ctx, ctx->nip - 4);
3278
gen_addr_reg_index(cpu_T[0], ctx);
2796
gen_addr_reg_index(ctx);
3279
2797
op_ldarx();
3280
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
2798
gen_op_store_T1_gpr(rD(ctx->opcode));
3281
2799
}
3282
2800
3283
2801
/* stdcx. */
3284
GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
2802
GEN_HANDLER(stdcx_, 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
3285
2803
{
3286
2804
/* NIP cannot be restored if the memory exception comes from an helper */
3287
2805
gen_update_nip(ctx, ctx->nip - 4);
3288
gen_addr_reg_index(cpu_T[0], ctx);
3289
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
2806
gen_addr_reg_index(ctx);
2807
gen_op_load_gpr_T1(rS(ctx->opcode));
3290
2808
op_stdcx();
3291
2809
}
3292
2810
#endif /* defined(TARGET_PPC64) */
3312
2830
GEN_EXCP_NO_FP(ctx); \
3313
2831
return; \
3314
2832
} \
3315
gen_addr_imm_index(cpu_T[0], ctx, 0); \
2833
gen_addr_imm_index(ctx, 0); \
3316
2834
op_ldst(l##width); \
3317
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2835
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
3318
2836
}
3319
2837
3320
2838
#define GEN_LDUF(width, opc, type) \
3328
2846
GEN_EXCP_INVAL(ctx); \
3329
2847
return; \
3330
2848
} \
3331
gen_addr_imm_index(cpu_T[0], ctx, 0); \
2849
gen_addr_imm_index(ctx, 0); \
3332
2850
op_ldst(l##width); \
3333
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
3334
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2851
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2852
gen_op_store_T0_gpr(rA(ctx->opcode)); \
3335
2853
}
3336
2854
3337
2855
#define GEN_LDUXF(width, opc, type) \
3345
2863
GEN_EXCP_INVAL(ctx); \
3346
2864
return; \
3347
2865
} \
3348
gen_addr_reg_index(cpu_T[0], ctx); \
2866
gen_addr_reg_index(ctx); \
3349
2867
op_ldst(l##width); \
3350
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
3351
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2868
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
2869
gen_op_store_T0_gpr(rA(ctx->opcode)); \
3352
2870
}
3353
2871
3354
2872
#define GEN_LDXF(width, opc2, opc3, type) \
3358
2876
GEN_EXCP_NO_FP(ctx); \
3359
2877
return; \
3360
2878
} \
3361
gen_addr_reg_index(cpu_T[0], ctx); \
2879
gen_addr_reg_index(ctx); \
3362
2880
op_ldst(l##width); \
3363
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
2881
gen_op_store_FT0_fpr(rD(ctx->opcode)); \
3364
2882
}
3365
2883
3366
2884
#define GEN_LDFS(width, op, type) \
3383
2901
GEN_EXCP_NO_FP(ctx); \
3384
2902
return; \
3385
2903
} \
3386
gen_addr_imm_index(cpu_T[0], ctx, 0); \
3387
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
2904
gen_addr_imm_index(ctx, 0); \
2905
gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3388
2906
op_ldst(st##width); \
3389
2907
}
3390
2908
3399
2917
GEN_EXCP_INVAL(ctx); \
3400
2918
return; \
3401
2919
} \
3402
gen_addr_imm_index(cpu_T[0], ctx, 0); \
3403
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
2920
gen_addr_imm_index(ctx, 0); \
2921
gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3404
2922
op_ldst(st##width); \
3405
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2923
gen_op_store_T0_gpr(rA(ctx->opcode)); \
3406
2924
}
3407
2925
3408
2926
#define GEN_STUXF(width, opc, type) \
3416
2934
GEN_EXCP_INVAL(ctx); \
3417
2935
return; \
3418
2936
} \
3419
gen_addr_reg_index(cpu_T[0], ctx); \
3420
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
2937
gen_addr_reg_index(ctx); \
2938
gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3421
2939
op_ldst(st##width); \
3422
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
2940
gen_op_store_T0_gpr(rA(ctx->opcode)); \
3423
2941
}
3424
2942
3425
2943
#define GEN_STXF(width, opc2, opc3, type) \
3429
2947
GEN_EXCP_NO_FP(ctx); \
3430
2948
return; \
3431
2949
} \
3432
gen_addr_reg_index(cpu_T[0], ctx); \
3433
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
2950
gen_addr_reg_index(ctx); \
2951
gen_op_load_fpr_FT0(rS(ctx->opcode)); \
3434
2952
op_ldst(st##width); \
3435
2953
}
3436
2954
3448
2966
3449
2967
/* Optional: */
3450
2968
/* stfiwx */
3451
OP_ST_TABLE(fiw);
3452
GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
2969
OP_ST_TABLE(fiwx);
2970
GEN_STXF(fiwx, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3453
2971
3454
2972
/*** Branch ***/
3455
2973
static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3457
2975
{
3458
2976
TranslationBlock *tb;
3459
2977
tb = ctx->tb;
2978
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
2979
if (n == 0)
2980
gen_op_goto_tb0(TBPARAM(tb));
2981
else
2982
gen_op_goto_tb1(TBPARAM(tb));
2983
gen_set_T1(dest);
3460
2984
#if defined(TARGET_PPC64)
3461
if (!ctx->sf_mode)
3462
dest = (uint32_t) dest;
2985
if (ctx->sf_mode)
2986
gen_op_b_T1_64();
2987
else
3463
2988
#endif
3464
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3465
likely(!ctx->singlestep_enabled)) {
3466
tcg_gen_goto_tb(n);
3467
tcg_gen_movi_tl(cpu_nip, dest & ~3);
3468
tcg_gen_exit_tb((long)tb + n);
2989
gen_op_b_T1();
2990
gen_op_set_T0((long)tb + n);
2991
if (ctx->singlestep_enabled)
2992
gen_op_debug();
2993
gen_op_exit_tb();
3469
2994
} else {
3470
tcg_gen_movi_tl(cpu_nip, dest & ~3);
3471
if (unlikely(ctx->singlestep_enabled)) {
3472
if ((ctx->singlestep_enabled &
3473
(CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3474
ctx->exception == POWERPC_EXCP_BRANCH) {
3475
target_ulong tmp = ctx->nip;
3476
ctx->nip = dest;
3477
GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3478
ctx->nip = tmp;
3479
}
3480
if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3481
gen_update_nip(ctx, dest);
3482
gen_op_debug();
3483
}
3484
}
3485
tcg_gen_exit_tb(0);
2995
gen_set_T1(dest);
2996
#if defined(TARGET_PPC64)
2997
if (ctx->sf_mode)
2998
gen_op_b_T1_64();
2999
else
3000
#endif
3001
gen_op_b_T1();
3002
gen_op_reset_T0();
3003
if (ctx->singlestep_enabled)
3004
gen_op_debug();
3005
gen_op_exit_tb();
3486
3006
}
3487
3007
}
3488
3008
3489
3009
static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
3490
3010
{
3491
3011
#if defined(TARGET_PPC64)
3492
if (ctx->sf_mode == 0)
3493
tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3012
if (ctx->sf_mode != 0 && (nip >> 32))
3013
gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
3494
3014
else
3495
3015
#endif
3496
tcg_gen_movi_tl(cpu_lr, nip);
3016
gen_op_setlr(ctx->nip);
3497
3017
}
3498
3018
3499
3019
/* b ba bl bla */
3501
3021
{
3502
3022
target_ulong li, target;
3503
3023
3504
ctx->exception = POWERPC_EXCP_BRANCH;
3505
3024
/* sign extend LI */
3506
3025
#if defined(TARGET_PPC64)
3507
3026
if (ctx->sf_mode)
3513
3032
target = ctx->nip + li - 4;
3514
3033
else
3515
3034
target = li;
3035
#if defined(TARGET_PPC64)
3036
if (!ctx->sf_mode)
3037
target = (uint32_t)target;
3038
#endif
3516
3039
if (LK(ctx->opcode))
3517
3040
gen_setlr(ctx, ctx->nip);
3518
3041
gen_goto_tb(ctx, 0, target);
3042
ctx->exception = POWERPC_EXCP_BRANCH;
3519
3043
}
3520
3044
3521
3045
#define BCOND_IM 0
3524
3048
3525
3049
static always_inline void gen_bcond (DisasContext *ctx, int type)
3526
3050
{
3051
target_ulong target = 0;
3052
target_ulong li;
3527
3053
uint32_t bo = BO(ctx->opcode);
3528
int l1 = gen_new_label();
3529
TCGv target;
3054
uint32_t bi = BI(ctx->opcode);
3055
uint32_t mask;
3530
3056
3531
ctx->exception = POWERPC_EXCP_BRANCH;
3532
if (type == BCOND_LR || type == BCOND_CTR) {
3533
target = tcg_temp_local_new(TCG_TYPE_TL);
3534
if (type == BCOND_CTR)
3535
tcg_gen_mov_tl(target, cpu_ctr);
3536
else
3537
tcg_gen_mov_tl(target, cpu_lr);
3057
if ((bo & 0x4) == 0)
3058
gen_op_dec_ctr();
3059
switch(type) {
3060
case BCOND_IM:
3061
li = (target_long)((int16_t)(BD(ctx->opcode)));
3062
if (likely(AA(ctx->opcode) == 0)) {
3063
target = ctx->nip + li - 4;
3064
} else {
3065
target = li;
3066
}
3067
#if defined(TARGET_PPC64)
3068
if (!ctx->sf_mode)
3069
target = (uint32_t)target;
3070
#endif
3071
break;
3072
case BCOND_CTR:
3073
gen_op_movl_T1_ctr();
3074
break;
3075
default:
3076
case BCOND_LR:
3077
gen_op_movl_T1_lr();
3078
break;
3538
3079
}
3539
3080
if (LK(ctx->opcode))
3540
3081
gen_setlr(ctx, ctx->nip);
3541
l1 = gen_new_label();
3542
if ((bo & 0x4) == 0) {
3543
/* Decrement and test CTR */
3544
TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3545
if (unlikely(type == BCOND_CTR)) {
3546
GEN_EXCP_INVAL(ctx);
3547
return;
3548
}
3549
tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3550
#if defined(TARGET_PPC64)
3551
if (!ctx->sf_mode)
3552
tcg_gen_ext32u_tl(temp, cpu_ctr);
3553
else
3554
#endif
3555
tcg_gen_mov_tl(temp, cpu_ctr);
3556
if (bo & 0x2) {
3557
tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3558
} else {
3559
tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3560
}
3561
}
3562
if ((bo & 0x10) == 0) {
3563
/* Test CR */
3564
uint32_t bi = BI(ctx->opcode);
3565
uint32_t mask = 1 << (3 - (bi & 0x03));
3566
TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3567
3082
if (bo & 0x10) {
3083
/* No CR condition */
3084
switch (bo & 0x6) {
3085
case 0:
3086
#if defined(TARGET_PPC64)
3087
if (ctx->sf_mode)
3088
gen_op_test_ctr_64();
3089
else
3090
#endif
3091
gen_op_test_ctr();
3092
break;
3093
case 2:
3094
#if defined(TARGET_PPC64)
3095
if (ctx->sf_mode)
3096
gen_op_test_ctrz_64();
3097
else
3098
#endif
3099
gen_op_test_ctrz();
3100
break;
3101
default:
3102
case 4:
3103
case 6:
3104
if (type == BCOND_IM) {
3105
gen_goto_tb(ctx, 0, target);
3106
goto out;
3107
} else {
3108
#if defined(TARGET_PPC64)
3109
if (ctx->sf_mode)
3110
gen_op_b_T1_64();
3111
else
3112
#endif
3113
gen_op_b_T1();
3114
gen_op_reset_T0();
3115
goto no_test;
3116
}
3117
break;
3118
}
3119
} else {
3120
mask = 1 << (3 - (bi & 0x03));
3121
gen_op_load_crf_T0(bi >> 2);
3568
3122
if (bo & 0x8) {
3569
tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3570
tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3123
switch (bo & 0x6) {
3124
case 0:
3125
#if defined(TARGET_PPC64)
3126
if (ctx->sf_mode)
3127
gen_op_test_ctr_true_64(mask);
3128
else
3129
#endif
3130
gen_op_test_ctr_true(mask);
3131
break;
3132
case 2:
3133
#if defined(TARGET_PPC64)
3134
if (ctx->sf_mode)
3135
gen_op_test_ctrz_true_64(mask);
3136
else
3137
#endif
3138
gen_op_test_ctrz_true(mask);
3139
break;
3140
default:
3141
case 4:
3142
case 6:
3143
gen_op_test_true(mask);
3144
break;
3145
}
3571
3146
} else {
3572
tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3573
tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3147
switch (bo & 0x6) {
3148
case 0:
3149
#if defined(TARGET_PPC64)
3150
if (ctx->sf_mode)
3151
gen_op_test_ctr_false_64(mask);
3152
else
3153
#endif
3154
gen_op_test_ctr_false(mask);
3155
break;
3156
case 2:
3157
#if defined(TARGET_PPC64)
3158
if (ctx->sf_mode)
3159
gen_op_test_ctrz_false_64(mask);
3160
else
3161
#endif
3162
gen_op_test_ctrz_false(mask);
3163
break;
3164
default:
3165
case 4:
3166
case 6:
3167
gen_op_test_false(mask);
3168
break;
3169
}
3574
3170
}
3575
3171
}
3576
3172
if (type == BCOND_IM) {
3577
target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3578
if (likely(AA(ctx->opcode) == 0)) {
3579
gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3580
} else {
3581
gen_goto_tb(ctx, 0, li);
3582
}
3173
int l1 = gen_new_label();
3174
gen_op_jz_T0(l1);
3175
gen_goto_tb(ctx, 0, target);
3583
3176
gen_set_label(l1);
3584
3177
gen_goto_tb(ctx, 1, ctx->nip);
3585
3178
} else {
3586
3179
#if defined(TARGET_PPC64)
3587
if (!(ctx->sf_mode))
3588
tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3589
else
3590
#endif
3591
tcg_gen_andi_tl(cpu_nip, target, ~3);
3592
tcg_gen_exit_tb(0);
3593
gen_set_label(l1);
3594
#if defined(TARGET_PPC64)
3595
if (!(ctx->sf_mode))
3596
tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3597
else
3598
#endif
3599
tcg_gen_movi_tl(cpu_nip, ctx->nip);
3600
tcg_gen_exit_tb(0);
3180
if (ctx->sf_mode)
3181
gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3182
else
3183
#endif
3184
gen_op_btest_T1(ctx->nip);
3185
gen_op_reset_T0();
3186
no_test:
3187
if (ctx->singlestep_enabled)
3188
gen_op_debug();
3189
gen_op_exit_tb();
3601
3190
}
3191
out:
3192
ctx->exception = POWERPC_EXCP_BRANCH;
3602
3193
}
3603
3194
3604
3195
GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3617
3208
}
3618
3209
3619
3210
/*** Condition register logical ***/
3620
#define GEN_CRLOGIC(name, tcg_op, opc) \
3621
GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3211
#define GEN_CRLOGIC(op, opc) \
3212
GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3622
3213
{ \
3623
uint8_t bitmask; \
3624
int sh; \
3625
TCGv t0, t1; \
3626
sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3627
t0 = tcg_temp_new(TCG_TYPE_I32); \
3628
if (sh > 0) \
3629
tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3630
else if (sh < 0) \
3631
tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3632
else \
3633
tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3634
t1 = tcg_temp_new(TCG_TYPE_I32); \
3635
sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3636
if (sh > 0) \
3637
tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3638
else if (sh < 0) \
3639
tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3640
else \
3641
tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3642
tcg_op(t0, t0, t1); \
3643
bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3644
tcg_gen_andi_i32(t0, t0, bitmask); \
3645
tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3646
tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3647
tcg_temp_free(t0); \
3648
tcg_temp_free(t1); \
3214
gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
3215
gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
3216
gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
3217
gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
3218
gen_op_##op(); \
3219
gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
3220
gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
3221
3 - (crbD(ctx->opcode) & 0x03)); \
3222
gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
3649
3223
}
3650
3224
3651
3225
/* crand */
3652
GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3226
GEN_CRLOGIC(and, 0x08);
3653
3227
/* crandc */
3654
GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3228
GEN_CRLOGIC(andc, 0x04);
3655
3229
/* creqv */
3656
GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3230
GEN_CRLOGIC(eqv, 0x09);
3657
3231
/* crnand */
3658
GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3232
GEN_CRLOGIC(nand, 0x07);
3659
3233
/* crnor */
3660
GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3234
GEN_CRLOGIC(nor, 0x01);
3661
3235
/* cror */
3662
GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3236
GEN_CRLOGIC(or, 0x0E);
3663
3237
/* crorc */
3664
GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3238
GEN_CRLOGIC(orc, 0x0D);
3665
3239
/* crxor */
3666
GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3240
GEN_CRLOGIC(xor, 0x06);
3667
3241
/* mcrf */
3668
3242
GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3669
3243
{
3670
tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3244
gen_op_load_crf_T0(crfS(ctx->opcode));
3245
gen_op_store_T0_crf(crfD(ctx->opcode));
3671
3246
}
3672
3247
3673
3248
/*** System linkage ***/
3702
3277
GEN_SYNC(ctx);
3703
3278
#endif
3704
3279
}
3280
#endif
3705
3281
3706
GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
3282
#if defined(TARGET_PPC64H)
3283
GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B)
3707
3284
{
3708
3285
#if defined(CONFIG_USER_ONLY)
3709
3286
GEN_EXCP_PRIVOPC(ctx);
3737
3314
/* tw */
3738
3315
GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
3739
3316
{
3740
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3741
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3317
gen_op_load_gpr_T0(rA(ctx->opcode));
3318
gen_op_load_gpr_T1(rB(ctx->opcode));
3742
3319
/* Update the nip since this might generate a trap exception */
3743
3320
gen_update_nip(ctx, ctx->nip);
3744
3321
gen_op_tw(TO(ctx->opcode));
3747
3324
/* twi */
3748
3325
GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3749
3326
{
3750
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3751
tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3327
gen_op_load_gpr_T0(rA(ctx->opcode));
3328
gen_set_T1(SIMM(ctx->opcode));
3752
3329
/* Update the nip since this might generate a trap exception */
3753
3330
gen_update_nip(ctx, ctx->nip);
3754
3331
gen_op_tw(TO(ctx->opcode));
3758
3335
/* td */
3759
3336
GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3760
3337
{
3761
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3762
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3338
gen_op_load_gpr_T0(rA(ctx->opcode));
3339
gen_op_load_gpr_T1(rB(ctx->opcode));
3763
3340
/* Update the nip since this might generate a trap exception */
3764
3341
gen_update_nip(ctx, ctx->nip);
3765
3342
gen_op_td(TO(ctx->opcode));
3768
3345
/* tdi */
3769
3346
GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3770
3347
{
3771
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3772
tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
3348
gen_op_load_gpr_T0(rA(ctx->opcode));
3349
gen_set_T1(SIMM(ctx->opcode));
3773
3350
/* Update the nip since this might generate a trap exception */
3774
3351
gen_update_nip(ctx, ctx->nip);
3775
3352
gen_op_td(TO(ctx->opcode));
3780
3357
/* mcrxr */
3781
3358
GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3782
3359
{
3783
tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3784
tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3785
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3360
gen_op_load_xer_cr();
3361
gen_op_store_T0_crf(crfD(ctx->opcode));
3362
gen_op_clear_xer_ov();
3363
gen_op_clear_xer_ca();
3786
3364
}
3787
3365
3788
3366
/* mfcr */
3794
3372
crm = CRM(ctx->opcode);
3795
3373
if (likely((crm ^ (crm - 1)) == 0)) {
3796
3374
crn = ffs(crm);
3797
tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3375
gen_op_load_cro(7 - crn);
3798
3376
}
3799
3377
} else {
3800
tcg_gen_helper_1_0(helper_load_cr, cpu_gpr[rD(ctx->opcode)]);
3378
gen_op_load_cr();
3801
3379
}
3380
gen_op_store_T0_gpr(rD(ctx->opcode));
3802
3381
}
3803
3382
3804
3383
/* mfmsr */
3812
3391
return;
3813
3392
}
3814
3393
gen_op_load_msr();
3815
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3394
gen_op_store_T0_gpr(rD(ctx->opcode));
3816
3395
#endif
3817
3396
}
3818
3397
3819
#if 1
3820
#define SPR_NOACCESS ((void *)(-1UL))
3398
#if 0
3399
#define SPR_NOACCESS ((void *)(-1))
3821
3400
#else
3822
3401
static void spr_noaccess (void *opaque, int sprn)
3823
3402
{
3834
3413
uint32_t sprn = SPR(ctx->opcode);
3835
3414
3836
3415
#if !defined(CONFIG_USER_ONLY)
3416
#if defined(TARGET_PPC64H)
3837
3417
if (ctx->supervisor == 2)
3838
3418
read_cb = ctx->spr_cb[sprn].hea_read;
3839
else if (ctx->supervisor)
3419
else
3420
#endif
3421
if (ctx->supervisor)
3840
3422
read_cb = ctx->spr_cb[sprn].oea_read;
3841
3423
else
3842
3424
#endif
3844
3426
if (likely(read_cb != NULL)) {
3845
3427
if (likely(read_cb != SPR_NOACCESS)) {
3846
3428
(*read_cb)(ctx, sprn);
3847
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3429
gen_op_store_T0_gpr(rD(ctx->opcode));
3848
3430
} else {
3849
3431
/* Privilege exception */
3850
/* This is a hack to avoid warnings when running Linux:
3851
* this OS breaks the PowerPC virtualisation model,
3852
* allowing userland application to read the PVR
3853
*/
3854
if (sprn != SPR_PVR) {
3855
if (loglevel != 0) {
3856
fprintf(logfile, "Trying to read privileged spr %d %03x at "
3857
ADDRX "\n", sprn, sprn, ctx->nip);
3858
}
3859
printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3860
sprn, sprn, ctx->nip);
3432
if (loglevel != 0) {
3433
fprintf(logfile, "Trying to read privileged spr %d %03x\n",
3434
sprn, sprn);
3861
3435
}
3436
printf("Trying to read privileged spr %d %03x\n", sprn, sprn);
3862
3437
GEN_EXCP_PRIVREG(ctx);
3863
3438
}
3864
3439
} else {
3865
3440
/* Not defined */
3866
3441
if (loglevel != 0) {
3867
fprintf(logfile, "Trying to read invalid spr %d %03x at "
3868
ADDRX "\n", sprn, sprn, ctx->nip);
3442
fprintf(logfile, "Trying to read invalid spr %d %03x\n",
3443
sprn, sprn);
3869
3444
}
3870
printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3871
sprn, sprn, ctx->nip);
3445
printf("Trying to read invalid spr %d %03x\n", sprn, sprn);
3872
3446
GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3873
3447
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
3874
3448
}
3890
3464
{
3891
3465
uint32_t crm, crn;
3892
3466
3467
gen_op_load_gpr_T0(rS(ctx->opcode));
3893
3468
crm = CRM(ctx->opcode);
3894
3469
if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3895
3470
crn = ffs(crm);
3896
tcg_gen_shri_i32(cpu_crf[7 - crn], cpu_gpr[rS(ctx->opcode)], crn * 4);
3897
tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3471
gen_op_srli_T0(crn * 4);
3472
gen_op_andi_T0(0xF);
3473
gen_op_store_cro(7 - crn);
3898
3474
} else {
3899
TCGv t0 = tcg_const_tl(crm);
3900
tcg_gen_helper_0_2(helper_store_cr, cpu_gpr[rS(ctx->opcode)], t0);
3901
tcg_temp_free(t0);
3475
gen_op_store_cr(crm);
3902
3476
}
3903
3477
}
3904
3478
3913
3487
GEN_EXCP_PRIVREG(ctx);
3914
3488
return;
3915
3489
}
3916
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3490
gen_op_load_gpr_T0(rS(ctx->opcode));
3917
3491
if (ctx->opcode & 0x00010000) {
3918
3492
/* Special form that does not need any synchronisation */
3919
3493
gen_op_update_riee();
3941
3515
GEN_EXCP_PRIVREG(ctx);
3942
3516
return;
3943
3517
}
3944
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3518
gen_op_load_gpr_T0(rS(ctx->opcode));
3945
3519
if (ctx->opcode & 0x00010000) {
3946
3520
/* Special form that does not need any synchronisation */
3947
3521
gen_op_update_riee();
3971
3545
uint32_t sprn = SPR(ctx->opcode);
3972
3546
3973
3547
#if !defined(CONFIG_USER_ONLY)
3548
#if defined(TARGET_PPC64H)
3974
3549
if (ctx->supervisor == 2)
3975
3550
write_cb = ctx->spr_cb[sprn].hea_write;
3976
else if (ctx->supervisor)
3551
else
3552
#endif
3553
if (ctx->supervisor)
3977
3554
write_cb = ctx->spr_cb[sprn].oea_write;
3978
3555
else
3979
3556
#endif
3980
3557
write_cb = ctx->spr_cb[sprn].uea_write;
3981
3558
if (likely(write_cb != NULL)) {
3982
3559
if (likely(write_cb != SPR_NOACCESS)) {
3983
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3560
gen_op_load_gpr_T0(rS(ctx->opcode));
3984
3561
(*write_cb)(ctx, sprn);
3985
3562
} else {
3986
3563
/* Privilege exception */
3987
3564
if (loglevel != 0) {
3988
fprintf(logfile, "Trying to write privileged spr %d %03x at "
3989
ADDRX "\n", sprn, sprn, ctx->nip);
3565
fprintf(logfile, "Trying to write privileged spr %d %03x\n",
3566
sprn, sprn);
3990
3567
}
3991
printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3992
sprn, sprn, ctx->nip);
3568
printf("Trying to write privileged spr %d %03x\n", sprn, sprn);
3993
3569
GEN_EXCP_PRIVREG(ctx);
3994
3570
}
3995
3571
} else {
3996
3572
/* Not defined */
3997
3573
if (loglevel != 0) {
3998
fprintf(logfile, "Trying to write invalid spr %d %03x at "
3999
ADDRX "\n", sprn, sprn, ctx->nip);
3574
fprintf(logfile, "Trying to write invalid spr %d %03x\n",
3575
sprn, sprn);
4000
3576
}
4001
printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4002
sprn, sprn, ctx->nip);
3577
printf("Trying to write invalid spr %d %03x\n", sprn, sprn);
4003
3578
GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4004
3579
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
4005
3580
}
4006
3581
}
4007
3582
4008
3583
/*** Cache management ***/
3584
/* For now, all those will be implemented as nop:
3585
* this is valid, regarding the PowerPC specs...
3586
* We just have to flush tb while invalidating instruction cache lines...
3587
*/
4009
3588
/* dcbf */
4010
3589
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
4011
3590
{
4012
/* XXX: specification says this is treated as a load by the MMU */
4013
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
4014
gen_addr_reg_index(t0, ctx);
4015
gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4016
tcg_temp_free(t0);
3591
gen_addr_reg_index(ctx);
3592
op_ldst(lbz);
4017
3593
}
4018
3594
4019
3595
/* dcbi (Supervisor only) */
4022
3598
#if defined(CONFIG_USER_ONLY)
4023
3599
GEN_EXCP_PRIVOPC(ctx);
4024
3600
#else
4025
TCGv EA, val;
4026
3601
if (unlikely(!ctx->supervisor)) {
4027
3602
GEN_EXCP_PRIVOPC(ctx);
4028
3603
return;
4029
3604
}
4030
EA = tcg_temp_new(TCG_TYPE_TL);
4031
gen_addr_reg_index(EA, ctx);
4032
val = tcg_temp_new(TCG_TYPE_TL);
3605
gen_addr_reg_index(ctx);
4033
3606
/* XXX: specification says this should be treated as a store by the MMU */
4034
gen_qemu_ld8u(val, EA, ctx->mem_idx);
4035
gen_qemu_st8(val, EA, ctx->mem_idx);
4036
tcg_temp_free(val);
4037
tcg_temp_free(EA);
3607
//op_ldst(lbz);
3608
op_ldst(stb);
4038
3609
#endif
4039
3610
}
4040
3611
4042
3613
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
4043
3614
{
4044
3615
/* XXX: specification say this is treated as a load by the MMU */
4045
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
4046
gen_addr_reg_index(t0, ctx);
4047
gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4048
tcg_temp_free(t0);
3616
gen_addr_reg_index(ctx);
3617
op_ldst(lbz);
4049
3618
}
4050
3619
4051
3620
/* dcbt */
4068
3637
4069
3638
/* dcbz */
4070
3639
#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
4071
static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
4072
/* 32 bytes cache line size */
4073
{
4074
#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
4075
#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
4076
#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
4077
#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
4078
#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
4079
#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
4080
#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
4081
#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
4082
GEN_MEM_FUNCS(dcbz_l32),
4083
},
4084
/* 64 bytes cache line size */
4085
{
4086
#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
4087
#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
4088
#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
4089
#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
4090
#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
4091
#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
4092
#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
4093
#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
4094
GEN_MEM_FUNCS(dcbz_l64),
4095
},
4096
/* 128 bytes cache line size */
4097
{
4098
#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
4099
#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
4100
#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
4101
#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
4102
#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
4103
#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
4104
#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
4105
#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
4106
GEN_MEM_FUNCS(dcbz_l128),
4107
},
4108
/* tunable cache line size */
4109
{
4110
#define gen_op_dcbz_le_raw gen_op_dcbz_raw
4111
#define gen_op_dcbz_le_user gen_op_dcbz_user
4112
#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
4113
#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
4114
#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
4115
#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
4116
#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
4117
#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
4118
GEN_MEM_FUNCS(dcbz),
4119
},
4120
};
3640
#if defined(CONFIG_USER_ONLY)
3641
/* User-mode only */
3642
static GenOpFunc *gen_op_dcbz[4][4] = {
3643
{
3644
&gen_op_dcbz_l32_raw,
3645
&gen_op_dcbz_l32_raw,
3646
#if defined(TARGET_PPC64)
3647
&gen_op_dcbz_l32_64_raw,
3648
&gen_op_dcbz_l32_64_raw,
3649
#endif
3650
},
3651
{
3652
&gen_op_dcbz_l64_raw,
3653
&gen_op_dcbz_l64_raw,
3654
#if defined(TARGET_PPC64)
3655
&gen_op_dcbz_l64_64_raw,
3656
&gen_op_dcbz_l64_64_raw,
3657
#endif
3658
},
3659
{
3660
&gen_op_dcbz_l128_raw,
3661
&gen_op_dcbz_l128_raw,
3662
#if defined(TARGET_PPC64)
3663
&gen_op_dcbz_l128_64_raw,
3664
&gen_op_dcbz_l128_64_raw,
3665
#endif
3666
},
3667
{
3668
&gen_op_dcbz_raw,
3669
&gen_op_dcbz_raw,
3670
#if defined(TARGET_PPC64)
3671
&gen_op_dcbz_64_raw,
3672
&gen_op_dcbz_64_raw,
3673
#endif
3674
},
3675
};
3676
#else
3677
#if defined(TARGET_PPC64)
3678
/* Full system - 64 bits mode */
3679
static GenOpFunc *gen_op_dcbz[4][12] = {
3680
{
3681
&gen_op_dcbz_l32_user,
3682
&gen_op_dcbz_l32_user,
3683
&gen_op_dcbz_l32_64_user,
3684
&gen_op_dcbz_l32_64_user,
3685
&gen_op_dcbz_l32_kernel,
3686
&gen_op_dcbz_l32_kernel,
3687
&gen_op_dcbz_l32_64_kernel,
3688
&gen_op_dcbz_l32_64_kernel,
3689
#if defined(TARGET_PPC64H)
3690
&gen_op_dcbz_l32_hypv,
3691
&gen_op_dcbz_l32_hypv,
3692
&gen_op_dcbz_l32_64_hypv,
3693
&gen_op_dcbz_l32_64_hypv,
3694
#endif
3695
},
3696
{
3697
&gen_op_dcbz_l64_user,
3698
&gen_op_dcbz_l64_user,
3699
&gen_op_dcbz_l64_64_user,
3700
&gen_op_dcbz_l64_64_user,
3701
&gen_op_dcbz_l64_kernel,
3702
&gen_op_dcbz_l64_kernel,
3703
&gen_op_dcbz_l64_64_kernel,
3704
&gen_op_dcbz_l64_64_kernel,
3705
#if defined(TARGET_PPC64H)
3706
&gen_op_dcbz_l64_hypv,
3707
&gen_op_dcbz_l64_hypv,
3708
&gen_op_dcbz_l64_64_hypv,
3709
&gen_op_dcbz_l64_64_hypv,
3710
#endif
3711
},
3712
{
3713
&gen_op_dcbz_l128_user,
3714
&gen_op_dcbz_l128_user,
3715
&gen_op_dcbz_l128_64_user,
3716
&gen_op_dcbz_l128_64_user,
3717
&gen_op_dcbz_l128_kernel,
3718
&gen_op_dcbz_l128_kernel,
3719
&gen_op_dcbz_l128_64_kernel,
3720
&gen_op_dcbz_l128_64_kernel,
3721
#if defined(TARGET_PPC64H)
3722
&gen_op_dcbz_l128_hypv,
3723
&gen_op_dcbz_l128_hypv,
3724
&gen_op_dcbz_l128_64_hypv,
3725
&gen_op_dcbz_l128_64_hypv,
3726
#endif
3727
},
3728
{
3729
&gen_op_dcbz_user,
3730
&gen_op_dcbz_user,
3731
&gen_op_dcbz_64_user,
3732
&gen_op_dcbz_64_user,
3733
&gen_op_dcbz_kernel,
3734
&gen_op_dcbz_kernel,
3735
&gen_op_dcbz_64_kernel,
3736
&gen_op_dcbz_64_kernel,
3737
#if defined(TARGET_PPC64H)
3738
&gen_op_dcbz_hypv,
3739
&gen_op_dcbz_hypv,
3740
&gen_op_dcbz_64_hypv,
3741
&gen_op_dcbz_64_hypv,
3742
#endif
3743
},
3744
};
3745
#else
3746
/* Full system - 32 bits mode */
3747
static GenOpFunc *gen_op_dcbz[4][4] = {
3748
{
3749
&gen_op_dcbz_l32_user,
3750
&gen_op_dcbz_l32_user,
3751
&gen_op_dcbz_l32_kernel,
3752
&gen_op_dcbz_l32_kernel,
3753
},
3754
{
3755
&gen_op_dcbz_l64_user,
3756
&gen_op_dcbz_l64_user,
3757
&gen_op_dcbz_l64_kernel,
3758
&gen_op_dcbz_l64_kernel,
3759
},
3760
{
3761
&gen_op_dcbz_l128_user,
3762
&gen_op_dcbz_l128_user,
3763
&gen_op_dcbz_l128_kernel,
3764
&gen_op_dcbz_l128_kernel,
3765
},
3766
{
3767
&gen_op_dcbz_user,
3768
&gen_op_dcbz_user,
3769
&gen_op_dcbz_kernel,
3770
&gen_op_dcbz_kernel,
3771
},
3772
};
3773
#endif
3774
#endif
4121
3775
4122
3776
static always_inline void handler_dcbz (DisasContext *ctx,
4123
3777
int dcache_line_size)
4143
3797
4144
3798
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
4145
3799
{
4146
gen_addr_reg_index(cpu_T[0], ctx);
3800
gen_addr_reg_index(ctx);
4147
3801
handler_dcbz(ctx, ctx->dcache_line_size);
4148
3802
gen_op_check_reservation();
4149
3803
}
4150
3804
4151
GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
3805
GEN_HANDLER(dcbz_970, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
4152
3806
{
4153
gen_addr_reg_index(cpu_T[0], ctx);
3807
gen_addr_reg_index(ctx);
4154
3808
if (ctx->opcode & 0x00200000)
4155
3809
handler_dcbz(ctx, ctx->dcache_line_size);
4156
3810
else
4160
3814
4161
3815
/* icbi */
4162
3816
#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
4163
#define gen_op_icbi_le_raw gen_op_icbi_raw
4164
#define gen_op_icbi_le_user gen_op_icbi_user
4165
#define gen_op_icbi_le_kernel gen_op_icbi_kernel
4166
#define gen_op_icbi_le_hypv gen_op_icbi_hypv
4167
#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
4168
#define gen_op_icbi_le_64_user gen_op_icbi_64_user
4169
#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
4170
#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
4171
static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
4172
GEN_MEM_FUNCS(icbi),
4173
};
3817
#if defined(CONFIG_USER_ONLY)
3818
/* User-mode only */
3819
static GenOpFunc *gen_op_icbi[] = {
3820
&gen_op_icbi_raw,
3821
&gen_op_icbi_raw,
3822
#if defined(TARGET_PPC64)
3823
&gen_op_icbi_64_raw,
3824
&gen_op_icbi_64_raw,
3825
#endif
3826
};
3827
#else
3828
/* Full system - 64 bits mode */
3829
#if defined(TARGET_PPC64)
3830
static GenOpFunc *gen_op_icbi[] = {
3831
&gen_op_icbi_user,
3832
&gen_op_icbi_user,
3833
&gen_op_icbi_64_user,
3834
&gen_op_icbi_64_user,
3835
&gen_op_icbi_kernel,
3836
&gen_op_icbi_kernel,
3837
&gen_op_icbi_64_kernel,
3838
&gen_op_icbi_64_kernel,
3839
#if defined(TARGET_PPC64H)
3840
&gen_op_icbi_hypv,
3841
&gen_op_icbi_hypv,
3842
&gen_op_icbi_64_hypv,
3843
&gen_op_icbi_64_hypv,
3844
#endif
3845
};
3846
#else
3847
/* Full system - 32 bits mode */
3848
static GenOpFunc *gen_op_icbi[] = {
3849
&gen_op_icbi_user,
3850
&gen_op_icbi_user,
3851
&gen_op_icbi_kernel,
3852
&gen_op_icbi_kernel,
3853
};
3854
#endif
3855
#endif
4174
3856
4175
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
3857
GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
4176
3858
{
4177
3859
/* NIP cannot be restored if the memory exception comes from an helper */
4178
3860
gen_update_nip(ctx, ctx->nip - 4);
4179
gen_addr_reg_index(cpu_T[0], ctx);
3861
gen_addr_reg_index(ctx);
4180
3862
op_icbi();
4181
3863
}
4182
3864
4202
3884
GEN_EXCP_PRIVREG(ctx);
4203
3885
return;
4204
3886
}
4205
tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
3887
gen_op_set_T1(SR(ctx->opcode));
4206
3888
gen_op_load_sr();
4207
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3889
gen_op_store_T0_gpr(rD(ctx->opcode));
4208
3890
#endif
4209
3891
}
4210
3892
4218
3900
GEN_EXCP_PRIVREG(ctx);
4219
3901
return;
4220
3902
}
4221
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3903
gen_op_load_gpr_T1(rB(ctx->opcode));
4222
3904
gen_op_srli_T1(28);
4223
3905
gen_op_load_sr();
4224
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3906
gen_op_store_T0_gpr(rD(ctx->opcode));
4225
3907
#endif
4226
3908
}
4227
3909
4235
3917
GEN_EXCP_PRIVREG(ctx);
4236
3918
return;
4237
3919
}
4238
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4239
tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
3920
gen_op_load_gpr_T0(rS(ctx->opcode));
3921
gen_op_set_T1(SR(ctx->opcode));
4240
3922
gen_op_store_sr();
4241
3923
#endif
4242
3924
}
4251
3933
GEN_EXCP_PRIVREG(ctx);
4252
3934
return;
4253
3935
}
4254
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4255
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3936
gen_op_load_gpr_T0(rS(ctx->opcode));
3937
gen_op_load_gpr_T1(rB(ctx->opcode));
4256
3938
gen_op_srli_T1(28);
4257
3939
gen_op_store_sr();
4258
3940
#endif
4261
3943
#if defined(TARGET_PPC64)
4262
3944
/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4263
3945
/* mfsr */
4264
GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
3946
GEN_HANDLER(mfsr_64b, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
4265
3947
{
4266
3948
#if defined(CONFIG_USER_ONLY)
4267
3949
GEN_EXCP_PRIVREG(ctx);
4270
3952
GEN_EXCP_PRIVREG(ctx);
4271
3953
return;
4272
3954
}
4273
tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
3955
gen_op_set_T1(SR(ctx->opcode));
4274
3956
gen_op_load_slb();
4275
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3957
gen_op_store_T0_gpr(rD(ctx->opcode));
4276
3958
#endif
4277
3959
}
4278
3960
4279
3961
/* mfsrin */
4280
GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4281
PPC_SEGMENT_64B)
3962
GEN_HANDLER(mfsrin_64b, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT_64B)
4282
3963
{
4283
3964
#if defined(CONFIG_USER_ONLY)
4284
3965
GEN_EXCP_PRIVREG(ctx);
4287
3968
GEN_EXCP_PRIVREG(ctx);
4288
3969
return;
4289
3970
}
4290
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
3971
gen_op_load_gpr_T1(rB(ctx->opcode));
4291
3972
gen_op_srli_T1(28);
4292
3973
gen_op_load_slb();
4293
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3974
gen_op_store_T0_gpr(rD(ctx->opcode));
4294
3975
#endif
4295
3976
}
4296
3977
4297
3978
/* mtsr */
4298
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
3979
GEN_HANDLER(mtsr_64b, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
4299
3980
{
4300
3981
#if defined(CONFIG_USER_ONLY)
4301
3982
GEN_EXCP_PRIVREG(ctx);
4304
3985
GEN_EXCP_PRIVREG(ctx);
4305
3986
return;
4306
3987
}
4307
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4308
tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
3988
gen_op_load_gpr_T0(rS(ctx->opcode));
3989
gen_op_set_T1(SR(ctx->opcode));
4309
3990
gen_op_store_slb();
4310
3991
#endif
4311
3992
}
4312
3993
4313
3994
/* mtsrin */
4314
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4315
PPC_SEGMENT_64B)
3995
GEN_HANDLER(mtsrin_64b, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT_64B)
4316
3996
{
4317
3997
#if defined(CONFIG_USER_ONLY)
4318
3998
GEN_EXCP_PRIVREG(ctx);
4321
4001
GEN_EXCP_PRIVREG(ctx);
4322
4002
return;
4323
4003
}
4324
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4325
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4004
gen_op_load_gpr_T0(rS(ctx->opcode));
4005
gen_op_load_gpr_T1(rB(ctx->opcode));
4326
4006
gen_op_srli_T1(28);
4327
4007
gen_op_store_slb();
4328
4008
#endif
4338
4018
GEN_EXCP_PRIVOPC(ctx);
4339
4019
#else
4340
4020
if (unlikely(!ctx->supervisor)) {
4021
if (loglevel != 0)
4022
fprintf(logfile, "%s: ! supervisor\n", __func__);
4341
4023
GEN_EXCP_PRIVOPC(ctx);
4342
4024
return;
4343
4025
}
4355
4037
GEN_EXCP_PRIVOPC(ctx);
4356
4038
return;
4357
4039
}
4358
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4040
gen_op_load_gpr_T0(rB(ctx->opcode));
4359
4041
#if defined(TARGET_PPC64)
4360
4042
if (ctx->sf_mode)
4361
4043
gen_op_tlbie_64();
4390
4072
GEN_EXCP_PRIVOPC(ctx);
4391
4073
#else
4392
4074
if (unlikely(!ctx->supervisor)) {
4075
if (loglevel != 0)
4076
fprintf(logfile, "%s: ! supervisor\n", __func__);
4393
4077
GEN_EXCP_PRIVOPC(ctx);
4394
4078
return;
4395
4079
}
4407
4091
GEN_EXCP_PRIVOPC(ctx);
4408
4092
return;
4409
4093
}
4410
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4094
gen_op_load_gpr_T0(rB(ctx->opcode));
4411
4095
gen_op_slbie();
4412
4096
#endif
4413
4097
}
4417
4101
/* Optional: */
4418
4102
#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4419
4103
#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
4420
static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4421
GEN_MEM_FUNCS(eciwx),
4422
};
4423
static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4424
GEN_MEM_FUNCS(ecowx),
4425
};
4104
#if defined(CONFIG_USER_ONLY)
4105
/* User-mode only */
4106
static GenOpFunc *gen_op_eciwx[] = {
4107
&gen_op_eciwx_raw,
4108
&gen_op_eciwx_le_raw,
4109
#if defined(TARGET_PPC64)
4110
&gen_op_eciwx_64_raw,
4111
&gen_op_eciwx_le_64_raw,
4112
#endif
4113
};
4114
static GenOpFunc *gen_op_ecowx[] = {
4115
&gen_op_ecowx_raw,
4116
&gen_op_ecowx_le_raw,
4117
#if defined(TARGET_PPC64)
4118
&gen_op_ecowx_64_raw,
4119
&gen_op_ecowx_le_64_raw,
4120
#endif
4121
};
4122
#else
4123
#if defined(TARGET_PPC64)
4124
/* Full system - 64 bits mode */
4125
static GenOpFunc *gen_op_eciwx[] = {
4126
&gen_op_eciwx_user,
4127
&gen_op_eciwx_le_user,
4128
&gen_op_eciwx_64_user,
4129
&gen_op_eciwx_le_64_user,
4130
&gen_op_eciwx_kernel,
4131
&gen_op_eciwx_le_kernel,
4132
&gen_op_eciwx_64_kernel,
4133
&gen_op_eciwx_le_64_kernel,
4134
#if defined(TARGET_PPC64H)
4135
&gen_op_eciwx_hypv,
4136
&gen_op_eciwx_le_hypv,
4137
&gen_op_eciwx_64_hypv,
4138
&gen_op_eciwx_le_64_hypv,
4139
#endif
4140
};
4141
static GenOpFunc *gen_op_ecowx[] = {
4142
&gen_op_ecowx_user,
4143
&gen_op_ecowx_le_user,
4144
&gen_op_ecowx_64_user,
4145
&gen_op_ecowx_le_64_user,
4146
&gen_op_ecowx_kernel,
4147
&gen_op_ecowx_le_kernel,
4148
&gen_op_ecowx_64_kernel,
4149
&gen_op_ecowx_le_64_kernel,
4150
#if defined(TARGET_PPC64H)
4151
&gen_op_ecowx_hypv,
4152
&gen_op_ecowx_le_hypv,
4153
&gen_op_ecowx_64_hypv,
4154
&gen_op_ecowx_le_64_hypv,
4155
#endif
4156
};
4157
#else
4158
/* Full system - 32 bits mode */
4159
static GenOpFunc *gen_op_eciwx[] = {
4160
&gen_op_eciwx_user,
4161
&gen_op_eciwx_le_user,
4162
&gen_op_eciwx_kernel,
4163
&gen_op_eciwx_le_kernel,
4164
};
4165
static GenOpFunc *gen_op_ecowx[] = {
4166
&gen_op_ecowx_user,
4167
&gen_op_ecowx_le_user,
4168
&gen_op_ecowx_kernel,
4169
&gen_op_ecowx_le_kernel,
4170
};
4171
#endif
4172
#endif
4426
4173
4427
4174
/* eciwx */
4428
4175
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4429
4176
{
4430
4177
/* Should check EAR[E] & alignment ! */
4431
gen_addr_reg_index(cpu_T[0], ctx);
4178
gen_addr_reg_index(ctx);
4432
4179
op_eciwx();
4433
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4180
gen_op_store_T0_gpr(rD(ctx->opcode));
4434
4181
}
4435
4182
4436
4183
/* ecowx */
4437
4184
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4438
4185
{
4439
4186
/* Should check EAR[E] & alignment ! */
4440
gen_addr_reg_index(cpu_T[0], ctx);
4441
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4187
gen_addr_reg_index(ctx);
4188
gen_op_load_gpr_T1(rS(ctx->opcode));
4442
4189
op_ecowx();
4443
4190
}
4444
4191
4446
4193
/* abs - abs. */
4447
4194
GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4448
4195
{
4449
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4196
gen_op_load_gpr_T0(rA(ctx->opcode));
4450
4197
gen_op_POWER_abs();
4451
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4198
gen_op_store_T0_gpr(rD(ctx->opcode));
4452
4199
if (unlikely(Rc(ctx->opcode) != 0))
4453
gen_set_Rc0(ctx, cpu_T[0]);
4200
gen_set_Rc0(ctx);
4454
4201
}
4455
4202
4456
4203
/* abso - abso. */
4457
4204
GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4458
4205
{
4459
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4206
gen_op_load_gpr_T0(rA(ctx->opcode));
4460
4207
gen_op_POWER_abso();
4461
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4208
gen_op_store_T0_gpr(rD(ctx->opcode));
4462
4209
if (unlikely(Rc(ctx->opcode) != 0))
4463
gen_set_Rc0(ctx, cpu_T[0]);
4210
gen_set_Rc0(ctx);
4464
4211
}
4465
4212
4466
4213
/* clcs */
4467
4214
GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
4468
4215
{
4469
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4216
gen_op_load_gpr_T0(rA(ctx->opcode));
4470
4217
gen_op_POWER_clcs();
4471
/* Rc=1 sets CR0 to an undefined state */
4472
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4218
gen_op_store_T0_gpr(rD(ctx->opcode));
4473
4219
}
4474
4220
4475
4221
/* div - div. */
4476
4222
GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4477
4223
{
4478
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4479
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4224
gen_op_load_gpr_T0(rA(ctx->opcode));
4225
gen_op_load_gpr_T1(rB(ctx->opcode));
4480
4226
gen_op_POWER_div();
4481
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4227
gen_op_store_T0_gpr(rD(ctx->opcode));
4482
4228
if (unlikely(Rc(ctx->opcode) != 0))
4483
gen_set_Rc0(ctx, cpu_T[0]);
4229
gen_set_Rc0(ctx);
4484
4230
}
4485
4231
4486
4232
/* divo - divo. */
4487
4233
GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4488
4234
{
4489
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4490
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4235
gen_op_load_gpr_T0(rA(ctx->opcode));
4236
gen_op_load_gpr_T1(rB(ctx->opcode));
4491
4237
gen_op_POWER_divo();
4492
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4238
gen_op_store_T0_gpr(rD(ctx->opcode));
4493
4239
if (unlikely(Rc(ctx->opcode) != 0))
4494
gen_set_Rc0(ctx, cpu_T[0]);
4240
gen_set_Rc0(ctx);
4495
4241
}
4496
4242
4497
4243
/* divs - divs. */
4498
4244
GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4499
4245
{
4500
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4501
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4246
gen_op_load_gpr_T0(rA(ctx->opcode));
4247
gen_op_load_gpr_T1(rB(ctx->opcode));
4502
4248
gen_op_POWER_divs();
4503
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4249
gen_op_store_T0_gpr(rD(ctx->opcode));
4504
4250
if (unlikely(Rc(ctx->opcode) != 0))
4505
gen_set_Rc0(ctx, cpu_T[0]);
4251
gen_set_Rc0(ctx);
4506
4252
}
4507
4253
4508
4254
/* divso - divso. */
4509
4255
GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4510
4256
{
4511
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4512
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4257
gen_op_load_gpr_T0(rA(ctx->opcode));
4258
gen_op_load_gpr_T1(rB(ctx->opcode));
4513
4259
gen_op_POWER_divso();
4514
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4260
gen_op_store_T0_gpr(rD(ctx->opcode));
4515
4261
if (unlikely(Rc(ctx->opcode) != 0))
4516
gen_set_Rc0(ctx, cpu_T[0]);
4262
gen_set_Rc0(ctx);
4517
4263
}
4518
4264
4519
4265
/* doz - doz. */
4520
4266
GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4521
4267
{
4522
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4523
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4268
gen_op_load_gpr_T0(rA(ctx->opcode));
4269
gen_op_load_gpr_T1(rB(ctx->opcode));
4524
4270
gen_op_POWER_doz();
4525
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4271
gen_op_store_T0_gpr(rD(ctx->opcode));
4526
4272
if (unlikely(Rc(ctx->opcode) != 0))
4527
gen_set_Rc0(ctx, cpu_T[0]);
4273
gen_set_Rc0(ctx);
4528
4274
}
4529
4275
4530
4276
/* dozo - dozo. */
4531
4277
GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4532
4278
{
4533
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4534
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4279
gen_op_load_gpr_T0(rA(ctx->opcode));
4280
gen_op_load_gpr_T1(rB(ctx->opcode));
4535
4281
gen_op_POWER_dozo();
4536
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4282
gen_op_store_T0_gpr(rD(ctx->opcode));
4537
4283
if (unlikely(Rc(ctx->opcode) != 0))
4538
gen_set_Rc0(ctx, cpu_T[0]);
4284
gen_set_Rc0(ctx);
4539
4285
}
4540
4286
4541
4287
/* dozi */
4542
4288
GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4543
4289
{
4544
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4545
tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
4290
gen_op_load_gpr_T0(rA(ctx->opcode));
4291
gen_op_set_T1(SIMM(ctx->opcode));
4546
4292
gen_op_POWER_doz();
4547
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4293
gen_op_store_T0_gpr(rD(ctx->opcode));
4548
4294
}
4549
4295
4550
/* As lscbx load from memory byte after byte, it's always endian safe.
4551
* Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
4552
*/
4296
/* As lscbx load from memory byte after byte, it's always endian safe */
4553
4297
#define op_POWER_lscbx(start, ra, rb) \
4554
4298
(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
4555
#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
4556
#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
4557
#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
4558
#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
4559
#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
4560
#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
4561
#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
4562
#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4563
#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4564
#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4565
#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4566
#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4567
static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4568
GEN_MEM_FUNCS(POWER_lscbx),
4569
};
4299
#if defined(CONFIG_USER_ONLY)
4300
static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4301
&gen_op_POWER_lscbx_raw,
4302
&gen_op_POWER_lscbx_raw,
4303
};
4304
#else
4305
static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4306
&gen_op_POWER_lscbx_user,
4307
&gen_op_POWER_lscbx_user,
4308
&gen_op_POWER_lscbx_kernel,
4309
&gen_op_POWER_lscbx_kernel,
4310
};
4311
#endif
4570
4312
4571
4313
/* lscbx - lscbx. */
4572
4314
GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4574
4316
int ra = rA(ctx->opcode);
4575
4317
int rb = rB(ctx->opcode);
4576
4318
4577
gen_addr_reg_index(cpu_T[0], ctx);
4319
gen_addr_reg_index(ctx);
4578
4320
if (ra == 0) {
4579
4321
ra = rb;
4580
4322
}
4581
4323
/* NIP cannot be restored if the memory exception comes from an helper */
4582
4324
gen_update_nip(ctx, ctx->nip - 4);
4583
tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
4584
tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
4585
tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
4325
gen_op_load_xer_bc();
4326
gen_op_load_xer_cmp();
4586
4327
op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4587
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4588
tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
4328
gen_op_store_xer_bc();
4589
4329
if (unlikely(Rc(ctx->opcode) != 0))
4590
gen_set_Rc0(ctx, cpu_T[0]);
4330
gen_set_Rc0(ctx);
4591
4331
}
4592
4332
4593
4333
/* maskg - maskg. */
4594
4334
GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4595
4335
{
4596
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4597
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4336
gen_op_load_gpr_T0(rS(ctx->opcode));
4337
gen_op_load_gpr_T1(rB(ctx->opcode));
4598
4338
gen_op_POWER_maskg();
4599
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4339
gen_op_store_T0_gpr(rA(ctx->opcode));
4600
4340
if (unlikely(Rc(ctx->opcode) != 0))
4601
gen_set_Rc0(ctx, cpu_T[0]);
4341
gen_set_Rc0(ctx);
4602
4342
}
4603
4343
4604
4344
/* maskir - maskir. */
4605
4345
GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4606
4346
{
4607
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4608
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4609
tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4347
gen_op_load_gpr_T0(rA(ctx->opcode));
4348
gen_op_load_gpr_T1(rS(ctx->opcode));
4349
gen_op_load_gpr_T2(rB(ctx->opcode));
4610
4350
gen_op_POWER_maskir();
4611
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4351
gen_op_store_T0_gpr(rA(ctx->opcode));
4612
4352
if (unlikely(Rc(ctx->opcode) != 0))
4613
gen_set_Rc0(ctx, cpu_T[0]);
4353
gen_set_Rc0(ctx);
4614
4354
}
4615
4355
4616
4356
/* mul - mul. */
4617
4357
GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4618
4358
{
4619
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4620
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4359
gen_op_load_gpr_T0(rA(ctx->opcode));
4360
gen_op_load_gpr_T1(rB(ctx->opcode));
4621
4361
gen_op_POWER_mul();
4622
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4362
gen_op_store_T0_gpr(rD(ctx->opcode));
4623
4363
if (unlikely(Rc(ctx->opcode) != 0))
4624
gen_set_Rc0(ctx, cpu_T[0]);
4364
gen_set_Rc0(ctx);
4625
4365
}
4626
4366
4627
4367
/* mulo - mulo. */
4628
4368
GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4629
4369
{
4630
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4631
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4370
gen_op_load_gpr_T0(rA(ctx->opcode));
4371
gen_op_load_gpr_T1(rB(ctx->opcode));
4632
4372
gen_op_POWER_mulo();
4633
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4373
gen_op_store_T0_gpr(rD(ctx->opcode));
4634
4374
if (unlikely(Rc(ctx->opcode) != 0))
4635
gen_set_Rc0(ctx, cpu_T[0]);
4375
gen_set_Rc0(ctx);
4636
4376
}
4637
4377
4638
4378
/* nabs - nabs. */
4639
4379
GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4640
4380
{
4641
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4381
gen_op_load_gpr_T0(rA(ctx->opcode));
4642
4382
gen_op_POWER_nabs();
4643
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4383
gen_op_store_T0_gpr(rD(ctx->opcode));
4644
4384
if (unlikely(Rc(ctx->opcode) != 0))
4645
gen_set_Rc0(ctx, cpu_T[0]);
4385
gen_set_Rc0(ctx);
4646
4386
}
4647
4387
4648
4388
/* nabso - nabso. */
4649
4389
GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4650
4390
{
4651
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4391
gen_op_load_gpr_T0(rA(ctx->opcode));
4652
4392
gen_op_POWER_nabso();
4653
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4393
gen_op_store_T0_gpr(rD(ctx->opcode));
4654
4394
if (unlikely(Rc(ctx->opcode) != 0))
4655
gen_set_Rc0(ctx, cpu_T[0]);
4395
gen_set_Rc0(ctx);
4656
4396
}
4657
4397
4658
4398
/* rlmi - rlmi. */
4662
4402
4663
4403
mb = MB(ctx->opcode);
4664
4404
me = ME(ctx->opcode);
4665
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4666
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4667
tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4405
gen_op_load_gpr_T0(rS(ctx->opcode));
4406
gen_op_load_gpr_T1(rA(ctx->opcode));
4407
gen_op_load_gpr_T2(rB(ctx->opcode));
4668
4408
gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4669
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4409
gen_op_store_T0_gpr(rA(ctx->opcode));
4670
4410
if (unlikely(Rc(ctx->opcode) != 0))
4671
gen_set_Rc0(ctx, cpu_T[0]);
4411
gen_set_Rc0(ctx);
4672
4412
}
4673
4413
4674
4414
/* rrib - rrib. */
4675
4415
GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4676
4416
{
4677
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4678
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4679
tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
4417
gen_op_load_gpr_T0(rS(ctx->opcode));
4418
gen_op_load_gpr_T1(rA(ctx->opcode));
4419
gen_op_load_gpr_T2(rB(ctx->opcode));
4680
4420
gen_op_POWER_rrib();
4681
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4421
gen_op_store_T0_gpr(rA(ctx->opcode));
4682
4422
if (unlikely(Rc(ctx->opcode) != 0))
4683
gen_set_Rc0(ctx, cpu_T[0]);
4423
gen_set_Rc0(ctx);
4684
4424
}
4685
4425
4686
4426
/* sle - sle. */
4687
4427
GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4688
4428
{
4689
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4690
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4429
gen_op_load_gpr_T0(rS(ctx->opcode));
4430
gen_op_load_gpr_T1(rB(ctx->opcode));
4691
4431
gen_op_POWER_sle();
4692
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4432
gen_op_store_T0_gpr(rA(ctx->opcode));
4693
4433
if (unlikely(Rc(ctx->opcode) != 0))
4694
gen_set_Rc0(ctx, cpu_T[0]);
4434
gen_set_Rc0(ctx);
4695
4435
}
4696
4436
4697
4437
/* sleq - sleq. */
4698
4438
GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4699
4439
{
4700
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4701
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4440
gen_op_load_gpr_T0(rS(ctx->opcode));
4441
gen_op_load_gpr_T1(rB(ctx->opcode));
4702
4442
gen_op_POWER_sleq();
4703
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4443
gen_op_store_T0_gpr(rA(ctx->opcode));
4704
4444
if (unlikely(Rc(ctx->opcode) != 0))
4705
gen_set_Rc0(ctx, cpu_T[0]);
4445
gen_set_Rc0(ctx);
4706
4446
}
4707
4447
4708
4448
/* sliq - sliq. */
4709
4449
GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4710
4450
{
4711
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4712
tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4451
gen_op_load_gpr_T0(rS(ctx->opcode));
4452
gen_op_set_T1(SH(ctx->opcode));
4713
4453
gen_op_POWER_sle();
4714
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4454
gen_op_store_T0_gpr(rA(ctx->opcode));
4715
4455
if (unlikely(Rc(ctx->opcode) != 0))
4716
gen_set_Rc0(ctx, cpu_T[0]);
4456
gen_set_Rc0(ctx);
4717
4457
}
4718
4458
4719
4459
/* slliq - slliq. */
4720
4460
GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4721
4461
{
4722
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4723
tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4462
gen_op_load_gpr_T0(rS(ctx->opcode));
4463
gen_op_set_T1(SH(ctx->opcode));
4724
4464
gen_op_POWER_sleq();
4725
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4465
gen_op_store_T0_gpr(rA(ctx->opcode));
4726
4466
if (unlikely(Rc(ctx->opcode) != 0))
4727
gen_set_Rc0(ctx, cpu_T[0]);
4467
gen_set_Rc0(ctx);
4728
4468
}
4729
4469
4730
4470
/* sllq - sllq. */
4731
4471
GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4732
4472
{
4733
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4734
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4473
gen_op_load_gpr_T0(rS(ctx->opcode));
4474
gen_op_load_gpr_T1(rB(ctx->opcode));
4735
4475
gen_op_POWER_sllq();
4736
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4476
gen_op_store_T0_gpr(rA(ctx->opcode));
4737
4477
if (unlikely(Rc(ctx->opcode) != 0))
4738
gen_set_Rc0(ctx, cpu_T[0]);
4478
gen_set_Rc0(ctx);
4739
4479
}
4740
4480
4741
4481
/* slq - slq. */
4742
4482
GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4743
4483
{
4744
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4745
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4484
gen_op_load_gpr_T0(rS(ctx->opcode));
4485
gen_op_load_gpr_T1(rB(ctx->opcode));
4746
4486
gen_op_POWER_slq();
4747
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4487
gen_op_store_T0_gpr(rA(ctx->opcode));
4748
4488
if (unlikely(Rc(ctx->opcode) != 0))
4749
gen_set_Rc0(ctx, cpu_T[0]);
4489
gen_set_Rc0(ctx);
4750
4490
}
4751
4491
4752
4492
/* sraiq - sraiq. */
4753
4493
GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4754
4494
{
4755
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4756
tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4495
gen_op_load_gpr_T0(rS(ctx->opcode));
4496
gen_op_set_T1(SH(ctx->opcode));
4757
4497
gen_op_POWER_sraq();
4758
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4498
gen_op_store_T0_gpr(rA(ctx->opcode));
4759
4499
if (unlikely(Rc(ctx->opcode) != 0))
4760
gen_set_Rc0(ctx, cpu_T[0]);
4500
gen_set_Rc0(ctx);
4761
4501
}
4762
4502
4763
4503
/* sraq - sraq. */
4764
4504
GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4765
4505
{
4766
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4767
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4506
gen_op_load_gpr_T0(rS(ctx->opcode));
4507
gen_op_load_gpr_T1(rB(ctx->opcode));
4768
4508
gen_op_POWER_sraq();
4769
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4509
gen_op_store_T0_gpr(rA(ctx->opcode));
4770
4510
if (unlikely(Rc(ctx->opcode) != 0))
4771
gen_set_Rc0(ctx, cpu_T[0]);
4511
gen_set_Rc0(ctx);
4772
4512
}
4773
4513
4774
4514
/* sre - sre. */
4775
4515
GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4776
4516
{
4777
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4778
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4517
gen_op_load_gpr_T0(rS(ctx->opcode));
4518
gen_op_load_gpr_T1(rB(ctx->opcode));
4779
4519
gen_op_POWER_sre();
4780
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4520
gen_op_store_T0_gpr(rA(ctx->opcode));
4781
4521
if (unlikely(Rc(ctx->opcode) != 0))
4782
gen_set_Rc0(ctx, cpu_T[0]);
4522
gen_set_Rc0(ctx);
4783
4523
}
4784
4524
4785
4525
/* srea - srea. */
4786
4526
GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4787
4527
{
4788
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4789
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4528
gen_op_load_gpr_T0(rS(ctx->opcode));
4529
gen_op_load_gpr_T1(rB(ctx->opcode));
4790
4530
gen_op_POWER_srea();
4791
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4531
gen_op_store_T0_gpr(rA(ctx->opcode));
4792
4532
if (unlikely(Rc(ctx->opcode) != 0))
4793
gen_set_Rc0(ctx, cpu_T[0]);
4533
gen_set_Rc0(ctx);
4794
4534
}
4795
4535
4796
4536
/* sreq */
4797
4537
GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4798
4538
{
4799
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4800
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4539
gen_op_load_gpr_T0(rS(ctx->opcode));
4540
gen_op_load_gpr_T1(rB(ctx->opcode));
4801
4541
gen_op_POWER_sreq();
4802
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4542
gen_op_store_T0_gpr(rA(ctx->opcode));
4803
4543
if (unlikely(Rc(ctx->opcode) != 0))
4804
gen_set_Rc0(ctx, cpu_T[0]);
4544
gen_set_Rc0(ctx);
4805
4545
}
4806
4546
4807
4547
/* sriq */
4808
4548
GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4809
4549
{
4810
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4811
tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4550
gen_op_load_gpr_T0(rS(ctx->opcode));
4551
gen_op_set_T1(SH(ctx->opcode));
4812
4552
gen_op_POWER_srq();
4813
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4553
gen_op_store_T0_gpr(rA(ctx->opcode));
4814
4554
if (unlikely(Rc(ctx->opcode) != 0))
4815
gen_set_Rc0(ctx, cpu_T[0]);
4555
gen_set_Rc0(ctx);
4816
4556
}
4817
4557
4818
4558
/* srliq */
4819
4559
GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4820
4560
{
4821
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4822
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4823
tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
4561
gen_op_load_gpr_T0(rS(ctx->opcode));
4562
gen_op_load_gpr_T1(rB(ctx->opcode));
4563
gen_op_set_T1(SH(ctx->opcode));
4824
4564
gen_op_POWER_srlq();
4825
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4565
gen_op_store_T0_gpr(rA(ctx->opcode));
4826
4566
if (unlikely(Rc(ctx->opcode) != 0))
4827
gen_set_Rc0(ctx, cpu_T[0]);
4567
gen_set_Rc0(ctx);
4828
4568
}
4829
4569
4830
4570
/* srlq */
4831
4571
GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4832
4572
{
4833
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4834
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4573
gen_op_load_gpr_T0(rS(ctx->opcode));
4574
gen_op_load_gpr_T1(rB(ctx->opcode));
4835
4575
gen_op_POWER_srlq();
4836
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4576
gen_op_store_T0_gpr(rA(ctx->opcode));
4837
4577
if (unlikely(Rc(ctx->opcode) != 0))
4838
gen_set_Rc0(ctx, cpu_T[0]);
4578
gen_set_Rc0(ctx);
4839
4579
}
4840
4580
4841
4581
/* srq */
4842
4582
GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4843
4583
{
4844
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4845
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
4584
gen_op_load_gpr_T0(rS(ctx->opcode));
4585
gen_op_load_gpr_T1(rB(ctx->opcode));
4846
4586
gen_op_POWER_srq();
4847
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
4587
gen_op_store_T0_gpr(rA(ctx->opcode));
4848
4588
if (unlikely(Rc(ctx->opcode) != 0))
4849
gen_set_Rc0(ctx, cpu_T[0]);
4589
gen_set_Rc0(ctx);
4850
4590
}
4851
4591
4852
4592
/* PowerPC 602 specific instructions */
4874
4614
GEN_EXCP_PRIVOPC(ctx);
4875
4615
return;
4876
4616
}
4877
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4617
gen_op_load_gpr_T0(rA(ctx->opcode));
4878
4618
gen_op_602_mfrom();
4879
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4619
gen_op_store_T0_gpr(rD(ctx->opcode));
4880
4620
#endif
4881
4621
}
4882
4622
4883
4623
/* 602 - 603 - G2 TLB management */
4884
4624
/* tlbld */
4885
GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4625
GEN_HANDLER(tlbld_6xx, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
4886
4626
{
4887
4627
#if defined(CONFIG_USER_ONLY)
4888
4628
GEN_EXCP_PRIVOPC(ctx);
4891
4631
GEN_EXCP_PRIVOPC(ctx);
4892
4632
return;
4893
4633
}
4894
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4634
gen_op_load_gpr_T0(rB(ctx->opcode));
4895
4635
gen_op_6xx_tlbld();
4896
4636
#endif
4897
4637
}
4898
4638
4899
4639
/* tlbli */
4900
GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4640
GEN_HANDLER(tlbli_6xx, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
4901
4641
{
4902
4642
#if defined(CONFIG_USER_ONLY)
4903
4643
GEN_EXCP_PRIVOPC(ctx);
4906
4646
GEN_EXCP_PRIVOPC(ctx);
4907
4647
return;
4908
4648
}
4909
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4649
gen_op_load_gpr_T0(rB(ctx->opcode));
4910
4650
gen_op_6xx_tlbli();
4911
4651
#endif
4912
4652
}
4913
4653
4914
4654
/* 74xx TLB management */
4915
4655
/* tlbld */
4916
GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4656
GEN_HANDLER(tlbld_74xx, 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
4917
4657
{
4918
4658
#if defined(CONFIG_USER_ONLY)
4919
4659
GEN_EXCP_PRIVOPC(ctx);
4922
4662
GEN_EXCP_PRIVOPC(ctx);
4923
4663
return;
4924
4664
}
4925
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4665
gen_op_load_gpr_T0(rB(ctx->opcode));
4926
4666
gen_op_74xx_tlbld();
4927
4667
#endif
4928
4668
}
4929
4669
4930
4670
/* tlbli */
4931
GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4671
GEN_HANDLER(tlbli_74xx, 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
4932
4672
{
4933
4673
#if defined(CONFIG_USER_ONLY)
4934
4674
GEN_EXCP_PRIVOPC(ctx);
4937
4677
GEN_EXCP_PRIVOPC(ctx);
4938
4678
return;
4939
4679
}
4940
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
4680
gen_op_load_gpr_T0(rB(ctx->opcode));
4941
4681
gen_op_74xx_tlbli();
4942
4682
#endif
4943
4683
}
4981
4721
int ra = rA(ctx->opcode);
4982
4722
int rd = rD(ctx->opcode);
4983
4723
4984
gen_addr_reg_index(cpu_T[0], ctx);
4724
gen_addr_reg_index(ctx);
4985
4725
gen_op_POWER_mfsri();
4986
tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
4726
gen_op_store_T0_gpr(rd);
4987
4727
if (ra != 0 && ra != rd)
4988
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
4728
gen_op_store_T1_gpr(ra);
4989
4729
#endif
4990
4730
}
4991
4731
4998
4738
GEN_EXCP_PRIVOPC(ctx);
4999
4739
return;
5000
4740
}
5001
gen_addr_reg_index(cpu_T[0], ctx);
4741
gen_addr_reg_index(ctx);
5002
4742
gen_op_POWER_rac();
5003
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
4743
gen_op_store_T0_gpr(rD(ctx->opcode));
5004
4744
#endif
5005
4745
}
5006
4746
5022
4762
5023
4763
/* POWER2 specific instructions */
5024
4764
/* Quad manipulation (load/store two floats at a time) */
5025
/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
5026
4765
#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
5027
4766
#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
5028
#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
5029
#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
5030
#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
5031
#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
5032
#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
5033
#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
5034
#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
5035
#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
5036
#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
5037
#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
5038
#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
5039
#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
5040
#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
5041
#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
5042
#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
5043
#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
5044
static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
5045
GEN_MEM_FUNCS(POWER2_lfq),
5046
};
5047
static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
5048
GEN_MEM_FUNCS(POWER2_stfq),
5049
};
4767
#if defined(CONFIG_USER_ONLY)
4768
static GenOpFunc *gen_op_POWER2_lfq[] = {
4769
&gen_op_POWER2_lfq_le_raw,
4770
&gen_op_POWER2_lfq_raw,
4771
};
4772
static GenOpFunc *gen_op_POWER2_stfq[] = {
4773
&gen_op_POWER2_stfq_le_raw,
4774
&gen_op_POWER2_stfq_raw,
4775
};
4776
#else
4777
static GenOpFunc *gen_op_POWER2_lfq[] = {
4778
&gen_op_POWER2_lfq_le_user,
4779
&gen_op_POWER2_lfq_user,
4780
&gen_op_POWER2_lfq_le_kernel,
4781
&gen_op_POWER2_lfq_kernel,
4782
};
4783
static GenOpFunc *gen_op_POWER2_stfq[] = {
4784
&gen_op_POWER2_stfq_le_user,
4785
&gen_op_POWER2_stfq_user,
4786
&gen_op_POWER2_stfq_le_kernel,
4787
&gen_op_POWER2_stfq_kernel,
4788
};
4789
#endif
5050
4790
5051
4791
/* lfq */
5052
4792
GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5053
4793
{
5054
4794
/* NIP cannot be restored if the memory exception comes from an helper */
5055
4795
gen_update_nip(ctx, ctx->nip - 4);
5056
gen_addr_imm_index(cpu_T[0], ctx, 0);
4796
gen_addr_imm_index(ctx, 0);
5057
4797
op_POWER2_lfq();
5058
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5059
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
4798
gen_op_store_FT0_fpr(rD(ctx->opcode));
4799
gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
5060
4800
}
5061
4801
5062
4802
/* lfqu */
5066
4806
5067
4807
/* NIP cannot be restored if the memory exception comes from an helper */
5068
4808
gen_update_nip(ctx, ctx->nip - 4);
5069
gen_addr_imm_index(cpu_T[0], ctx, 0);
4809
gen_addr_imm_index(ctx, 0);
5070
4810
op_POWER2_lfq();
5071
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5072
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
4811
gen_op_store_FT0_fpr(rD(ctx->opcode));
4812
gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
5073
4813
if (ra != 0)
5074
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
4814
gen_op_store_T0_gpr(ra);
5075
4815
}
5076
4816
5077
4817
/* lfqux */
5081
4821
5082
4822
/* NIP cannot be restored if the memory exception comes from an helper */
5083
4823
gen_update_nip(ctx, ctx->nip - 4);
5084
gen_addr_reg_index(cpu_T[0], ctx);
4824
gen_addr_reg_index(ctx);
5085
4825
op_POWER2_lfq();
5086
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5087
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
4826
gen_op_store_FT0_fpr(rD(ctx->opcode));
4827
gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
5088
4828
if (ra != 0)
5089
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
4829
gen_op_store_T0_gpr(ra);
5090
4830
}
5091
4831
5092
4832
/* lfqx */
5094
4834
{
5095
4835
/* NIP cannot be restored if the memory exception comes from an helper */
5096
4836
gen_update_nip(ctx, ctx->nip - 4);
5097
gen_addr_reg_index(cpu_T[0], ctx);
4837
gen_addr_reg_index(ctx);
5098
4838
op_POWER2_lfq();
5099
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5100
tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
4839
gen_op_store_FT0_fpr(rD(ctx->opcode));
4840
gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
5101
4841
}
5102
4842
5103
4843
/* stfq */
5105
4845
{
5106
4846
/* NIP cannot be restored if the memory exception comes from an helper */
5107
4847
gen_update_nip(ctx, ctx->nip - 4);
5108
gen_addr_imm_index(cpu_T[0], ctx, 0);
5109
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5110
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
4848
gen_addr_imm_index(ctx, 0);
4849
gen_op_load_fpr_FT0(rS(ctx->opcode));
4850
gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
5111
4851
op_POWER2_stfq();
5112
4852
}
5113
4853
5118
4858
5119
4859
/* NIP cannot be restored if the memory exception comes from an helper */
5120
4860
gen_update_nip(ctx, ctx->nip - 4);
5121
gen_addr_imm_index(cpu_T[0], ctx, 0);
5122
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5123
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
4861
gen_addr_imm_index(ctx, 0);
4862
gen_op_load_fpr_FT0(rS(ctx->opcode));
4863
gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
5124
4864
op_POWER2_stfq();
5125
4865
if (ra != 0)
5126
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
4866
gen_op_store_T0_gpr(ra);
5127
4867
}
5128
4868
5129
4869
/* stfqux */
5133
4873
5134
4874
/* NIP cannot be restored if the memory exception comes from an helper */
5135
4875
gen_update_nip(ctx, ctx->nip - 4);
5136
gen_addr_reg_index(cpu_T[0], ctx);
5137
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5138
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
4876
gen_addr_reg_index(ctx);
4877
gen_op_load_fpr_FT0(rS(ctx->opcode));
4878
gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
5139
4879
op_POWER2_stfq();
5140
4880
if (ra != 0)
5141
tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
4881
gen_op_store_T0_gpr(ra);
5142
4882
}
5143
4883
5144
4884
/* stfqx */
5146
4886
{
5147
4887
/* NIP cannot be restored if the memory exception comes from an helper */
5148
4888
gen_update_nip(ctx, ctx->nip - 4);
5149
gen_addr_reg_index(cpu_T[0], ctx);
5150
tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5151
tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
4889
gen_addr_reg_index(ctx);
4890
gen_op_load_fpr_FT0(rS(ctx->opcode));
4891
gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
5152
4892
op_POWER2_stfq();
5153
4893
}
5154
4894
5155
4895
/* BookE specific instructions */
5156
4896
/* XXX: not implemented on 440 ? */
5157
GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
4897
GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT)
5158
4898
{
5159
4899
/* XXX: TODO */
5160
4900
GEN_EXCP_INVAL(ctx);
5161
4901
}
5162
4902
5163
4903
/* XXX: not implemented on 440 ? */
5164
GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
4904
GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT)
5165
4905
{
5166
4906
#if defined(CONFIG_USER_ONLY)
5167
4907
GEN_EXCP_PRIVOPC(ctx);
5170
4910
GEN_EXCP_PRIVOPC(ctx);
5171
4911
return;
5172
4912
}
5173
gen_addr_reg_index(cpu_T[0], ctx);
4913
gen_addr_reg_index(ctx);
5174
4914
/* Use the same micro-ops as for tlbie */
5175
4915
#if defined(TARGET_PPC64)
5176
4916
if (ctx->sf_mode)
5186
4926
int opc2, int opc3,
5187
4927
int ra, int rb, int rt, int Rc)
5188
4928
{
5189
TCGv t0, t1;
5190
5191
t0 = tcg_temp_local_new(TCG_TYPE_TL);
5192
t1 = tcg_temp_local_new(TCG_TYPE_TL);
5193
4929
gen_op_load_gpr_T0(ra);
4930
gen_op_load_gpr_T1(rb);
5194
4931
switch (opc3 & 0x0D) {
5195
4932
case 0x05:
5196
4933
/* macchw - macchw. - macchwo - macchwo. */
5198
4935
/* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5199
4936
/* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5200
4937
/* mulchw - mulchw. */
5201
tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5202
tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5203
tcg_gen_ext16s_tl(t1, t1);
4938
gen_op_405_mulchw();
5204
4939
break;
5205
4940
case 0x04:
5206
4941
/* macchwu - macchwu. - macchwuo - macchwuo. */
5207
4942
/* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5208
4943
/* mulchwu - mulchwu. */
5209
tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5210
tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5211
tcg_gen_ext16u_tl(t1, t1);
4944
gen_op_405_mulchwu();
5212
4945
break;
5213
4946
case 0x01:
5214
4947
/* machhw - machhw. - machhwo - machhwo. */
5216
4949
/* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5217
4950
/* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5218
4951
/* mulhhw - mulhhw. */
5219
tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5220
tcg_gen_ext16s_tl(t0, t0);
5221
tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5222
tcg_gen_ext16s_tl(t1, t1);
4952
gen_op_405_mulhhw();
5223
4953
break;
5224
4954
case 0x00:
5225
4955
/* machhwu - machhwu. - machhwuo - machhwuo. */
5226
4956
/* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5227
4957
/* mulhhwu - mulhhwu. */
5228
tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5229
tcg_gen_ext16u_tl(t0, t0);
5230
tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5231
tcg_gen_ext16u_tl(t1, t1);
4958
gen_op_405_mulhhwu();
5232
4959
break;
5233
4960
case 0x0D:
5234
4961
/* maclhw - maclhw. - maclhwo - maclhwo. */
5236
4963
/* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5237
4964
/* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5238
4965
/* mullhw - mullhw. */
5239
tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5240
tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
4966
gen_op_405_mullhw();
5241
4967
break;
5242
4968
case 0x0C:
5243
4969
/* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5244
4970
/* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5245
4971
/* mullhwu - mullhwu. */
5246
tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5247
tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
4972
gen_op_405_mullhwu();
5248
4973
break;
5249
4974
}
4975
if (opc2 & 0x02) {
4976
/* nmultiply-and-accumulate (0x0E) */
4977
gen_op_neg();
4978
}
5250
4979
if (opc2 & 0x04) {
5251
/* (n)multiply-and-accumulate (0x0C / 0x0E) */
5252
tcg_gen_mul_tl(t1, t0, t1);
5253
if (opc2 & 0x02) {
5254
/* nmultiply-and-accumulate (0x0E) */
5255
tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5256
} else {
5257
/* multiply-and-accumulate (0x0C) */
5258
tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5259
}
5260
5261
if (opc3 & 0x12) {
5262
/* Check overflow and/or saturate */
5263
int l1 = gen_new_label();
5264
5265
if (opc3 & 0x10) {
5266
/* Start with XER OV disabled, the most likely case */
5267
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5268
}
5269
if (opc3 & 0x01) {
5270
/* Signed */
5271
tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5272
tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5273
tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5274
tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5275
if (opc3 & 0x02) {
5276
/* Saturate */
5277
tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5278
tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5279
}
5280
} else {
5281
/* Unsigned */
5282
tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5283
if (opc3 & 0x02) {
5284
/* Saturate */
5285
tcg_gen_movi_tl(t0, UINT32_MAX);
5286
}
5287
}
5288
if (opc3 & 0x10) {
5289
/* Check overflow */
5290
tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5291
}
5292
gen_set_label(l1);
5293
tcg_gen_mov_tl(cpu_gpr[rt], t0);
5294
}
5295
} else {
5296
tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5297
}
5298
tcg_temp_free(t0);
5299
tcg_temp_free(t1);
4980
/* (n)multiply-and-accumulate (0x0C - 0x0E) */
4981
gen_op_load_gpr_T2(rt);
4982
gen_op_move_T1_T0();
4983
gen_op_405_add_T0_T2();
4984
}
4985
if (opc3 & 0x10) {
4986
/* Check overflow */
4987
if (opc3 & 0x01)
4988
gen_op_405_check_ov();
4989
else
4990
gen_op_405_check_ovu();
4991
}
4992
if (opc3 & 0x02) {
4993
/* Saturate */
4994
if (opc3 & 0x01)
4995
gen_op_405_check_sat();
4996
else
4997
gen_op_405_check_satu();
4998
}
4999
gen_op_store_T0_gpr(rt);
5300
5000
if (unlikely(Rc) != 0) {
5301
5001
/* Update Rc0 */
5302
gen_set_Rc0(ctx, cpu_gpr[rt]);
5002
gen_set_Rc0(ctx);
5303
5003
}
5304
5004
}
5305
5005
5397
5097
GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5398
5098
5399
5099
/* mfdcr */
5400
GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
5100
GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON)
5401
5101
{
5402
5102
#if defined(CONFIG_USER_ONLY)
5403
5103
GEN_EXCP_PRIVREG(ctx);
5408
5108
GEN_EXCP_PRIVREG(ctx);
5409
5109
return;
5410
5110
}
5411
tcg_gen_movi_tl(cpu_T[0], dcrn);
5111
gen_op_set_T0(dcrn);
5412
5112
gen_op_load_dcr();
5413
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5113
gen_op_store_T0_gpr(rD(ctx->opcode));
5414
5114
#endif
5415
5115
}
5416
5116
5417
5117
/* mtdcr */
5418
GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
5118
GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON)
5419
5119
{
5420
5120
#if defined(CONFIG_USER_ONLY)
5421
5121
GEN_EXCP_PRIVREG(ctx);
5426
5126
GEN_EXCP_PRIVREG(ctx);
5427
5127
return;
5428
5128
}
5429
tcg_gen_movi_tl(cpu_T[0], dcrn);
5430
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5129
gen_op_set_T0(dcrn);
5130
gen_op_load_gpr_T1(rS(ctx->opcode));
5431
5131
gen_op_store_dcr();
5432
5132
#endif
5433
5133
}
5434
5134
5435
5135
/* mfdcrx */
5436
5136
/* XXX: not implemented on 440 ? */
5437
GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
5137
GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT)
5438
5138
{
5439
5139
#if defined(CONFIG_USER_ONLY)
5440
5140
GEN_EXCP_PRIVREG(ctx);
5443
5143
GEN_EXCP_PRIVREG(ctx);
5444
5144
return;
5445
5145
}
5446
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5146
gen_op_load_gpr_T0(rA(ctx->opcode));
5447
5147
gen_op_load_dcr();
5448
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5148
gen_op_store_T0_gpr(rD(ctx->opcode));
5449
5149
/* Note: Rc update flag set leads to undefined state of Rc0 */
5450
5150
#endif
5451
5151
}
5452
5152
5453
5153
/* mtdcrx */
5454
5154
/* XXX: not implemented on 440 ? */
5455
GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
5155
GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT)
5456
5156
{
5457
5157
#if defined(CONFIG_USER_ONLY)
5458
5158
GEN_EXCP_PRIVREG(ctx);
5461
5161
GEN_EXCP_PRIVREG(ctx);
5462
5162
return;
5463
5163
}
5464
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5465
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5164
gen_op_load_gpr_T0(rA(ctx->opcode));
5165
gen_op_load_gpr_T1(rS(ctx->opcode));
5466
5166
gen_op_store_dcr();
5467
5167
/* Note: Rc update flag set leads to undefined state of Rc0 */
5468
5168
#endif
5471
5171
/* mfdcrux (PPC 460) : user-mode access to DCR */
5472
5172
GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5473
5173
{
5474
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5174
gen_op_load_gpr_T0(rA(ctx->opcode));
5475
5175
gen_op_load_dcr();
5476
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5176
gen_op_store_T0_gpr(rD(ctx->opcode));
5477
5177
/* Note: Rc update flag set leads to undefined state of Rc0 */
5478
5178
}
5479
5179
5480
5180
/* mtdcrux (PPC 460) : user-mode access to DCR */
5481
5181
GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5482
5182
{
5483
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5484
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5183
gen_op_load_gpr_T0(rA(ctx->opcode));
5184
gen_op_load_gpr_T1(rS(ctx->opcode));
5485
5185
gen_op_store_dcr();
5486
5186
/* Note: Rc update flag set leads to undefined state of Rc0 */
5487
5187
}
5506
5206
#if defined(CONFIG_USER_ONLY)
5507
5207
GEN_EXCP_PRIVOPC(ctx);
5508
5208
#else
5509
TCGv EA, val;
5510
5209
if (unlikely(!ctx->supervisor)) {
5511
5210
GEN_EXCP_PRIVOPC(ctx);
5512
5211
return;
5513
5212
}
5514
EA = tcg_temp_new(TCG_TYPE_TL);
5515
gen_addr_reg_index(EA, ctx);
5516
val = tcg_temp_new(TCG_TYPE_TL);
5517
gen_qemu_ld32u(val, EA, ctx->mem_idx);
5518
tcg_temp_free(val);
5519
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5520
tcg_temp_free(EA);
5213
gen_addr_reg_index(ctx);
5214
op_ldst(lwz);
5215
gen_op_store_T0_gpr(rD(ctx->opcode));
5521
5216
#endif
5522
5217
}
5523
5218
5524
5219
/* icbt */
5525
GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5220
GEN_HANDLER(icbt_40x, 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
5526
5221
{
5527
5222
/* interpreted as no-op */
5528
5223
/* XXX: specification say this is treated as a load by the MMU
5559
5254
}
5560
5255
5561
5256
/* rfci (supervisor only) */
5562
GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5257
GEN_HANDLER(rfci_40x, 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
5563
5258
{
5564
5259
#if defined(CONFIG_USER_ONLY)
5565
5260
GEN_EXCP_PRIVOPC(ctx);
5591
5286
5592
5287
/* BookE specific */
5593
5288
/* XXX: not implemented on 440 ? */
5594
GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
5289
GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT)
5595
5290
{
5596
5291
#if defined(CONFIG_USER_ONLY)
5597
5292
GEN_EXCP_PRIVOPC(ctx);
5624
5319
5625
5320
/* TLB management - PowerPC 405 implementation */
5626
5321
/* tlbre */
5627
GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5322
GEN_HANDLER(tlbre_40x, 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
5628
5323
{
5629
5324
#if defined(CONFIG_USER_ONLY)
5630
5325
GEN_EXCP_PRIVOPC(ctx);
5635
5330
}
5636
5331
switch (rB(ctx->opcode)) {
5637
5332
case 0:
5638
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5333
gen_op_load_gpr_T0(rA(ctx->opcode));
5639
5334
gen_op_4xx_tlbre_hi();
5640
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5335
gen_op_store_T0_gpr(rD(ctx->opcode));
5641
5336
break;
5642
5337
case 1:
5643
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5338
gen_op_load_gpr_T0(rA(ctx->opcode));
5644
5339
gen_op_4xx_tlbre_lo();
5645
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5340
gen_op_store_T0_gpr(rD(ctx->opcode));
5646
5341
break;
5647
5342
default:
5648
5343
GEN_EXCP_INVAL(ctx);
5652
5347
}
5653
5348
5654
5349
/* tlbsx - tlbsx. */
5655
GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5350
GEN_HANDLER(tlbsx_40x, 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
5656
5351
{
5657
5352
#if defined(CONFIG_USER_ONLY)
5658
5353
GEN_EXCP_PRIVOPC(ctx);
5661
5356
GEN_EXCP_PRIVOPC(ctx);
5662
5357
return;
5663
5358
}
5664
gen_addr_reg_index(cpu_T[0], ctx);
5359
gen_addr_reg_index(ctx);
5665
5360
gen_op_4xx_tlbsx();
5666
5361
if (Rc(ctx->opcode))
5667
5362
gen_op_4xx_tlbsx_check();
5668
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5363
gen_op_store_T0_gpr(rD(ctx->opcode));
5669
5364
#endif
5670
5365
}
5671
5366
5672
5367
/* tlbwe */
5673
GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5368
GEN_HANDLER(tlbwe_40x, 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
5674
5369
{
5675
5370
#if defined(CONFIG_USER_ONLY)
5676
5371
GEN_EXCP_PRIVOPC(ctx);
5681
5376
}
5682
5377
switch (rB(ctx->opcode)) {
5683
5378
case 0:
5684
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5685
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5379
gen_op_load_gpr_T0(rA(ctx->opcode));
5380
gen_op_load_gpr_T1(rS(ctx->opcode));
5686
5381
gen_op_4xx_tlbwe_hi();
5687
5382
break;
5688
5383
case 1:
5689
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5690
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5384
gen_op_load_gpr_T0(rA(ctx->opcode));
5385
gen_op_load_gpr_T1(rS(ctx->opcode));
5691
5386
gen_op_4xx_tlbwe_lo();
5692
5387
break;
5693
5388
default:
5699
5394
5700
5395
/* TLB management - PowerPC 440 implementation */
5701
5396
/* tlbre */
5702
GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5397
GEN_HANDLER(tlbre_440, 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5703
5398
{
5704
5399
#if defined(CONFIG_USER_ONLY)
5705
5400
GEN_EXCP_PRIVOPC(ctx);
5712
5407
case 0:
5713
5408
case 1:
5714
5409
case 2:
5715
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5410
gen_op_load_gpr_T0(rA(ctx->opcode));
5716
5411
gen_op_440_tlbre(rB(ctx->opcode));
5717
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5412
gen_op_store_T0_gpr(rD(ctx->opcode));
5718
5413
break;
5719
5414
default:
5720
5415
GEN_EXCP_INVAL(ctx);
5724
5419
}
5725
5420
5726
5421
/* tlbsx - tlbsx. */
5727
GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5422
GEN_HANDLER(tlbsx_440, 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5728
5423
{
5729
5424
#if defined(CONFIG_USER_ONLY)
5730
5425
GEN_EXCP_PRIVOPC(ctx);
5733
5428
GEN_EXCP_PRIVOPC(ctx);
5734
5429
return;
5735
5430
}
5736
gen_addr_reg_index(cpu_T[0], ctx);
5431
gen_addr_reg_index(ctx);
5737
5432
gen_op_440_tlbsx();
5738
5433
if (Rc(ctx->opcode))
5739
5434
gen_op_4xx_tlbsx_check();
5740
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5435
gen_op_store_T0_gpr(rD(ctx->opcode));
5741
5436
#endif
5742
5437
}
5743
5438
5744
5439
/* tlbwe */
5745
GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5440
GEN_HANDLER(tlbwe_440, 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5746
5441
{
5747
5442
#if defined(CONFIG_USER_ONLY)
5748
5443
GEN_EXCP_PRIVOPC(ctx);
5755
5450
case 0:
5756
5451
case 1:
5757
5452
case 2:
5758
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5759
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
5453
gen_op_load_gpr_T0(rA(ctx->opcode));
5454
gen_op_load_gpr_T1(rS(ctx->opcode));
5760
5455
gen_op_440_tlbwe(rB(ctx->opcode));
5761
5456
break;
5762
5457
default:
5767
5462
}
5768
5463
5769
5464
/* wrtee */
5770
GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
5465
GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON)
5771
5466
{
5772
5467
#if defined(CONFIG_USER_ONLY)
5773
5468
GEN_EXCP_PRIVOPC(ctx);
5776
5471
GEN_EXCP_PRIVOPC(ctx);
5777
5472
return;
5778
5473
}
5779
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
5474
gen_op_load_gpr_T0(rD(ctx->opcode));
5780
5475
gen_op_wrte();
5781
5476
/* Stop translation to have a chance to raise an exception
5782
5477
* if we just set msr_ee to 1
5786
5481
}
5787
5482
5788
5483
/* wrteei */
5789
GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
5484
GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_EMB_COMMON)
5790
5485
{
5791
5486
#if defined(CONFIG_USER_ONLY)
5792
5487
GEN_EXCP_PRIVOPC(ctx);
5795
5490
GEN_EXCP_PRIVOPC(ctx);
5796
5491
return;
5797
5492
}
5798
tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
5493
gen_op_set_T0(ctx->opcode & 0x00010000);
5799
5494
gen_op_wrte();
5800
5495
/* Stop translation to have a chance to raise an exception
5801
5496
* if we just set msr_ee to 1
5808
5503
/* dlmzb */
5809
5504
GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5810
5505
{
5811
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5812
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
5506
gen_op_load_gpr_T0(rS(ctx->opcode));
5507
gen_op_load_gpr_T1(rB(ctx->opcode));
5813
5508
gen_op_440_dlmzb();
5814
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
5815
tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5816
tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
5509
gen_op_store_T0_gpr(rA(ctx->opcode));
5510
gen_op_store_xer_bc();
5817
5511
if (Rc(ctx->opcode)) {
5818
5512
gen_op_440_dlmzb_update_Rc();
5819
tcg_gen_andi_i32(cpu_crf[0], cpu_T[0], 0xf);
5513
gen_op_store_T0_crf(0);
5820
5514
}
5821
5515
}
5822
5516
5833
5527
}
5834
5528
5835
5529
/* icbt */
5836
GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
5530
GEN_HANDLER(icbt_440, 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
5837
5531
{
5838
5532
/* interpreted as no-op */
5839
5533
/* XXX: specification say this is treated as a load by the MMU
5843
5537
5844
5538
/*** Altivec vector extension ***/
5845
5539
/* Altivec registers moves */
5846
5847
static always_inline void gen_load_avr(int t, int reg) {
5848
tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
5849
tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
5850
}
5851
5852
static always_inline void gen_store_avr(int reg, int t) {
5853
tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
5854
tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
5855
}
5540
GEN32(gen_op_load_avr_A0, gen_op_load_avr_A0_avr);
5541
GEN32(gen_op_load_avr_A1, gen_op_load_avr_A1_avr);
5542
GEN32(gen_op_load_avr_A2, gen_op_load_avr_A2_avr);
5543
5544
GEN32(gen_op_store_A0_avr, gen_op_store_A0_avr_avr);
5545
GEN32(gen_op_store_A1_avr, gen_op_store_A1_avr_avr);
5546
#if 0 // unused
5547
GEN32(gen_op_store_A2_avr, gen_op_store_A2_avr_avr);
5548
#endif
5856
5549
5857
5550
#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5858
#define OP_VR_LD_TABLE(name) \
5859
static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5860
GEN_MEM_FUNCS(vr_l##name), \
5861
};
5862
#define OP_VR_ST_TABLE(name) \
5863
static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5864
GEN_MEM_FUNCS(vr_st##name), \
5865
};
5551
#if defined(CONFIG_USER_ONLY)
5552
#if defined(TARGET_PPC64)
5553
/* User-mode only - 64 bits mode */
5554
#define OP_VR_LD_TABLE(name) \
5555
static GenOpFunc *gen_op_vr_l##name[] = { \
5556
&gen_op_vr_l##name##_raw, \
5557
&gen_op_vr_l##name##_le_raw, \
5558
&gen_op_vr_l##name##_64_raw, \
5559
&gen_op_vr_l##name##_le_64_raw, \
5560
};
5561
#define OP_VR_ST_TABLE(name) \
5562
static GenOpFunc *gen_op_vr_st##name[] = { \
5563
&gen_op_vr_st##name##_raw, \
5564
&gen_op_vr_st##name##_le_raw, \
5565
&gen_op_vr_st##name##_64_raw, \
5566
&gen_op_vr_st##name##_le_64_raw, \
5567
};
5568
#else /* defined(TARGET_PPC64) */
5569
/* User-mode only - 32 bits mode */
5570
#define OP_VR_LD_TABLE(name) \
5571
static GenOpFunc *gen_op_vr_l##name[] = { \
5572
&gen_op_vr_l##name##_raw, \
5573
&gen_op_vr_l##name##_le_raw, \
5574
};
5575
#define OP_VR_ST_TABLE(name) \
5576
static GenOpFunc *gen_op_vr_st##name[] = { \
5577
&gen_op_vr_st##name##_raw, \
5578
&gen_op_vr_st##name##_le_raw, \
5579
};
5580
#endif /* defined(TARGET_PPC64) */
5581
#else /* defined(CONFIG_USER_ONLY) */
5582
#if defined(TARGET_PPC64H)
5583
/* Full system with hypervisor mode */
5584
#define OP_VR_LD_TABLE(name) \
5585
static GenOpFunc *gen_op_vr_l##name[] = { \
5586
&gen_op_vr_l##name##_user, \
5587
&gen_op_vr_l##name##_le_user, \
5588
&gen_op_vr_l##name##_64_user, \
5589
&gen_op_vr_l##name##_le_64_user, \
5590
&gen_op_vr_l##name##_kernel, \
5591
&gen_op_vr_l##name##_le_kernel, \
5592
&gen_op_vr_l##name##_64_kernel, \
5593
&gen_op_vr_l##name##_le_64_kernel, \
5594
&gen_op_vr_l##name##_hypv, \
5595
&gen_op_vr_l##name##_le_hypv, \
5596
&gen_op_vr_l##name##_64_hypv, \
5597
&gen_op_vr_l##name##_le_64_hypv, \
5598
};
5599
#define OP_VR_ST_TABLE(name) \
5600
static GenOpFunc *gen_op_vr_st##name[] = { \
5601
&gen_op_vr_st##name##_user, \
5602
&gen_op_vr_st##name##_le_user, \
5603
&gen_op_vr_st##name##_64_user, \
5604
&gen_op_vr_st##name##_le_64_user, \
5605
&gen_op_vr_st##name##_kernel, \
5606
&gen_op_vr_st##name##_le_kernel, \
5607
&gen_op_vr_st##name##_64_kernel, \
5608
&gen_op_vr_st##name##_le_64_kernel, \
5609
&gen_op_vr_st##name##_hypv, \
5610
&gen_op_vr_st##name##_le_hypv, \
5611
&gen_op_vr_st##name##_64_hypv, \
5612
&gen_op_vr_st##name##_le_64_hypv, \
5613
};
5614
#elif defined(TARGET_PPC64)
5615
/* Full system - 64 bits mode */
5616
#define OP_VR_LD_TABLE(name) \
5617
static GenOpFunc *gen_op_vr_l##name[] = { \
5618
&gen_op_vr_l##name##_user, \
5619
&gen_op_vr_l##name##_le_user, \
5620
&gen_op_vr_l##name##_64_user, \
5621
&gen_op_vr_l##name##_le_64_user, \
5622
&gen_op_vr_l##name##_kernel, \
5623
&gen_op_vr_l##name##_le_kernel, \
5624
&gen_op_vr_l##name##_64_kernel, \
5625
&gen_op_vr_l##name##_le_64_kernel, \
5626
};
5627
#define OP_VR_ST_TABLE(name) \
5628
static GenOpFunc *gen_op_vr_st##name[] = { \
5629
&gen_op_vr_st##name##_user, \
5630
&gen_op_vr_st##name##_le_user, \
5631
&gen_op_vr_st##name##_64_user, \
5632
&gen_op_vr_st##name##_le_64_user, \
5633
&gen_op_vr_st##name##_kernel, \
5634
&gen_op_vr_st##name##_le_kernel, \
5635
&gen_op_vr_st##name##_64_kernel, \
5636
&gen_op_vr_st##name##_le_64_kernel, \
5637
};
5638
#else /* defined(TARGET_PPC64) */
5639
/* Full system - 32 bits mode */
5640
#define OP_VR_LD_TABLE(name) \
5641
static GenOpFunc *gen_op_vr_l##name[] = { \
5642
&gen_op_vr_l##name##_user, \
5643
&gen_op_vr_l##name##_le_user, \
5644
&gen_op_vr_l##name##_kernel, \
5645
&gen_op_vr_l##name##_le_kernel, \
5646
};
5647
#define OP_VR_ST_TABLE(name) \
5648
static GenOpFunc *gen_op_vr_st##name[] = { \
5649
&gen_op_vr_st##name##_user, \
5650
&gen_op_vr_st##name##_le_user, \
5651
&gen_op_vr_st##name##_kernel, \
5652
&gen_op_vr_st##name##_le_kernel, \
5653
};
5654
#endif /* defined(TARGET_PPC64) */
5655
#endif /* defined(CONFIG_USER_ONLY) */
5866
5656
5867
5657
#define GEN_VR_LDX(name, opc2, opc3) \
5868
5658
GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5871
5661
GEN_EXCP_NO_VR(ctx); \
5872
5662
return; \
5873
5663
} \
5874
gen_addr_reg_index(cpu_T[0], ctx); \
5664
gen_addr_reg_index(ctx); \
5875
5665
op_vr_ldst(vr_l##name); \
5876
gen_store_avr(rD(ctx->opcode), 0); \
5666
gen_op_store_A0_avr(rD(ctx->opcode)); \
5877
5667
}
5878
5668
5879
5669
#define GEN_VR_STX(name, opc2, opc3) \
5883
5673
GEN_EXCP_NO_VR(ctx); \
5884
5674
return; \
5885
5675
} \
5886
gen_addr_reg_index(cpu_T[0], ctx); \
5887
gen_load_avr(0, rS(ctx->opcode)); \
5676
gen_addr_reg_index(ctx); \
5677
gen_op_load_avr_A0(rS(ctx->opcode)); \
5888
5678
op_vr_ldst(vr_st##name); \
5889
5679
}
5890
5680
5900
5690
#define gen_op_vr_stvxl gen_op_vr_stvx
5901
5691
GEN_VR_STX(vxl, 0x07, 0x0F);
5902
5692
5693
#if defined(TARGET_PPCEMB)
5903
5694
/*** SPE extension ***/
5695
5904
5696
/* Register moves */
5905
5906
static always_inline void gen_load_gpr64(TCGv t, int reg) {
5907
#if defined(TARGET_PPC64)
5908
tcg_gen_mov_i64(t, cpu_gpr[reg]);
5909
#else
5910
tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
5911
#endif
5912
}
5913
5914
static always_inline void gen_store_gpr64(int reg, TCGv t) {
5915
#if defined(TARGET_PPC64)
5916
tcg_gen_mov_i64(cpu_gpr[reg], t);
5917
#else
5918
tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
5919
TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
5920
tcg_gen_shri_i64(tmp, t, 32);
5921
tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
5922
tcg_temp_free(tmp);
5923
#endif
5924
}
5697
GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
5698
GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
5699
#if 0 // unused
5700
GEN32(gen_op_load_gpr64_T2, gen_op_load_gpr64_T2_gpr);
5701
#endif
5702
5703
GEN32(gen_op_store_T0_gpr64, gen_op_store_T0_gpr64_gpr);
5704
GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
5705
#if 0 // unused
5706
GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
5707
#endif
5925
5708
5926
5709
#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5927
5710
GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5939
5722
}
5940
5723
5941
5724
/* SPE load and stores */
5942
static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
5725
static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
5943
5726
{
5944
5727
target_long simm = rB(ctx->opcode);
5945
5728
5946
if (rA(ctx->opcode) == 0)
5947
tcg_gen_movi_tl(EA, simm << sh);
5948
else if (likely(simm != 0))
5949
tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh);
5950
else
5951
tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
5729
if (rA(ctx->opcode) == 0) {
5730
gen_set_T0(simm << sh);
5731
} else {
5732
gen_op_load_gpr_T0(rA(ctx->opcode));
5733
if (likely(simm != 0))
5734
gen_op_addi(simm << sh);
5735
}
5952
5736
}
5953
5737
5954
5738
#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5955
#define OP_SPE_LD_TABLE(name) \
5956
static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5957
GEN_MEM_FUNCS(spe_l##name), \
5958
};
5959
#define OP_SPE_ST_TABLE(name) \
5960
static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5961
GEN_MEM_FUNCS(spe_st##name), \
5962
};
5739
#if defined(CONFIG_USER_ONLY)
5740
#if defined(TARGET_PPC64)
5741
/* User-mode only - 64 bits mode */
5742
#define OP_SPE_LD_TABLE(name) \
5743
static GenOpFunc *gen_op_spe_l##name[] = { \
5744
&gen_op_spe_l##name##_raw, \
5745
&gen_op_spe_l##name##_le_raw, \
5746
&gen_op_spe_l##name##_64_raw, \
5747
&gen_op_spe_l##name##_le_64_raw, \
5748
};
5749
#define OP_SPE_ST_TABLE(name) \
5750
static GenOpFunc *gen_op_spe_st##name[] = { \
5751
&gen_op_spe_st##name##_raw, \
5752
&gen_op_spe_st##name##_le_raw, \
5753
&gen_op_spe_st##name##_64_raw, \
5754
&gen_op_spe_st##name##_le_64_raw, \
5755
};
5756
#else /* defined(TARGET_PPC64) */
5757
/* User-mode only - 32 bits mode */
5758
#define OP_SPE_LD_TABLE(name) \
5759
static GenOpFunc *gen_op_spe_l##name[] = { \
5760
&gen_op_spe_l##name##_raw, \
5761
&gen_op_spe_l##name##_le_raw, \
5762
};
5763
#define OP_SPE_ST_TABLE(name) \
5764
static GenOpFunc *gen_op_spe_st##name[] = { \
5765
&gen_op_spe_st##name##_raw, \
5766
&gen_op_spe_st##name##_le_raw, \
5767
};
5768
#endif /* defined(TARGET_PPC64) */
5769
#else /* defined(CONFIG_USER_ONLY) */
5770
#if defined(TARGET_PPC64H)
5771
/* Full system with hypervisor mode */
5772
#define OP_SPE_LD_TABLE(name) \
5773
static GenOpFunc *gen_op_spe_l##name[] = { \
5774
&gen_op_spe_l##name##_user, \
5775
&gen_op_spe_l##name##_le_user, \
5776
&gen_op_spe_l##name##_64_user, \
5777
&gen_op_spe_l##name##_le_64_user, \
5778
&gen_op_spe_l##name##_kernel, \
5779
&gen_op_spe_l##name##_le_kernel, \
5780
&gen_op_spe_l##name##_64_kernel, \
5781
&gen_op_spe_l##name##_le_64_kernel, \
5782
&gen_op_spe_l##name##_hypv, \
5783
&gen_op_spe_l##name##_le_hypv, \
5784
&gen_op_spe_l##name##_64_hypv, \
5785
&gen_op_spe_l##name##_le_64_hypv, \
5786
};
5787
#define OP_SPE_ST_TABLE(name) \
5788
static GenOpFunc *gen_op_spe_st##name[] = { \
5789
&gen_op_spe_st##name##_user, \
5790
&gen_op_spe_st##name##_le_user, \
5791
&gen_op_spe_st##name##_64_user, \
5792
&gen_op_spe_st##name##_le_64_user, \
5793
&gen_op_spe_st##name##_kernel, \
5794
&gen_op_spe_st##name##_le_kernel, \
5795
&gen_op_spe_st##name##_64_kernel, \
5796
&gen_op_spe_st##name##_le_64_kernel, \
5797
&gen_op_spe_st##name##_hypv, \
5798
&gen_op_spe_st##name##_le_hypv, \
5799
&gen_op_spe_st##name##_64_hypv, \
5800
&gen_op_spe_st##name##_le_64_hypv, \
5801
};
5802
#elif defined(TARGET_PPC64)
5803
/* Full system - 64 bits mode */
5804
#define OP_SPE_LD_TABLE(name) \
5805
static GenOpFunc *gen_op_spe_l##name[] = { \
5806
&gen_op_spe_l##name##_user, \
5807
&gen_op_spe_l##name##_le_user, \
5808
&gen_op_spe_l##name##_64_user, \
5809
&gen_op_spe_l##name##_le_64_user, \
5810
&gen_op_spe_l##name##_kernel, \
5811
&gen_op_spe_l##name##_le_kernel, \
5812
&gen_op_spe_l##name##_64_kernel, \
5813
&gen_op_spe_l##name##_le_64_kernel, \
5814
};
5815
#define OP_SPE_ST_TABLE(name) \
5816
static GenOpFunc *gen_op_spe_st##name[] = { \
5817
&gen_op_spe_st##name##_user, \
5818
&gen_op_spe_st##name##_le_user, \
5819
&gen_op_spe_st##name##_64_user, \
5820
&gen_op_spe_st##name##_le_64_user, \
5821
&gen_op_spe_st##name##_kernel, \
5822
&gen_op_spe_st##name##_le_kernel, \
5823
&gen_op_spe_st##name##_64_kernel, \
5824
&gen_op_spe_st##name##_le_64_kernel, \
5825
};
5826
#else /* defined(TARGET_PPC64) */
5827
/* Full system - 32 bits mode */
5828
#define OP_SPE_LD_TABLE(name) \
5829
static GenOpFunc *gen_op_spe_l##name[] = { \
5830
&gen_op_spe_l##name##_user, \
5831
&gen_op_spe_l##name##_le_user, \
5832
&gen_op_spe_l##name##_kernel, \
5833
&gen_op_spe_l##name##_le_kernel, \
5834
};
5835
#define OP_SPE_ST_TABLE(name) \
5836
static GenOpFunc *gen_op_spe_st##name[] = { \
5837
&gen_op_spe_st##name##_user, \
5838
&gen_op_spe_st##name##_le_user, \
5839
&gen_op_spe_st##name##_kernel, \
5840
&gen_op_spe_st##name##_le_kernel, \
5841
};
5842
#endif /* defined(TARGET_PPC64) */
5843
#endif /* defined(CONFIG_USER_ONLY) */
5963
5844
5964
5845
#define GEN_SPE_LD(name, sh) \
5965
5846
static always_inline void gen_evl##name (DisasContext *ctx) \
5968
5849
GEN_EXCP_NO_AP(ctx); \
5969
5850
return; \
5970
5851
} \
5971
gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
5852
gen_addr_spe_imm_index(ctx, sh); \
5972
5853
op_spe_ldst(spe_l##name); \
5973
gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
5854
gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5974
5855
}
5975
5856
5976
5857
#define GEN_SPE_LDX(name) \
5980
5861
GEN_EXCP_NO_AP(ctx); \
5981
5862
return; \
5982
5863
} \
5983
gen_addr_reg_index(cpu_T[0], ctx); \
5864
gen_addr_reg_index(ctx); \
5984
5865
op_spe_ldst(spe_l##name); \
5985
gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
5866
gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5986
5867
}
5987
5868
5988
5869
#define GEN_SPEOP_LD(name, sh) \
5997
5878
GEN_EXCP_NO_AP(ctx); \
5998
5879
return; \
5999
5880
} \
6000
gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
6001
gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
5881
gen_addr_spe_imm_index(ctx, sh); \
5882
gen_op_load_gpr64_T1(rS(ctx->opcode)); \
6002
5883
op_spe_ldst(spe_st##name); \
6003
5884
}
6004
5885
6009
5890
GEN_EXCP_NO_AP(ctx); \
6010
5891
return; \
6011
5892
} \
6012
gen_addr_reg_index(cpu_T[0], ctx); \
6013
gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
5893
gen_addr_reg_index(ctx); \
5894
gen_op_load_gpr64_T1(rS(ctx->opcode)); \
6014
5895
op_spe_ldst(spe_st##name); \
6015
5896
}
6016
5897
6023
5904
GEN_SPEOP_LD(name, sh); \
6024
5905
GEN_SPEOP_ST(name, sh)
6025
5906
6026
/* SPE logic */
6027
#if defined(TARGET_PPC64)
6028
#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6029
static always_inline void gen_##name (DisasContext *ctx) \
6030
{ \
6031
if (unlikely(!ctx->spe_enabled)) { \
6032
GEN_EXCP_NO_AP(ctx); \
6033
return; \
6034
} \
6035
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6036
cpu_gpr[rB(ctx->opcode)]); \
6037
}
6038
#else
6039
#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6040
static always_inline void gen_##name (DisasContext *ctx) \
6041
{ \
6042
if (unlikely(!ctx->spe_enabled)) { \
6043
GEN_EXCP_NO_AP(ctx); \
6044
return; \
6045
} \
6046
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6047
cpu_gpr[rB(ctx->opcode)]); \
6048
tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6049
cpu_gprh[rB(ctx->opcode)]); \
6050
}
6051
#endif
6052
6053
GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6054
GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6055
GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6056
GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6057
GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6058
GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6059
GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6060
GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6061
6062
/* SPE logic immediate */
6063
#if defined(TARGET_PPC64)
6064
#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6065
static always_inline void gen_##name (DisasContext *ctx) \
6066
{ \
6067
if (unlikely(!ctx->spe_enabled)) { \
6068
GEN_EXCP_NO_AP(ctx); \
6069
return; \
6070
} \
6071
TCGv t0 = tcg_temp_local_new(TCG_TYPE_I32); \
6072
TCGv t1 = tcg_temp_local_new(TCG_TYPE_I32); \
6073
TCGv t2 = tcg_temp_local_new(TCG_TYPE_I64); \
6074
tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6075
tcg_opi(t0, t0, rB(ctx->opcode)); \
6076
tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6077
tcg_gen_trunc_i64_i32(t1, t2); \
6078
tcg_temp_free(t2); \
6079
tcg_opi(t1, t1, rB(ctx->opcode)); \
6080
tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6081
tcg_temp_free(t0); \
6082
tcg_temp_free(t1); \
6083
}
6084
#else
6085
#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6086
static always_inline void gen_##name (DisasContext *ctx) \
6087
{ \
6088
if (unlikely(!ctx->spe_enabled)) { \
6089
GEN_EXCP_NO_AP(ctx); \
6090
return; \
6091
} \
6092
tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6093
rB(ctx->opcode)); \
6094
tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6095
rB(ctx->opcode)); \
6096
}
6097
#endif
6098
GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6099
GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6100
GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6101
GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6102
6103
/* SPE arithmetic */
6104
#if defined(TARGET_PPC64)
6105
#define GEN_SPEOP_ARITH1(name, tcg_op) \
6106
static always_inline void gen_##name (DisasContext *ctx) \
6107
{ \
6108
if (unlikely(!ctx->spe_enabled)) { \
6109
GEN_EXCP_NO_AP(ctx); \
6110
return; \
6111
} \
6112
TCGv t0 = tcg_temp_local_new(TCG_TYPE_I32); \
6113
TCGv t1 = tcg_temp_local_new(TCG_TYPE_I32); \
6114
TCGv t2 = tcg_temp_local_new(TCG_TYPE_I64); \
6115
tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6116
tcg_op(t0, t0); \
6117
tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6118
tcg_gen_trunc_i64_i32(t1, t2); \
6119
tcg_temp_free(t2); \
6120
tcg_op(t1, t1); \
6121
tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6122
tcg_temp_free(t0); \
6123
tcg_temp_free(t1); \
6124
}
6125
#else
6126
#define GEN_SPEOP_ARITH1(name, tcg_op) \
6127
static always_inline void gen_##name (DisasContext *ctx) \
6128
{ \
6129
if (unlikely(!ctx->spe_enabled)) { \
6130
GEN_EXCP_NO_AP(ctx); \
6131
return; \
6132
} \
6133
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6134
tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6135
}
6136
#endif
6137
6138
static always_inline void gen_op_evabs (TCGv ret, TCGv arg1)
6139
{
6140
int l1 = gen_new_label();
6141
int l2 = gen_new_label();
6142
6143
tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6144
tcg_gen_neg_i32(ret, arg1);
6145
tcg_gen_br(l2);
6146
gen_set_label(l1);
6147
tcg_gen_mov_tl(ret, arg1);
6148
gen_set_label(l2);
6149
}
6150
GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6151
GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6152
GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6153
GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6154
static always_inline void gen_op_evrndw (TCGv ret, TCGv arg1)
6155
{
6156
tcg_gen_addi_i32(ret, arg1, 0x8000);
6157
tcg_gen_ext16u_i32(ret, ret);
6158
}
6159
GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6160
static always_inline void gen_op_cntlsw (TCGv ret, TCGv arg1)
6161
{
6162
tcg_gen_helper_1_1(helper_cntlsw32, ret, arg1);
6163
}
6164
GEN_SPEOP_ARITH1(evcntlsw, gen_op_cntlsw);
6165
static always_inline void gen_op_cntlzw (TCGv ret, TCGv arg1)
6166
{
6167
tcg_gen_helper_1_1(helper_cntlzw32, ret, arg1);
6168
}
6169
GEN_SPEOP_ARITH1(evcntlzw, gen_op_cntlzw);
6170
6171
#if defined(TARGET_PPC64)
6172
#define GEN_SPEOP_ARITH2(name, tcg_op) \
6173
static always_inline void gen_##name (DisasContext *ctx) \
6174
{ \
6175
if (unlikely(!ctx->spe_enabled)) { \
6176
GEN_EXCP_NO_AP(ctx); \
6177
return; \
6178
} \
6179
TCGv t0 = tcg_temp_local_new(TCG_TYPE_I32); \
6180
TCGv t1 = tcg_temp_local_new(TCG_TYPE_I32); \
6181
TCGv t2 = tcg_temp_local_new(TCG_TYPE_I32); \
6182
TCGv t3 = tcg_temp_local_new(TCG_TYPE_I64); \
6183
tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6184
tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6185
tcg_op(t0, t0, t2); \
6186
tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6187
tcg_gen_trunc_i64_i32(t1, t3); \
6188
tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6189
tcg_gen_trunc_i64_i32(t2, t3); \
6190
tcg_temp_free(t3); \
6191
tcg_op(t1, t1, t2); \
6192
tcg_temp_free(t2); \
6193
tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6194
tcg_temp_free(t0); \
6195
tcg_temp_free(t1); \
6196
}
6197
#else
6198
#define GEN_SPEOP_ARITH2(name, tcg_op) \
6199
static always_inline void gen_##name (DisasContext *ctx) \
6200
{ \
6201
if (unlikely(!ctx->spe_enabled)) { \
6202
GEN_EXCP_NO_AP(ctx); \
6203
return; \
6204
} \
6205
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6206
cpu_gpr[rB(ctx->opcode)]); \
6207
tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6208
cpu_gprh[rB(ctx->opcode)]); \
6209
}
6210
#endif
6211
6212
static always_inline void gen_op_evsrwu (TCGv ret, TCGv arg1, TCGv arg2)
6213
{
6214
TCGv t0;
6215
int l1, l2;
6216
6217
l1 = gen_new_label();
6218
l2 = gen_new_label();
6219
t0 = tcg_temp_local_new(TCG_TYPE_I32);
6220
/* No error here: 6 bits are used */
6221
tcg_gen_andi_i32(t0, arg2, 0x3F);
6222
tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6223
tcg_gen_shr_i32(ret, arg1, t0);
6224
tcg_gen_br(l2);
6225
gen_set_label(l1);
6226
tcg_gen_movi_i32(ret, 0);
6227
tcg_gen_br(l2);
6228
tcg_temp_free(t0);
6229
}
6230
GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
6231
static always_inline void gen_op_evsrws (TCGv ret, TCGv arg1, TCGv arg2)
6232
{
6233
TCGv t0;
6234
int l1, l2;
6235
6236
l1 = gen_new_label();
6237
l2 = gen_new_label();
6238
t0 = tcg_temp_local_new(TCG_TYPE_I32);
6239
/* No error here: 6 bits are used */
6240
tcg_gen_andi_i32(t0, arg2, 0x3F);
6241
tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6242
tcg_gen_sar_i32(ret, arg1, t0);
6243
tcg_gen_br(l2);
6244
gen_set_label(l1);
6245
tcg_gen_movi_i32(ret, 0);
6246
tcg_gen_br(l2);
6247
tcg_temp_free(t0);
6248
}
6249
GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
6250
static always_inline void gen_op_evslw (TCGv ret, TCGv arg1, TCGv arg2)
6251
{
6252
TCGv t0;
6253
int l1, l2;
6254
6255
l1 = gen_new_label();
6256
l2 = gen_new_label();
6257
t0 = tcg_temp_local_new(TCG_TYPE_I32);
6258
/* No error here: 6 bits are used */
6259
tcg_gen_andi_i32(t0, arg2, 0x3F);
6260
tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6261
tcg_gen_shl_i32(ret, arg1, t0);
6262
tcg_gen_br(l2);
6263
gen_set_label(l1);
6264
tcg_gen_movi_i32(ret, 0);
6265
tcg_gen_br(l2);
6266
tcg_temp_free(t0);
6267
}
6268
GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
6269
static always_inline void gen_op_evrlw (TCGv ret, TCGv arg1, TCGv arg2)
6270
{
6271
TCGv t0 = tcg_temp_new(TCG_TYPE_I32);
6272
tcg_gen_andi_i32(t0, arg2, 0x1F);
6273
tcg_gen_rotl_i32(ret, arg1, t0);
6274
tcg_temp_free(t0);
6275
}
6276
GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6277
static always_inline void gen_evmergehi (DisasContext *ctx)
6278
{
6279
if (unlikely(!ctx->spe_enabled)) {
6280
GEN_EXCP_NO_AP(ctx);
6281
return;
6282
}
6283
#if defined(TARGET_PPC64)
6284
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
6285
TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
6286
tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6287
tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6288
tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6289
tcg_temp_free(t0);
6290
tcg_temp_free(t1);
6291
#else
6292
tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6293
tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6294
#endif
6295
}
6296
GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
6297
static always_inline void gen_op_evsubf (TCGv ret, TCGv arg1, TCGv arg2)
6298
{
6299
tcg_gen_sub_i32(ret, arg2, arg1);
6300
}
6301
GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
6302
6303
/* SPE arithmetic immediate */
6304
#if defined(TARGET_PPC64)
6305
#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6306
static always_inline void gen_##name (DisasContext *ctx) \
6307
{ \
6308
if (unlikely(!ctx->spe_enabled)) { \
6309
GEN_EXCP_NO_AP(ctx); \
6310
return; \
6311
} \
6312
TCGv t0 = tcg_temp_local_new(TCG_TYPE_I32); \
6313
TCGv t1 = tcg_temp_local_new(TCG_TYPE_I32); \
6314
TCGv t2 = tcg_temp_local_new(TCG_TYPE_I64); \
6315
tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6316
tcg_op(t0, t0, rA(ctx->opcode)); \
6317
tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6318
tcg_gen_trunc_i64_i32(t1, t2); \
6319
tcg_temp_free(t2); \
6320
tcg_op(t1, t1, rA(ctx->opcode)); \
6321
tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6322
tcg_temp_free(t0); \
6323
tcg_temp_free(t1); \
6324
}
6325
#else
6326
#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6327
static always_inline void gen_##name (DisasContext *ctx) \
6328
{ \
6329
if (unlikely(!ctx->spe_enabled)) { \
6330
GEN_EXCP_NO_AP(ctx); \
6331
return; \
6332
} \
6333
tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
6334
rA(ctx->opcode)); \
6335
tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
6336
rA(ctx->opcode)); \
6337
}
6338
#endif
6339
GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
6340
GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
6341
6342
/* SPE comparison */
6343
#if defined(TARGET_PPC64)
6344
#define GEN_SPEOP_COMP(name, tcg_cond) \
6345
static always_inline void gen_##name (DisasContext *ctx) \
6346
{ \
6347
if (unlikely(!ctx->spe_enabled)) { \
6348
GEN_EXCP_NO_AP(ctx); \
6349
return; \
6350
} \
6351
int l1 = gen_new_label(); \
6352
int l2 = gen_new_label(); \
6353
int l3 = gen_new_label(); \
6354
int l4 = gen_new_label(); \
6355
TCGv t0 = tcg_temp_local_new(TCG_TYPE_I32); \
6356
TCGv t1 = tcg_temp_local_new(TCG_TYPE_I32); \
6357
TCGv t2 = tcg_temp_local_new(TCG_TYPE_I64); \
6358
tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6359
tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
6360
tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
6361
tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6362
tcg_gen_br(l2); \
6363
gen_set_label(l1); \
6364
tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6365
CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6366
gen_set_label(l2); \
6367
tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6368
tcg_gen_trunc_i64_i32(t0, t2); \
6369
tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6370
tcg_gen_trunc_i64_i32(t1, t2); \
6371
tcg_temp_free(t2); \
6372
tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
6373
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6374
~(CRF_CH | CRF_CH_AND_CL)); \
6375
tcg_gen_br(l4); \
6376
gen_set_label(l3); \
6377
tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6378
CRF_CH | CRF_CH_OR_CL); \
6379
gen_set_label(l4); \
6380
tcg_temp_free(t0); \
6381
tcg_temp_free(t1); \
6382
}
6383
#else
6384
#define GEN_SPEOP_COMP(name, tcg_cond) \
6385
static always_inline void gen_##name (DisasContext *ctx) \
6386
{ \
6387
if (unlikely(!ctx->spe_enabled)) { \
6388
GEN_EXCP_NO_AP(ctx); \
6389
return; \
6390
} \
6391
int l1 = gen_new_label(); \
6392
int l2 = gen_new_label(); \
6393
int l3 = gen_new_label(); \
6394
int l4 = gen_new_label(); \
6395
\
6396
tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
6397
cpu_gpr[rB(ctx->opcode)], l1); \
6398
tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
6399
tcg_gen_br(l2); \
6400
gen_set_label(l1); \
6401
tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
6402
CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
6403
gen_set_label(l2); \
6404
tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
6405
cpu_gprh[rB(ctx->opcode)], l3); \
6406
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6407
~(CRF_CH | CRF_CH_AND_CL)); \
6408
tcg_gen_br(l4); \
6409
gen_set_label(l3); \
6410
tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
6411
CRF_CH | CRF_CH_OR_CL); \
6412
gen_set_label(l4); \
6413
}
6414
#endif
6415
GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
6416
GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
6417
GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
6418
GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
6419
GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
6420
6421
/* SPE misc */
5907
/* SPE arithmetic and logic */
5908
#define GEN_SPEOP_ARITH2(name) \
5909
static always_inline void gen_##name (DisasContext *ctx) \
5910
{ \
5911
if (unlikely(!ctx->spe_enabled)) { \
5912
GEN_EXCP_NO_AP(ctx); \
5913
return; \
5914
} \
5915
gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5916
gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5917
gen_op_##name(); \
5918
gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5919
}
5920
5921
#define GEN_SPEOP_ARITH1(name) \
5922
static always_inline void gen_##name (DisasContext *ctx) \
5923
{ \
5924
if (unlikely(!ctx->spe_enabled)) { \
5925
GEN_EXCP_NO_AP(ctx); \
5926
return; \
5927
} \
5928
gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5929
gen_op_##name(); \
5930
gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5931
}
5932
5933
#define GEN_SPEOP_COMP(name) \
5934
static always_inline void gen_##name (DisasContext *ctx) \
5935
{ \
5936
if (unlikely(!ctx->spe_enabled)) { \
5937
GEN_EXCP_NO_AP(ctx); \
5938
return; \
5939
} \
5940
gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5941
gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5942
gen_op_##name(); \
5943
gen_op_store_T0_crf(crfD(ctx->opcode)); \
5944
}
5945
5946
/* Logical */
5947
GEN_SPEOP_ARITH2(evand);
5948
GEN_SPEOP_ARITH2(evandc);
5949
GEN_SPEOP_ARITH2(evxor);
5950
GEN_SPEOP_ARITH2(evor);
5951
GEN_SPEOP_ARITH2(evnor);
5952
GEN_SPEOP_ARITH2(eveqv);
5953
GEN_SPEOP_ARITH2(evorc);
5954
GEN_SPEOP_ARITH2(evnand);
5955
GEN_SPEOP_ARITH2(evsrwu);
5956
GEN_SPEOP_ARITH2(evsrws);
5957
GEN_SPEOP_ARITH2(evslw);
5958
GEN_SPEOP_ARITH2(evrlw);
5959
GEN_SPEOP_ARITH2(evmergehi);
5960
GEN_SPEOP_ARITH2(evmergelo);
5961
GEN_SPEOP_ARITH2(evmergehilo);
5962
GEN_SPEOP_ARITH2(evmergelohi);
5963
5964
/* Arithmetic */
5965
GEN_SPEOP_ARITH2(evaddw);
5966
GEN_SPEOP_ARITH2(evsubfw);
5967
GEN_SPEOP_ARITH1(evabs);
5968
GEN_SPEOP_ARITH1(evneg);
5969
GEN_SPEOP_ARITH1(evextsb);
5970
GEN_SPEOP_ARITH1(evextsh);
5971
GEN_SPEOP_ARITH1(evrndw);
5972
GEN_SPEOP_ARITH1(evcntlzw);
5973
GEN_SPEOP_ARITH1(evcntlsw);
6422
5974
static always_inline void gen_brinc (DisasContext *ctx)
6423
5975
{
6424
5976
/* Note: brinc is usable even if SPE is disabled */
6425
tcg_gen_helper_1_2(helper_brinc, cpu_gpr[rD(ctx->opcode)],
6426
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6427
}
6428
static always_inline void gen_evmergelo (DisasContext *ctx)
6429
{
6430
if (unlikely(!ctx->spe_enabled)) {
6431
GEN_EXCP_NO_AP(ctx);
6432
return;
6433
}
6434
#if defined(TARGET_PPC64)
6435
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
6436
TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
6437
tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6438
tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6439
tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6440
tcg_temp_free(t0);
6441
tcg_temp_free(t1);
6442
#else
6443
tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6444
tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6445
#endif
6446
}
6447
static always_inline void gen_evmergehilo (DisasContext *ctx)
6448
{
6449
if (unlikely(!ctx->spe_enabled)) {
6450
GEN_EXCP_NO_AP(ctx);
6451
return;
6452
}
6453
#if defined(TARGET_PPC64)
6454
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
6455
TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
6456
tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
6457
tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6458
tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6459
tcg_temp_free(t0);
6460
tcg_temp_free(t1);
6461
#else
6462
tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6463
tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6464
#endif
6465
}
6466
static always_inline void gen_evmergelohi (DisasContext *ctx)
6467
{
6468
if (unlikely(!ctx->spe_enabled)) {
6469
GEN_EXCP_NO_AP(ctx);
6470
return;
6471
}
6472
#if defined(TARGET_PPC64)
6473
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
6474
TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
6475
tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6476
tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
6477
tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6478
tcg_temp_free(t0);
6479
tcg_temp_free(t1);
6480
#else
6481
tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6482
tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6483
#endif
6484
}
5977
gen_op_load_gpr64_T0(rA(ctx->opcode));
5978
gen_op_load_gpr64_T1(rB(ctx->opcode));
5979
gen_op_brinc();
5980
gen_op_store_T0_gpr64(rD(ctx->opcode));
5981
}
5982
5983
#define GEN_SPEOP_ARITH_IMM2(name) \
5984
static always_inline void gen_##name##i (DisasContext *ctx) \
5985
{ \
5986
if (unlikely(!ctx->spe_enabled)) { \
5987
GEN_EXCP_NO_AP(ctx); \
5988
return; \
5989
} \
5990
gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5991
gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5992
gen_op_##name(); \
5993
gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5994
}
5995
5996
#define GEN_SPEOP_LOGIC_IMM2(name) \
5997
static always_inline void gen_##name##i (DisasContext *ctx) \
5998
{ \
5999
if (unlikely(!ctx->spe_enabled)) { \
6000
GEN_EXCP_NO_AP(ctx); \
6001
return; \
6002
} \
6003
gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6004
gen_op_splatwi_T1_64(rB(ctx->opcode)); \
6005
gen_op_##name(); \
6006
gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6007
}
6008
6009
GEN_SPEOP_ARITH_IMM2(evaddw);
6010
#define gen_evaddiw gen_evaddwi
6011
GEN_SPEOP_ARITH_IMM2(evsubfw);
6012
#define gen_evsubifw gen_evsubfwi
6013
GEN_SPEOP_LOGIC_IMM2(evslw);
6014
GEN_SPEOP_LOGIC_IMM2(evsrwu);
6015
#define gen_evsrwis gen_evsrwsi
6016
GEN_SPEOP_LOGIC_IMM2(evsrws);
6017
#define gen_evsrwiu gen_evsrwui
6018
GEN_SPEOP_LOGIC_IMM2(evrlw);
6019
6485
6020
static always_inline void gen_evsplati (DisasContext *ctx)
6486
6021
{
6487
int32_t imm = (int32_t)(rA(ctx->opcode) << 11) >> 27;
6022
int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
6488
6023
6489
#if defined(TARGET_PPC64)
6490
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
6491
TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
6492
tcg_gen_movi_tl(t0, imm);
6493
tcg_gen_shri_tl(t1, t0, 32);
6494
tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6495
tcg_temp_free(t0);
6496
tcg_temp_free(t1);
6497
#else
6498
tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6499
tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6500
#endif
6024
gen_op_splatwi_T0_64(imm);
6025
gen_op_store_T0_gpr64(rD(ctx->opcode));
6501
6026
}
6027
6502
6028
static always_inline void gen_evsplatfi (DisasContext *ctx)
6503
6029
{
6504
uint32_t imm = rA(ctx->opcode) << 11;
6505
6506
#if defined(TARGET_PPC64)
6507
TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
6508
TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
6509
tcg_gen_movi_tl(t0, imm);
6510
tcg_gen_shri_tl(t1, t0, 32);
6511
tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6512
tcg_temp_free(t0);
6513
tcg_temp_free(t1);
6514
#else
6515
tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
6516
tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
6517
#endif
6518
}
6519
6520
static always_inline void gen_evsel (DisasContext *ctx)
6521
{
6522
int l1 = gen_new_label();
6523
int l2 = gen_new_label();
6524
int l3 = gen_new_label();
6525
int l4 = gen_new_label();
6526
TCGv t0 = tcg_temp_local_new(TCG_TYPE_I32);
6527
#if defined(TARGET_PPC64)
6528
TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
6529
TCGv t2 = tcg_temp_local_new(TCG_TYPE_TL);
6530
#endif
6531
tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
6532
tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
6533
#if defined(TARGET_PPC64)
6534
tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6535
#else
6536
tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6537
#endif
6538
tcg_gen_br(l2);
6539
gen_set_label(l1);
6540
#if defined(TARGET_PPC64)
6541
tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
6542
#else
6543
tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6544
#endif
6545
gen_set_label(l2);
6546
tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
6547
tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
6548
#if defined(TARGET_PPC64)
6549
tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
6550
#else
6551
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6552
#endif
6553
tcg_gen_br(l4);
6554
gen_set_label(l3);
6555
#if defined(TARGET_PPC64)
6556
tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
6557
#else
6558
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6559
#endif
6560
gen_set_label(l4);
6561
tcg_temp_free(t0);
6562
#if defined(TARGET_PPC64)
6563
tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
6564
tcg_temp_free(t1);
6565
tcg_temp_free(t2);
6566
#endif
6567
}
6568
GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6569
{
6570
gen_evsel(ctx);
6571
}
6572
GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6573
{
6574
gen_evsel(ctx);
6575
}
6576
GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6577
{
6578
gen_evsel(ctx);
6579
}
6580
GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6581
{
6582
gen_evsel(ctx);
6583
}
6030
uint32_t imm = rA(ctx->opcode) << 27;
6031
6032
gen_op_splatwi_T0_64(imm);
6033
gen_op_store_T0_gpr64(rD(ctx->opcode));
6034
}
6035
6036
/* Comparison */
6037
GEN_SPEOP_COMP(evcmpgtu);
6038
GEN_SPEOP_COMP(evcmpgts);
6039
GEN_SPEOP_COMP(evcmpltu);
6040
GEN_SPEOP_COMP(evcmplts);
6041
GEN_SPEOP_COMP(evcmpeq);
6584
6042
6585
6043
GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6586
6044
GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6608
6066
GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6609
6067
GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6610
6068
6069
static always_inline void gen_evsel (DisasContext *ctx)
6070
{
6071
if (unlikely(!ctx->spe_enabled)) {
6072
GEN_EXCP_NO_AP(ctx);
6073
return;
6074
}
6075
gen_op_load_crf_T0(ctx->opcode & 0x7);
6076
gen_op_load_gpr64_T0(rA(ctx->opcode));
6077
gen_op_load_gpr64_T1(rB(ctx->opcode));
6078
gen_op_evsel();
6079
gen_op_store_T0_gpr64(rD(ctx->opcode));
6080
}
6081
6082
GEN_HANDLER(evsel0, 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
6083
{
6084
gen_evsel(ctx);
6085
}
6086
GEN_HANDLER(evsel1, 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
6087
{
6088
gen_evsel(ctx);
6089
}
6090
GEN_HANDLER(evsel2, 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
6091
{
6092
gen_evsel(ctx);
6093
}
6094
GEN_HANDLER(evsel3, 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
6095
{
6096
gen_evsel(ctx);
6097
}
6098
6611
6099
/* Load and stores */
6100
#if defined(TARGET_PPC64)
6101
/* In that case, we already have 64 bits load & stores
6102
* so, spe_ldd is equivalent to ld and spe_std is equivalent to std
6103
*/
6104
#if defined(CONFIG_USER_ONLY)
6105
#define gen_op_spe_ldd_raw gen_op_ld_raw
6106
#define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
6107
#define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
6108
#define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
6109
#define gen_op_spe_stdd_raw gen_op_ld_raw
6110
#define gen_op_spe_stdd_64_raw gen_op_std_64_raw
6111
#define gen_op_spe_stdd_le_raw gen_op_std_le_raw
6112
#define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
6113
#else /* defined(CONFIG_USER_ONLY) */
6114
#define gen_op_spe_ldd_kernel gen_op_ld_kernel
6115
#define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
6116
#define gen_op_spe_ldd_le_kernel gen_op_ld_kernel
6117
#define gen_op_spe_ldd_le_64_kernel gen_op_ld_64_kernel
6118
#define gen_op_spe_ldd_user gen_op_ld_user
6119
#define gen_op_spe_ldd_64_user gen_op_ld_64_user
6120
#define gen_op_spe_ldd_le_user gen_op_ld_le_user
6121
#define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
6122
#define gen_op_spe_stdd_kernel gen_op_std_kernel
6123
#define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
6124
#define gen_op_spe_stdd_le_kernel gen_op_std_kernel
6125
#define gen_op_spe_stdd_le_64_kernel gen_op_std_64_kernel
6126
#define gen_op_spe_stdd_user gen_op_std_user
6127
#define gen_op_spe_stdd_64_user gen_op_std_64_user
6128
#define gen_op_spe_stdd_le_user gen_op_std_le_user
6129
#define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
6130
#endif /* defined(CONFIG_USER_ONLY) */
6131
#endif /* defined(TARGET_PPC64) */
6612
6132
GEN_SPEOP_LDST(dd, 3);
6613
6133
GEN_SPEOP_LDST(dw, 3);
6614
6134
GEN_SPEOP_LDST(dh, 3);
6617
6137
GEN_SPEOP_LD(whos, 2);
6618
6138
GEN_SPEOP_ST(who, 2);
6619
6139
6140
#if defined(TARGET_PPC64)
6141
/* In that case, spe_stwwo is equivalent to stw */
6142
#if defined(CONFIG_USER_ONLY)
6143
#define gen_op_spe_stwwo_raw gen_op_stw_raw
6144
#define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
6145
#define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
6146
#define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
6147
#else
6148
#define gen_op_spe_stwwo_user gen_op_stw_user
6149
#define gen_op_spe_stwwo_le_user gen_op_stw_le_user
6150
#define gen_op_spe_stwwo_64_user gen_op_stw_64_user
6151
#define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
6152
#define gen_op_spe_stwwo_kernel gen_op_stw_kernel
6153
#define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
6154
#define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
6155
#define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
6156
#endif
6157
#endif
6620
6158
#define _GEN_OP_SPE_STWWE(suffix) \
6621
6159
static always_inline void gen_op_spe_stwwe_##suffix (void) \
6622
6160
{ \
6651
6189
#if defined(CONFIG_USER_ONLY)
6652
6190
GEN_OP_SPE_STWWE(raw);
6653
6191
#else /* defined(CONFIG_USER_ONLY) */
6192
GEN_OP_SPE_STWWE(kernel);
6654
6193
GEN_OP_SPE_STWWE(user);
6655
GEN_OP_SPE_STWWE(kernel);
6656
GEN_OP_SPE_STWWE(hypv);
6657
6194
#endif /* defined(CONFIG_USER_ONLY) */
6658
6195
GEN_SPEOP_ST(wwe, 2);
6659
6196
GEN_SPEOP_ST(wwo, 2);
6703
6240
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6704
6241
#endif
6705
6242
#else
6243
GEN_OP_SPE_LHE(kernel);
6706
6244
GEN_OP_SPE_LHE(user);
6707
GEN_OP_SPE_LHE(kernel);
6708
GEN_OP_SPE_LHE(hypv);
6245
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6709
6246
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
6710
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6711
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
6247
GEN_OP_SPE_LHE(le_kernel);
6712
6248
GEN_OP_SPE_LHE(le_user);
6713
GEN_OP_SPE_LHE(le_kernel);
6714
GEN_OP_SPE_LHE(le_hypv);
6249
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6715
6250
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
6716
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6717
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
6251
GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6718
6252
GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
6719
GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6720
GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
6253
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6721
6254
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
6722
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6723
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
6255
GEN_OP_SPE_LHX(kernel);
6724
6256
GEN_OP_SPE_LHX(user);
6725
GEN_OP_SPE_LHX(kernel);
6726
GEN_OP_SPE_LHX(hypv);
6257
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6727
6258
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
6728
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6729
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
6259
GEN_OP_SPE_LHX(le_kernel);
6730
6260
GEN_OP_SPE_LHX(le_user);
6731
GEN_OP_SPE_LHX(le_kernel);
6732
GEN_OP_SPE_LHX(le_hypv);
6261
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6733
6262
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
6734
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6735
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
6736
6263
#if defined(TARGET_PPC64)
6264
GEN_OP_SPE_LHE(64_kernel);
6737
6265
GEN_OP_SPE_LHE(64_user);
6738
GEN_OP_SPE_LHE(64_kernel);
6739
GEN_OP_SPE_LHE(64_hypv);
6266
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6740
6267
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
6741
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6742
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
6268
GEN_OP_SPE_LHE(le_64_kernel);
6743
6269
GEN_OP_SPE_LHE(le_64_user);
6744
GEN_OP_SPE_LHE(le_64_kernel);
6745
GEN_OP_SPE_LHE(le_64_hypv);
6270
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6746
6271
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
6747
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6748
GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
6272
GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6749
6273
GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
6750
GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6751
GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
6274
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6752
6275
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
6753
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6754
GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
6276
GEN_OP_SPE_LHX(64_kernel);
6755
6277
GEN_OP_SPE_LHX(64_user);
6756
GEN_OP_SPE_LHX(64_kernel);
6757
GEN_OP_SPE_LHX(64_hypv);
6278
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6758
6279
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
6759
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6760
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
6280
GEN_OP_SPE_LHX(le_64_kernel);
6761
6281
GEN_OP_SPE_LHX(le_64_user);
6762
GEN_OP_SPE_LHX(le_64_kernel);
6763
GEN_OP_SPE_LHX(le_64_hypv);
6282
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6764
6283
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
6765
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6766
GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
6767
6284
#endif
6768
6285
#endif
6769
6286
GEN_SPEOP_LD(hhesplat, 1);
6871
6388
#define GEN_SPEFPUOP_CONV(name) \
6872
6389
static always_inline void gen_##name (DisasContext *ctx) \
6873
6390
{ \
6874
gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
6875
gen_op_##name(); \
6876
gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
6877
}
6878
6879
#define GEN_SPEFPUOP_ARITH1(name) \
6880
static always_inline void gen_##name (DisasContext *ctx) \
6881
{ \
6882
if (unlikely(!ctx->spe_enabled)) { \
6883
GEN_EXCP_NO_AP(ctx); \
6884
return; \
6885
} \
6886
gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
6887
gen_op_##name(); \
6888
gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
6889
}
6890
6891
#define GEN_SPEFPUOP_ARITH2(name) \
6892
static always_inline void gen_##name (DisasContext *ctx) \
6893
{ \
6894
if (unlikely(!ctx->spe_enabled)) { \
6895
GEN_EXCP_NO_AP(ctx); \
6896
return; \
6897
} \
6898
gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
6899
gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
6900
gen_op_##name(); \
6901
gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
6902
}
6903
6904
#define GEN_SPEFPUOP_COMP(name) \
6905
static always_inline void gen_##name (DisasContext *ctx) \
6906
{ \
6907
if (unlikely(!ctx->spe_enabled)) { \
6908
GEN_EXCP_NO_AP(ctx); \
6909
return; \
6910
} \
6911
gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
6912
gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
6913
gen_op_##name(); \
6914
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
6391
gen_op_load_gpr64_T0(rB(ctx->opcode)); \
6392
gen_op_##name(); \
6393
gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6915
6394
}
6916
6395
6917
6396
/* Single precision floating-point vectors operations */
6918
6397
/* Arithmetic */
6919
GEN_SPEFPUOP_ARITH2(evfsadd);
6920
GEN_SPEFPUOP_ARITH2(evfssub);
6921
GEN_SPEFPUOP_ARITH2(evfsmul);
6922
GEN_SPEFPUOP_ARITH2(evfsdiv);
6923
GEN_SPEFPUOP_ARITH1(evfsabs);
6924
GEN_SPEFPUOP_ARITH1(evfsnabs);
6925
GEN_SPEFPUOP_ARITH1(evfsneg);
6398
GEN_SPEOP_ARITH2(evfsadd);
6399
GEN_SPEOP_ARITH2(evfssub);
6400
GEN_SPEOP_ARITH2(evfsmul);
6401
GEN_SPEOP_ARITH2(evfsdiv);
6402
GEN_SPEOP_ARITH1(evfsabs);
6403
GEN_SPEOP_ARITH1(evfsnabs);
6404
GEN_SPEOP_ARITH1(evfsneg);
6926
6405
/* Conversion */
6927
6406
GEN_SPEFPUOP_CONV(evfscfui);
6928
6407
GEN_SPEFPUOP_CONV(evfscfsi);
6935
6414
GEN_SPEFPUOP_CONV(evfsctuiz);
6936
6415
GEN_SPEFPUOP_CONV(evfsctsiz);
6937
6416
/* Comparison */
6938
GEN_SPEFPUOP_COMP(evfscmpgt);
6939
GEN_SPEFPUOP_COMP(evfscmplt);
6940
GEN_SPEFPUOP_COMP(evfscmpeq);
6941
GEN_SPEFPUOP_COMP(evfststgt);
6942
GEN_SPEFPUOP_COMP(evfststlt);
6943
GEN_SPEFPUOP_COMP(evfststeq);
6417
GEN_SPEOP_COMP(evfscmpgt);
6418
GEN_SPEOP_COMP(evfscmplt);
6419
GEN_SPEOP_COMP(evfscmpeq);
6420
GEN_SPEOP_COMP(evfststgt);
6421
GEN_SPEOP_COMP(evfststlt);
6422
GEN_SPEOP_COMP(evfststeq);
6944
6423
6945
6424
/* Opcodes definitions */
6946
6425
GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6960
6439
6961
6440
/* Single precision floating-point operations */
6962
6441
/* Arithmetic */
6963
GEN_SPEFPUOP_ARITH2(efsadd);
6964
GEN_SPEFPUOP_ARITH2(efssub);
6965
GEN_SPEFPUOP_ARITH2(efsmul);
6966
GEN_SPEFPUOP_ARITH2(efsdiv);
6967
GEN_SPEFPUOP_ARITH1(efsabs);
6968
GEN_SPEFPUOP_ARITH1(efsnabs);
6969
GEN_SPEFPUOP_ARITH1(efsneg);
6442
GEN_SPEOP_ARITH2(efsadd);
6443
GEN_SPEOP_ARITH2(efssub);
6444
GEN_SPEOP_ARITH2(efsmul);
6445
GEN_SPEOP_ARITH2(efsdiv);
6446
GEN_SPEOP_ARITH1(efsabs);
6447
GEN_SPEOP_ARITH1(efsnabs);
6448
GEN_SPEOP_ARITH1(efsneg);
6970
6449
/* Conversion */
6971
6450
GEN_SPEFPUOP_CONV(efscfui);
6972
6451
GEN_SPEFPUOP_CONV(efscfsi);
6980
6459
GEN_SPEFPUOP_CONV(efsctsiz);
6981
6460
GEN_SPEFPUOP_CONV(efscfd);
6982
6461
/* Comparison */
6983
GEN_SPEFPUOP_COMP(efscmpgt);
6984
GEN_SPEFPUOP_COMP(efscmplt);
6985
GEN_SPEFPUOP_COMP(efscmpeq);
6986
GEN_SPEFPUOP_COMP(efststgt);
6987
GEN_SPEFPUOP_COMP(efststlt);
6988
GEN_SPEFPUOP_COMP(efststeq);
6462
GEN_SPEOP_COMP(efscmpgt);
6463
GEN_SPEOP_COMP(efscmplt);
6464
GEN_SPEOP_COMP(efscmpeq);
6465
GEN_SPEOP_COMP(efststgt);
6466
GEN_SPEOP_COMP(efststlt);
6467
GEN_SPEOP_COMP(efststeq);
6989
6468
6990
6469
/* Opcodes definitions */
6991
GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
6470
GEN_SPE(efsadd, efssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6992
6471
GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6993
6472
GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6994
6473
GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6998
6477
GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6999
6478
GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
7000
6479
GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
7001
GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7002
GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
6480
GEN_SPE(efsctuiz, efsctsiz, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
7003
6481
GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
7004
6482
GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
7005
6483
7006
6484
/* Double precision floating-point operations */
7007
6485
/* Arithmetic */
7008
GEN_SPEFPUOP_ARITH2(efdadd);
7009
GEN_SPEFPUOP_ARITH2(efdsub);
7010
GEN_SPEFPUOP_ARITH2(efdmul);
7011
GEN_SPEFPUOP_ARITH2(efddiv);
7012
GEN_SPEFPUOP_ARITH1(efdabs);
7013
GEN_SPEFPUOP_ARITH1(efdnabs);
7014
GEN_SPEFPUOP_ARITH1(efdneg);
6486
GEN_SPEOP_ARITH2(efdadd);
6487
GEN_SPEOP_ARITH2(efdsub);
6488
GEN_SPEOP_ARITH2(efdmul);
6489
GEN_SPEOP_ARITH2(efddiv);
6490
GEN_SPEOP_ARITH1(efdabs);
6491
GEN_SPEOP_ARITH1(efdnabs);
6492
GEN_SPEOP_ARITH1(efdneg);
7015
6493
/* Conversion */
7016
6494
7017
6495
GEN_SPEFPUOP_CONV(efdcfui);
7030
6508
GEN_SPEFPUOP_CONV(efdctuidz);
7031
6509
GEN_SPEFPUOP_CONV(efdctsidz);
7032
6510
/* Comparison */
7033
GEN_SPEFPUOP_COMP(efdcmpgt);
7034
GEN_SPEFPUOP_COMP(efdcmplt);
7035
GEN_SPEFPUOP_COMP(efdcmpeq);
7036
GEN_SPEFPUOP_COMP(efdtstgt);
7037
GEN_SPEFPUOP_COMP(efdtstlt);
7038
GEN_SPEFPUOP_COMP(efdtsteq);
6511
GEN_SPEOP_COMP(efdcmpgt);
6512
GEN_SPEOP_COMP(efdcmplt);
6513
GEN_SPEOP_COMP(efdcmpeq);
6514
GEN_SPEOP_COMP(efdtstgt);
6515
GEN_SPEOP_COMP(efdtstlt);
6516
GEN_SPEOP_COMP(efdtsteq);
7039
6517
7040
6518
/* Opcodes definitions */
7041
6519
GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
7054
6532
GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
7055
6533
GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
7056
6534
GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
6535
#endif
7057
6536
7058
6537
/* End opcode list */
7059
6538
GEN_OPCODE_MARK(end);
7060
6539
7061
6540
#include "translate_init.c"
7062
#include "helper_regs.h"
7063
6541
7064
6542
/*****************************************************************************/
7065
6543
/* Misc PowerPC helpers */
6544
static always_inline uint32_t load_xer (CPUState *env)
6545
{
6546
return (xer_so << XER_SO) |
6547
(xer_ov << XER_OV) |
6548
(xer_ca << XER_CA) |
6549
(xer_bc << XER_BC) |
6550
(xer_cmp << XER_CMP);
6551
}
6552
7066
6553
void cpu_dump_state (CPUState *env, FILE *f,
7067
6554
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
7068
6555
int flags)
7069
6556
{
6557
#if defined(TARGET_PPC64) || 1
6558
#define FILL ""
7070
6559
#define RGPL 4
7071
6560
#define RFPL 4
6561
#else
6562
#define FILL " "
6563
#define RGPL 8
6564
#define RFPL 4
6565
#endif
7072
6566
7073
6567
int i;
7074
6568
7075
cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
7076
env->nip, env->lr, env->ctr, env->xer);
7077
cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
7078
env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
6569
cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX "\n",
6570
env->nip, env->lr, env->ctr);
6571
cpu_fprintf(f, "MSR " REGX FILL " XER %08x "
7079
6572
#if !defined(NO_TIMER_DUMP)
7080
cpu_fprintf(f, "TB %08x %08x "
6573
"TB %08x %08x "
7081
6574
#if !defined(CONFIG_USER_ONLY)
7082
6575
"DECR %08x"
7083
6576
#endif
6577
#endif
7084
6578
"\n",
7085
cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6579
do_load_msr(env), load_xer(env)
6580
#if !defined(NO_TIMER_DUMP)
6581
, cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7086
6582
#if !defined(CONFIG_USER_ONLY)
7087
6583
, cpu_ppc_load_decr(env)
7088
6584
#endif
6585
#endif
7089
6586
);
7090
#endif
7091
6587
for (i = 0; i < 32; i++) {
7092
6588
if ((i & (RGPL - 1)) == 0)
7093
6589
cpu_fprintf(f, "GPR%02d", i);
7094
cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
6590
cpu_fprintf(f, " " REGX, (target_ulong)env->gpr[i]);
7095
6591
if ((i & (RGPL - 1)) == (RGPL - 1))
7096
6592
cpu_fprintf(f, "\n");
7097
6593
}
7109
6605
a = 'E';
7110
6606
cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7111
6607
}
7112
cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
6608
cpu_fprintf(f, " ] " FILL "RES " REGX "\n", env->reserve);
7113
6609
for (i = 0; i < 32; i++) {
7114
6610
if ((i & (RFPL - 1)) == 0)
7115
6611
cpu_fprintf(f, "FPR%02d", i);
7118
6614
cpu_fprintf(f, "\n");
7119
6615
}
7120
6616
#if !defined(CONFIG_USER_ONLY)
7121
cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
6617
cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX " " FILL FILL FILL
6618
"SDR1 " REGX "\n",
7122
6619
env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
7123
6620
#endif
7124
6621
7125
6622
#undef RGPL
7126
6623
#undef RFPL
6624
#undef FILL
7127
6625
}
7128
6626
7129
6627
void cpu_dump_statistics (CPUState *env, FILE*f,
7174
6672
}
7175
6673
7176
6674
/*****************************************************************************/
7177
static always_inline void gen_intermediate_code_internal (CPUState *env,
7178
TranslationBlock *tb,
7179
int search_pc)
6675
static always_inline int gen_intermediate_code_internal (CPUState *env,
6676
TranslationBlock *tb,
6677
int search_pc)
7180
6678
{
7181
6679
DisasContext ctx, *ctxp = &ctx;
7182
6680
opc_handler_t **table, *handler;
7183
6681
target_ulong pc_start;
7184
6682
uint16_t *gen_opc_end;
7185
int supervisor, little_endian;
6683
int supervisor;
6684
int single_step, branch_step;
7186
6685
int j, lj = -1;
7187
int num_insns;
7188
int max_insns;
7189
6686
7190
6687
pc_start = tb->pc;
6688
gen_opc_ptr = gen_opc_buf;
7191
6689
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7192
#if defined(OPTIMIZE_FPRF_UPDATE)
7193
gen_fprf_ptr = gen_fprf_buf;
7194
#endif
6690
gen_opparam_ptr = gen_opparam_buf;
6691
nb_gen_labels = 0;
7195
6692
ctx.nip = pc_start;
7196
6693
ctx.tb = tb;
7197
6694
ctx.exception = POWERPC_EXCP_NONE;
7198
6695
ctx.spr_cb = env->spr_cb;
7199
supervisor = env->mmu_idx;
7200
#if !defined(CONFIG_USER_ONLY)
6696
#if defined(CONFIG_USER_ONLY)
6697
supervisor = 0;
6698
#else
6699
#if defined(TARGET_PPC64H)
6700
if (msr_pr == 0 && msr_hv == 1)
6701
supervisor = 2;
6702
else
6703
#endif
6704
supervisor = 1 - msr_pr;
7201
6705
ctx.supervisor = supervisor;
7202
6706
#endif
7203
little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
7204
6707
#if defined(TARGET_PPC64)
7205
6708
ctx.sf_mode = msr_sf;
7206
ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
6709
ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | msr_le;
7207
6710
#else
7208
ctx.mem_idx = (supervisor << 1) | little_endian;
6711
ctx.mem_idx = (supervisor << 1) | msr_le;
7209
6712
#endif
7210
6713
ctx.dcache_line_size = env->dcache_line_size;
7211
6714
ctx.fpu_enabled = msr_fp;
6715
#if defined(TARGET_PPCEMB)
7212
6716
if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
7213
6717
ctx.spe_enabled = msr_spe;
7214
6718
else
7215
6719
ctx.spe_enabled = 0;
6720
#endif
7216
6721
if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
7217
6722
ctx.altivec_enabled = msr_vr;
7218
6723
else
7219
6724
ctx.altivec_enabled = 0;
7220
6725
if ((env->flags & POWERPC_FLAG_SE) && msr_se)
7221
ctx.singlestep_enabled = CPU_SINGLE_STEP;
6726
single_step = 1;
7222
6727
else
7223
ctx.singlestep_enabled = 0;
6728
single_step = 0;
7224
6729
if ((env->flags & POWERPC_FLAG_BE) && msr_be)
7225
ctx.singlestep_enabled |= CPU_BRANCH_STEP;
7226
if (unlikely(env->singlestep_enabled))
7227
ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
6730
branch_step = 1;
6731
else
6732
branch_step = 0;
6733
ctx.singlestep_enabled = env->singlestep_enabled || single_step == 1;
7228
6734
#if defined (DO_SINGLE_STEP) && 0
7229
6735
/* Single step trace mode */
7230
6736
msr_se = 1;
7231
6737
#endif
7232
num_insns = 0;
7233
max_insns = tb->cflags & CF_COUNT_MASK;
7234
if (max_insns == 0)
7235
max_insns = CF_COUNT_MASK;
7236
7237
gen_icount_start();
7238
6738
/* Set env in case of segfault during code fetch */
7239
6739
while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
7240
6740
if (unlikely(env->nb_breakpoints > 0)) {
7254
6754
gen_opc_instr_start[lj++] = 0;
7255
6755
gen_opc_pc[lj] = ctx.nip;
7256
6756
gen_opc_instr_start[lj] = 1;
7257
gen_opc_icount[lj] = num_insns;
7258
6757
}
7259
6758
}
7260
6759
#if defined PPC_DEBUG_DISAS
7261
6760
if (loglevel & CPU_LOG_TB_IN_ASM) {
7262
6761
fprintf(logfile, "----------------\n");
7263
6762
fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
7264
ctx.nip, supervisor, (int)msr_ir);
6763
ctx.nip, 1 - msr_pr, msr_ir);
7265
6764
}
7266
6765
#endif
7267
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7268
gen_io_start();
7269
if (unlikely(little_endian)) {
7270
ctx.opcode = bswap32(ldl_code(ctx.nip));
7271
} else {
7272
ctx.opcode = ldl_code(ctx.nip);
6766
ctx.opcode = ldl_code(ctx.nip);
6767
if (msr_le) {
6768
ctx.opcode = ((ctx.opcode & 0xFF000000) >> 24) |
6769
((ctx.opcode & 0x00FF0000) >> 8) |
6770
((ctx.opcode & 0x0000FF00) << 8) |
6771
((ctx.opcode & 0x000000FF) << 24);
7273
6772
}
7274
6773
#if defined PPC_DEBUG_DISAS
7275
6774
if (loglevel & CPU_LOG_TB_IN_ASM) {
7276
6775
fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
7277
6776
ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7278
opc3(ctx.opcode), little_endian ? "little" : "big");
6777
opc3(ctx.opcode), msr_le ? "little" : "big");
7279
6778
}
7280
6779
#endif
7281
6780
ctx.nip += 4;
7282
6781
table = env->opcodes;
7283
num_insns++;
7284
6782
handler = table[opc1(ctx.opcode)];
7285
6783
if (is_indirect_opcode(handler)) {
7286
6784
table = ind_table(handler);
7294
6792
if (unlikely(handler->handler == &gen_invalid)) {
7295
6793
if (loglevel != 0) {
7296
6794
fprintf(logfile, "invalid/unsupported opcode: "
7297
"%02x - %02x - %02x (%08x) " ADDRX " %d\n",
6795
"%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
7298
6796
opc1(ctx.opcode), opc2(ctx.opcode),
7299
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
6797
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
7300
6798
} else {
7301
6799
printf("invalid/unsupported opcode: "
7302
"%02x - %02x - %02x (%08x) " ADDRX " %d\n",
6800
"%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
7303
6801
opc1(ctx.opcode), opc2(ctx.opcode),
7304
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
6802
opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
7305
6803
}
7306
6804
} else {
7307
6805
if (unlikely((ctx.opcode & handler->inval) != 0)) {
7308
6806
if (loglevel != 0) {
7309
6807
fprintf(logfile, "invalid bits: %08x for opcode: "
7310
"%02x - %02x - %02x (%08x) " ADDRX "\n",
6808
"%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
7311
6809
ctx.opcode & handler->inval, opc1(ctx.opcode),
7312
6810
opc2(ctx.opcode), opc3(ctx.opcode),
7313
6811
ctx.opcode, ctx.nip - 4);
7314
6812
} else {
7315
6813
printf("invalid bits: %08x for opcode: "
7316
"%02x - %02x - %02x (%08x) " ADDRX "\n",
6814
"%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
7317
6815
ctx.opcode & handler->inval, opc1(ctx.opcode),
7318
6816
opc2(ctx.opcode), opc3(ctx.opcode),
7319
6817
ctx.opcode, ctx.nip - 4);
7327
6825
handler->count++;
7328
6826
#endif
7329
6827
/* Check trace mode exceptions */
7330
if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7331
(ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7332
ctx.exception != POWERPC_SYSCALL &&
7333
ctx.exception != POWERPC_EXCP_TRAP &&
7334
ctx.exception != POWERPC_EXCP_BRANCH)) {
6828
if (unlikely(branch_step != 0 &&
6829
ctx.exception == POWERPC_EXCP_BRANCH)) {
6830
GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6831
} else if (unlikely(single_step != 0 &&
6832
(ctx.nip <= 0x100 || ctx.nip > 0xF00 ||
6833
(ctx.nip & 0xFC) != 0x04) &&
6834
ctx.exception != POWERPC_SYSCALL &&
6835
ctx.exception != POWERPC_EXCP_TRAP)) {
7335
6836
GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
7336
6837
} else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7337
(env->singlestep_enabled) ||
7338
num_insns >= max_insns)) {
6838
(env->singlestep_enabled))) {
7339
6839
/* if we reach a page boundary or are single stepping, stop
7340
6840
* generation
7341
6841
*/
7345
6845
break;
7346
6846
#endif
7347
6847
}
7348
if (tb->cflags & CF_LAST_IO)
7349
gen_io_end();
7350
6848
if (ctx.exception == POWERPC_EXCP_NONE) {
7351
6849
gen_goto_tb(&ctx, 0, ctx.nip);
7352
6850
} else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7353
if (unlikely(env->singlestep_enabled)) {
7354
gen_update_nip(&ctx, ctx.nip);
7355
gen_op_debug();
7356
}
6851
gen_op_reset_T0();
7357
6852
/* Generate the return instruction */
7358
tcg_gen_exit_tb(0);
6853
gen_op_exit_tb();
7359
6854
}
7360
gen_icount_end(tb, num_insns);
7361
6855
*gen_opc_ptr = INDEX_op_end;
7362
6856
if (unlikely(search_pc)) {
7363
6857
j = gen_opc_ptr - gen_opc_buf;
7366
6860
gen_opc_instr_start[lj++] = 0;
7367
6861
} else {
7368
6862
tb->size = ctx.nip - pc_start;
7369
tb->icount = num_insns;
7370
6863
}
7371
6864
#if defined(DEBUG_DISAS)
7372
6865
if (loglevel & CPU_LOG_TB_CPU) {
7376
6869
if (loglevel & CPU_LOG_TB_IN_ASM) {
7377
6870
int flags;
7378
6871
flags = env->bfd_mach;
7379
flags |= little_endian << 16;
6872
flags |= msr_le << 16;
7380
6873
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
7381
6874
target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
7382
6875
fprintf(logfile, "\n");
7383
6876
}
7384
#endif
7385
}
7386
7387
void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
7388
{
7389
gen_intermediate_code_internal(env, tb, 0);
7390
}
7391
7392
void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
7393
{
7394
gen_intermediate_code_internal(env, tb, 1);
7395
}
7396
7397
void gen_pc_load(CPUState *env, TranslationBlock *tb,
7398
unsigned long searched_pc, int pc_pos, void *puc)
7399
{
7400
int type, c;
7401
/* for PPC, we need to look at the micro operation to get the
7402
* access type */
7403
env->nip = gen_opc_pc[pc_pos];
7404
c = gen_opc_buf[pc_pos];
7405
switch(c) {
7406
#if defined(CONFIG_USER_ONLY)
7407
#define CASE3(op)\
7408
case INDEX_op_ ## op ## _raw
7409
#else
7410
#define CASE3(op)\
7411
case INDEX_op_ ## op ## _user:\
7412
case INDEX_op_ ## op ## _kernel:\
7413
case INDEX_op_ ## op ## _hypv
7414
#endif
7415
7416
CASE3(stfd):
7417
CASE3(stfs):
7418
CASE3(lfd):
7419
CASE3(lfs):
7420
type = ACCESS_FLOAT;
7421
break;
7422
CASE3(lwarx):
7423
type = ACCESS_RES;
7424
break;
7425
CASE3(stwcx):
7426
type = ACCESS_RES;
7427
break;
7428
CASE3(eciwx):
7429
CASE3(ecowx):
7430
type = ACCESS_EXT;
7431
break;
7432
default:
7433
type = ACCESS_INT;
7434
break;
6877
if (loglevel & CPU_LOG_TB_OP) {
6878
fprintf(logfile, "OP:\n");
6879
dump_ops(gen_opc_buf, gen_opparam_buf);
6880
fprintf(logfile, "\n");
7435
6881
}
7436
env->access_type = type;
6882
#endif
6883
return 0;
6884
}
6885
6886
int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
6887
{
6888
return gen_intermediate_code_internal(env, tb, 0);
6889
}
6890
6891
int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
6892
{
6893
return gen_intermediate_code_internal(env, tb, 1);
7437
6894
}
Loggerhead is a web-based interface for Breezy
Version: 2.0.1