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  • Committer: blueswir1
  • Date: 2007-11-25 08:48:16 UTC
  • Revision ID: git-v1:b76482e76560345c00e7d6c89199ced204a926d2
 Fix buffer mux handling for unconnected serial ports


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3737 c046a42c-6fe2-441c-8c8c-71466251a162

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Lines of Context:
hw/arm_gic.c
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#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
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#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
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#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
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#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
 
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#define GIC_TEST_LEVEL(irq, cm) (s->irq_state[irq].level & (cm)) != 0
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#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
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#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
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#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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#endif
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}
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static void gic_save(QEMUFile *f, void *opaque)
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{
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    gic_state *s = (gic_state *)opaque;
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    int i;
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    int j;
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    qemu_put_be32(f, s->enabled);
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    for (i = 0; i < NCPU; i++) {
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        qemu_put_be32(f, s->cpu_enabled[i]);
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#ifndef NVIC
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        qemu_put_be32(f, s->irq_target[i]);
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#endif
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        for (j = 0; j < 32; j++)
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            qemu_put_be32(f, s->priority1[j][i]);
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        for (j = 0; j < GIC_NIRQ; j++)
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            qemu_put_be32(f, s->last_active[j][i]);
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        qemu_put_be32(f, s->priority_mask[i]);
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        qemu_put_be32(f, s->running_irq[i]);
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        qemu_put_be32(f, s->running_priority[i]);
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        qemu_put_be32(f, s->current_pending[i]);
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    }
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    for (i = 0; i < GIC_NIRQ - 32; i++) {
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        qemu_put_be32(f, s->priority2[i]);
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    }
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    for (i = 0; i < GIC_NIRQ; i++) {
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        qemu_put_byte(f, s->irq_state[i].enabled);
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        qemu_put_byte(f, s->irq_state[i].pending);
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        qemu_put_byte(f, s->irq_state[i].active);
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        qemu_put_byte(f, s->irq_state[i].level);
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        qemu_put_byte(f, s->irq_state[i].model);
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        qemu_put_byte(f, s->irq_state[i].trigger);
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    }
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}
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static int gic_load(QEMUFile *f, void *opaque, int version_id)
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{
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    gic_state *s = (gic_state *)opaque;
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    int i;
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    int j;
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    if (version_id != 1)
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        return -EINVAL;
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    s->enabled = qemu_get_be32(f);
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    for (i = 0; i < NCPU; i++) {
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        s->cpu_enabled[i] = qemu_get_be32(f);
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#ifndef NVIC
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        s->irq_target[i] = qemu_get_be32(f);
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#endif
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        for (j = 0; j < 32; j++)
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            s->priority1[j][i] = qemu_get_be32(f);
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        for (j = 0; j < GIC_NIRQ; j++)
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            s->last_active[j][i] = qemu_get_be32(f);
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        s->priority_mask[i] = qemu_get_be32(f);
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        s->running_irq[i] = qemu_get_be32(f);
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        s->running_priority[i] = qemu_get_be32(f);
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        s->current_pending[i] = qemu_get_be32(f);
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    }
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    for (i = 0; i < GIC_NIRQ - 32; i++) {
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        s->priority2[i] = qemu_get_be32(f);
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    }
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    for (i = 0; i < GIC_NIRQ; i++) {
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        s->irq_state[i].enabled = qemu_get_byte(f);
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        s->irq_state[i].pending = qemu_get_byte(f);
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        s->irq_state[i].active = qemu_get_byte(f);
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        s->irq_state[i].level = qemu_get_byte(f);
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        s->irq_state[i].model = qemu_get_byte(f);
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        s->irq_state[i].trigger = qemu_get_byte(f);
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    }
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    return 0;
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}
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static gic_state *gic_init(uint32_t base, qemu_irq *parent_irq)
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{
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    gic_state *s;
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                                 iomemtype);
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    s->base = base;
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    gic_reset(s);
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    register_savevm("arm_gic", -1, 1, gic_save, gic_load, s);
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    return s;
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}