4
* Copyright (c) 2004-2005 Fabrice Bellard
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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#include "qemu-timer.h"
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#include "host-utils.h"
26
//#define DEBUG_IOAPIC
28
/* APIC Local Vector Table */
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#define APIC_LVT_TIMER 0
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#define APIC_LVT_THERMAL 1
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#define APIC_LVT_PERFORM 2
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#define APIC_LVT_LINT0 3
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#define APIC_LVT_LINT1 4
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#define APIC_LVT_ERROR 5
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/* APIC delivery modes */
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#define APIC_DM_FIXED 0
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#define APIC_DM_LOWPRI 1
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#define APIC_DM_INIT 5
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#define APIC_DM_SIPI 6
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#define APIC_DM_EXTINT 7
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/* APIC destination mode */
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#define APIC_DESTMODE_FLAT 0xf
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#define APIC_DESTMODE_CLUSTER 1
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#define APIC_TRIGGER_EDGE 0
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#define APIC_TRIGGER_LEVEL 1
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#define APIC_LVT_TIMER_PERIODIC (1<<17)
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#define APIC_LVT_MASKED (1<<16)
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#define APIC_LVT_LEVEL_TRIGGER (1<<15)
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#define APIC_LVT_REMOTE_IRR (1<<14)
57
#define APIC_INPUT_POLARITY (1<<13)
58
#define APIC_SEND_PENDING (1<<12)
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#define IOAPIC_NUM_PINS 0x18
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#define ESR_ILLEGAL_ADDRESS (1 << 7)
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#define APIC_SV_ENABLE (1 << 8)
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#define MAX_APIC_WORDS 8
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typedef struct APICState {
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uint32_t spurious_vec;
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uint32_t isr[8]; /* in service register */
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uint32_t tmr[8]; /* trigger mode register */
80
uint32_t irr[8]; /* interrupt request register */
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uint32_t lvt[APIC_LVT_NB];
82
uint32_t esr; /* error register */
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uint32_t initial_count;
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int64_t initial_count_load_time, next_time;
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uint64_t ioredtbl[IOAPIC_NUM_PINS];
100
static int apic_io_memory;
101
static APICState *local_apics[MAX_APICS + 1];
102
static int last_apic_id = 0;
104
static void apic_init_ipi(APICState *s);
105
static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
106
static void apic_update_irq(APICState *s);
108
/* Find first bit starting from msb */
109
static int fls_bit(uint32_t value)
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return 31 - clz32(value);
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/* Find first bit starting from lsb */
115
static int ffs_bit(uint32_t value)
120
static inline void set_bit(uint32_t *tab, int index)
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mask = 1 << (index & 0x1f);
128
static inline void reset_bit(uint32_t *tab, int index)
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mask = 1 << (index & 0x1f);
136
static void apic_local_deliver(CPUState *env, int vector)
138
APICState *s = env->apic_state;
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uint32_t lvt = s->lvt[vector];
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if (lvt & APIC_LVT_MASKED)
145
switch ((lvt >> 8) & 7) {
147
cpu_interrupt(env, CPU_INTERRUPT_SMI);
151
cpu_interrupt(env, CPU_INTERRUPT_NMI);
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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trigger_mode = APIC_TRIGGER_EDGE;
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if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
161
(lvt & APIC_LVT_LEVEL_TRIGGER))
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trigger_mode = APIC_TRIGGER_LEVEL;
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apic_set_irq(s, lvt & 0xff, trigger_mode);
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void apic_deliver_pic_intr(CPUState *env, int level)
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apic_local_deliver(env, APIC_LVT_LINT0);
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APICState *s = env->apic_state;
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uint32_t lvt = s->lvt[APIC_LVT_LINT0];
175
switch ((lvt >> 8) & 7) {
177
if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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reset_bit(s->irr, lvt & 0xff);
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
188
#define foreach_apic(apic, deliver_bitmask, code) \
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int __i, __j, __mask;\
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for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
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__mask = deliver_bitmask[__i];\
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for(__j = 0; __j < 32; __j++) {\
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if (__mask & (1 << __j)) {\
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apic = local_apics[__i * 32 + __j];\
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static void apic_bus_deliver(const uint32_t *deliver_bitmask,
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uint8_t delivery_mode,
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uint8_t vector_num, uint8_t polarity,
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uint8_t trigger_mode)
211
APICState *apic_iter;
213
switch (delivery_mode) {
215
/* XXX: search for focus processor, arbitration */
219
for(i = 0; i < MAX_APIC_WORDS; i++) {
220
if (deliver_bitmask[i]) {
221
d = i * 32 + ffs_bit(deliver_bitmask[i]);
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apic_iter = local_apics[d];
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apic_set_irq(apic_iter, vector_num, trigger_mode);
238
foreach_apic(apic_iter, deliver_bitmask,
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
243
foreach_apic(apic_iter, deliver_bitmask,
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
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/* normal INIT IPI sent to processors */
249
foreach_apic(apic_iter, deliver_bitmask,
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apic_init_ipi(apic_iter) );
254
/* handled in I/O APIC code */
261
foreach_apic(apic_iter, deliver_bitmask,
262
apic_set_irq(apic_iter, vector_num, trigger_mode) );
265
void cpu_set_apic_base(CPUState *env, uint64_t val)
267
APICState *s = env->apic_state;
269
printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
271
s->apicbase = (val & 0xfffff000) |
272
(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
273
/* if disabled, cannot be enabled again */
274
if (!(val & MSR_IA32_APICBASE_ENABLE)) {
275
s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
276
env->cpuid_features &= ~CPUID_APIC;
277
s->spurious_vec &= ~APIC_SV_ENABLE;
281
uint64_t cpu_get_apic_base(CPUState *env)
283
APICState *s = env->apic_state;
285
printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
290
void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
292
APICState *s = env->apic_state;
293
s->tpr = (val & 0x0f) << 4;
297
uint8_t cpu_get_apic_tpr(CPUX86State *env)
299
APICState *s = env->apic_state;
303
/* return -1 if no bit is set */
304
static int get_highest_priority_int(uint32_t *tab)
307
for(i = 7; i >= 0; i--) {
309
return i * 32 + fls_bit(tab[i]);
315
static int apic_get_ppr(APICState *s)
320
isrv = get_highest_priority_int(s->isr);
331
static int apic_get_arb_pri(APICState *s)
333
/* XXX: arbitration */
337
/* signal the CPU if an irq is pending */
338
static void apic_update_irq(APICState *s)
341
if (!(s->spurious_vec & APIC_SV_ENABLE))
343
irrv = get_highest_priority_int(s->irr);
346
ppr = apic_get_ppr(s);
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if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
352
static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
354
set_bit(s->irr, vector_num);
356
set_bit(s->tmr, vector_num);
358
reset_bit(s->tmr, vector_num);
362
static void apic_eoi(APICState *s)
365
isrv = get_highest_priority_int(s->isr);
368
reset_bit(s->isr, isrv);
369
/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
370
set the remote IRR bit for level triggered interrupts. */
374
static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
375
uint8_t dest, uint8_t dest_mode)
377
APICState *apic_iter;
380
if (dest_mode == 0) {
382
memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
384
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
385
set_bit(deliver_bitmask, dest);
388
/* XXX: cluster mode */
389
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
390
for(i = 0; i < MAX_APICS; i++) {
391
apic_iter = local_apics[i];
393
if (apic_iter->dest_mode == 0xf) {
394
if (dest & apic_iter->log_dest)
395
set_bit(deliver_bitmask, i);
396
} else if (apic_iter->dest_mode == 0x0) {
397
if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
398
(dest & apic_iter->log_dest & 0x0f)) {
399
set_bit(deliver_bitmask, i);
408
static void apic_init_ipi(APICState *s)
413
s->spurious_vec = 0xff;
416
memset(s->isr, 0, sizeof(s->isr));
417
memset(s->tmr, 0, sizeof(s->tmr));
418
memset(s->irr, 0, sizeof(s->irr));
419
for(i = 0; i < APIC_LVT_NB; i++)
420
s->lvt[i] = 1 << 16; /* mask LVT */
422
memset(s->icr, 0, sizeof(s->icr));
425
s->initial_count = 0;
426
s->initial_count_load_time = 0;
429
cpu_reset(s->cpu_env);
431
if (!(s->apicbase & MSR_IA32_APICBASE_BSP))
432
s->cpu_env->halted = 1;
435
/* send a SIPI message to the CPU to start it */
436
static void apic_startup(APICState *s, int vector_num)
438
CPUState *env = s->cpu_env;
442
cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
447
static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
448
uint8_t delivery_mode, uint8_t vector_num,
449
uint8_t polarity, uint8_t trigger_mode)
451
uint32_t deliver_bitmask[MAX_APIC_WORDS];
452
int dest_shorthand = (s->icr[0] >> 18) & 3;
453
APICState *apic_iter;
455
switch (dest_shorthand) {
457
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
460
memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
461
set_bit(deliver_bitmask, s->id);
464
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
467
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
468
reset_bit(deliver_bitmask, s->id);
472
switch (delivery_mode) {
475
int trig_mode = (s->icr[0] >> 15) & 1;
476
int level = (s->icr[0] >> 14) & 1;
477
if (level == 0 && trig_mode == 1) {
478
foreach_apic(apic_iter, deliver_bitmask,
479
apic_iter->arb_id = apic_iter->id );
486
foreach_apic(apic_iter, deliver_bitmask,
487
apic_startup(apic_iter, vector_num) );
491
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
495
int apic_get_interrupt(CPUState *env)
497
APICState *s = env->apic_state;
500
/* if the APIC is installed or enabled, we let the 8259 handle the
504
if (!(s->spurious_vec & APIC_SV_ENABLE))
507
/* XXX: spurious IRQ handling */
508
intno = get_highest_priority_int(s->irr);
511
if (s->tpr && intno <= s->tpr)
512
return s->spurious_vec & 0xff;
513
reset_bit(s->irr, intno);
514
set_bit(s->isr, intno);
519
int apic_accept_pic_intr(CPUState *env)
521
APICState *s = env->apic_state;
527
lvt0 = s->lvt[APIC_LVT_LINT0];
529
if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
530
(lvt0 & APIC_LVT_MASKED) == 0)
536
static uint32_t apic_get_current_count(APICState *s)
540
d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
542
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
544
val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
546
if (d >= s->initial_count)
549
val = s->initial_count - d;
554
static void apic_timer_update(APICState *s, int64_t current_time)
556
int64_t next_time, d;
558
if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
559
d = (current_time - s->initial_count_load_time) >>
561
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
562
if (!s->initial_count)
564
d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
566
if (d >= s->initial_count)
568
d = (uint64_t)s->initial_count + 1;
570
next_time = s->initial_count_load_time + (d << s->count_shift);
571
qemu_mod_timer(s->timer, next_time);
572
s->next_time = next_time;
575
qemu_del_timer(s->timer);
579
static void apic_timer(void *opaque)
581
APICState *s = opaque;
583
apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
584
apic_timer_update(s, s->next_time);
587
static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
592
static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
597
static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
601
static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
605
static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
612
env = cpu_single_env;
617
index = (addr >> 4) & 0xff;
622
case 0x03: /* version */
623
val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
629
val = apic_get_arb_pri(s);
633
val = apic_get_ppr(s);
639
val = s->log_dest << 24;
642
val = s->dest_mode << 28;
645
val = s->spurious_vec;
648
val = s->isr[index & 7];
651
val = s->tmr[index & 7];
654
val = s->irr[index & 7];
661
val = s->icr[index & 1];
664
val = s->lvt[index - 0x32];
667
val = s->initial_count;
670
val = apic_get_current_count(s);
673
val = s->divide_conf;
676
s->esr |= ESR_ILLEGAL_ADDRESS;
681
printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
686
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
692
env = cpu_single_env;
698
printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
701
index = (addr >> 4) & 0xff;
719
s->log_dest = val >> 24;
722
s->dest_mode = val >> 28;
725
s->spurious_vec = val & 0x1ff;
735
apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
736
(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
737
(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
744
int n = index - 0x32;
746
if (n == APIC_LVT_TIMER)
747
apic_timer_update(s, qemu_get_clock(vm_clock));
751
s->initial_count = val;
752
s->initial_count_load_time = qemu_get_clock(vm_clock);
753
apic_timer_update(s, s->initial_count_load_time);
760
s->divide_conf = val & 0xb;
761
v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
762
s->count_shift = (v + 1) & 7;
766
s->esr |= ESR_ILLEGAL_ADDRESS;
771
static void apic_save(QEMUFile *f, void *opaque)
773
APICState *s = opaque;
776
qemu_put_be32s(f, &s->apicbase);
777
qemu_put_8s(f, &s->id);
778
qemu_put_8s(f, &s->arb_id);
779
qemu_put_8s(f, &s->tpr);
780
qemu_put_be32s(f, &s->spurious_vec);
781
qemu_put_8s(f, &s->log_dest);
782
qemu_put_8s(f, &s->dest_mode);
783
for (i = 0; i < 8; i++) {
784
qemu_put_be32s(f, &s->isr[i]);
785
qemu_put_be32s(f, &s->tmr[i]);
786
qemu_put_be32s(f, &s->irr[i]);
788
for (i = 0; i < APIC_LVT_NB; i++) {
789
qemu_put_be32s(f, &s->lvt[i]);
791
qemu_put_be32s(f, &s->esr);
792
qemu_put_be32s(f, &s->icr[0]);
793
qemu_put_be32s(f, &s->icr[1]);
794
qemu_put_be32s(f, &s->divide_conf);
795
qemu_put_be32(f, s->count_shift);
796
qemu_put_be32s(f, &s->initial_count);
797
qemu_put_be64(f, s->initial_count_load_time);
798
qemu_put_be64(f, s->next_time);
800
qemu_put_timer(f, s->timer);
803
static int apic_load(QEMUFile *f, void *opaque, int version_id)
805
APICState *s = opaque;
811
/* XXX: what if the base changes? (registered memory regions) */
812
qemu_get_be32s(f, &s->apicbase);
813
qemu_get_8s(f, &s->id);
814
qemu_get_8s(f, &s->arb_id);
815
qemu_get_8s(f, &s->tpr);
816
qemu_get_be32s(f, &s->spurious_vec);
817
qemu_get_8s(f, &s->log_dest);
818
qemu_get_8s(f, &s->dest_mode);
819
for (i = 0; i < 8; i++) {
820
qemu_get_be32s(f, &s->isr[i]);
821
qemu_get_be32s(f, &s->tmr[i]);
822
qemu_get_be32s(f, &s->irr[i]);
824
for (i = 0; i < APIC_LVT_NB; i++) {
825
qemu_get_be32s(f, &s->lvt[i]);
827
qemu_get_be32s(f, &s->esr);
828
qemu_get_be32s(f, &s->icr[0]);
829
qemu_get_be32s(f, &s->icr[1]);
830
qemu_get_be32s(f, &s->divide_conf);
831
s->count_shift=qemu_get_be32(f);
832
qemu_get_be32s(f, &s->initial_count);
833
s->initial_count_load_time=qemu_get_be64(f);
834
s->next_time=qemu_get_be64(f);
837
qemu_get_timer(f, s->timer);
841
static void apic_reset(void *opaque)
843
APICState *s = opaque;
845
s->apicbase = 0xfee00000 |
846
(s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
852
* LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
853
* time typically by BIOS, so PIC interrupt can be delivered to the
854
* processor when local APIC is enabled.
856
s->lvt[APIC_LVT_LINT0] = 0x700;
860
static CPUReadMemoryFunc *apic_mem_read[3] = {
866
static CPUWriteMemoryFunc *apic_mem_write[3] = {
872
int apic_init(CPUState *env)
876
if (last_apic_id >= MAX_APICS)
878
s = qemu_mallocz(sizeof(APICState));
882
s->id = last_apic_id++;
883
env->cpuid_apic_id = s->id;
888
/* XXX: mapping more APICs at the same memory location */
889
if (apic_io_memory == 0) {
890
/* NOTE: the APIC is directly connected to the CPU - it is not
891
on the global memory bus. */
892
apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
893
apic_mem_write, NULL);
894
cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
897
s->timer = qemu_new_timer(vm_clock, apic_timer, s);
899
register_savevm("apic", s->id, 2, apic_save, apic_load, s);
900
qemu_register_reset(apic_reset, s);
902
local_apics[s->id] = s;
906
static void ioapic_service(IOAPICState *s)
911
uint8_t delivery_mode;
917
uint32_t deliver_bitmask[MAX_APIC_WORDS];
919
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
922
entry = s->ioredtbl[i];
923
if (!(entry & APIC_LVT_MASKED)) {
924
trig_mode = ((entry >> 15) & 1);
926
dest_mode = (entry >> 11) & 1;
927
delivery_mode = (entry >> 8) & 7;
928
polarity = (entry >> 13) & 1;
929
if (trig_mode == APIC_TRIGGER_EDGE)
931
if (delivery_mode == APIC_DM_EXTINT)
932
vector = pic_read_irq(isa_pic);
934
vector = entry & 0xff;
936
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
937
apic_bus_deliver(deliver_bitmask, delivery_mode,
938
vector, polarity, trig_mode);
944
void ioapic_set_irq(void *opaque, int vector, int level)
946
IOAPICState *s = opaque;
948
if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
949
uint32_t mask = 1 << vector;
950
uint64_t entry = s->ioredtbl[vector];
952
if ((entry >> 15) & 1) {
953
/* level triggered */
970
static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
972
IOAPICState *s = opaque;
979
} else if (addr == 0x10) {
980
switch (s->ioregsel) {
985
val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
991
index = (s->ioregsel - 0x10) >> 1;
992
if (index >= 0 && index < IOAPIC_NUM_PINS) {
994
val = s->ioredtbl[index] >> 32;
996
val = s->ioredtbl[index] & 0xffffffff;
1000
printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
1006
static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1008
IOAPICState *s = opaque;
1015
} else if (addr == 0x10) {
1017
printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
1019
switch (s->ioregsel) {
1021
s->id = (val >> 24) & 0xff;
1027
index = (s->ioregsel - 0x10) >> 1;
1028
if (index >= 0 && index < IOAPIC_NUM_PINS) {
1029
if (s->ioregsel & 1) {
1030
s->ioredtbl[index] &= 0xffffffff;
1031
s->ioredtbl[index] |= (uint64_t)val << 32;
1033
s->ioredtbl[index] &= ~0xffffffffULL;
1034
s->ioredtbl[index] |= val;
1042
static void ioapic_save(QEMUFile *f, void *opaque)
1044
IOAPICState *s = opaque;
1047
qemu_put_8s(f, &s->id);
1048
qemu_put_8s(f, &s->ioregsel);
1049
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1050
qemu_put_be64s(f, &s->ioredtbl[i]);
1054
static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
1056
IOAPICState *s = opaque;
1059
if (version_id != 1)
1062
qemu_get_8s(f, &s->id);
1063
qemu_get_8s(f, &s->ioregsel);
1064
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1065
qemu_get_be64s(f, &s->ioredtbl[i]);
1070
static void ioapic_reset(void *opaque)
1072
IOAPICState *s = opaque;
1075
memset(s, 0, sizeof(*s));
1076
for(i = 0; i < IOAPIC_NUM_PINS; i++)
1077
s->ioredtbl[i] = 1 << 16; /* mask LVT */
1080
static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1086
static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1092
IOAPICState *ioapic_init(void)
1097
s = qemu_mallocz(sizeof(IOAPICState));
1101
s->id = last_apic_id++;
1103
io_memory = cpu_register_io_memory(0, ioapic_mem_read,
1104
ioapic_mem_write, s);
1105
cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
1107
register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
1108
qemu_register_reset(ioapic_reset, s);
added
removed
hw/apic.c
