213
215
sra %o0,%g0,%o0 ! we return signed int, remember?
214
216
.size OPENSSL_atomic_add,.-OPENSSL_atomic_add
216
.global OPENSSL_rdtsc
218
.global _sparcv9_rdtick
218
222
.word 0x91408000 !rd %ccr,%o0
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save %sp,FRAME-16,%sp
223
mov 513,%o0 !SI_PLATFORM
238
.type OPENSSL_rdtsc,#function
239
.size OPENSSL_rdtsc,.-OPENSSL_atomic_add
226
.word 0x91410000 !rd %tick,%o0
228
.word 0x93323020 !srlx %o0,32,%o1
232
.type _sparcv9_rdtick,#function
233
.size _sparcv9_rdtick,.-_sparcv9_rdtick
235
.global _sparcv9_vis1_probe
238
.word 0x81b00d80 !fxor %f0,%f0,%f0
241
.word 0xc19a5a40 !ldda [%o1]ASI_FP16_P,%f0
242
.type _sparcv9_vis1_probe,#function
243
.size _sparcv9_vis1_probe,.-_sparcv9_vis1_probe
245
! Probe and instrument VIS1 instruction. Output is number of cycles it
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! takes to execute rdtick and pair of VIS1 instructions. US-Tx VIS unit
247
! is slow (documented to be 6 cycles on T2) and the core is in-order
248
! single-issue, it should be possible to distinguish Tx reliably...
249
! Observed return values are:
255
! Numbers for T2 and SPARC64 V-VII are more than welcomed.
257
! It would be possible to detect specifically US-T1 by instrumenting
258
! fmul8ulx16, which is emulated on T1 and as such accounts for quite
259
! a lot of %tick-s, couple of thousand on Linux...
260
.global _sparcv9_vis1_instrument
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_sparcv9_vis1_instrument:
263
.word 0x91410000 !rd %tick,%o0
264
.word 0x81b00d80 !fxor %f0,%f0,%f0
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.word 0x85b08d82 !fxor %f2,%f2,%f2
266
.word 0x93410000 !rd %tick,%o1
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.word 0x81b00d80 !fxor %f0,%f0,%f0
268
.word 0x85b08d82 !fxor %f2,%f2,%f2
269
.word 0x95410000 !rd %tick,%o2
270
.word 0x81b00d80 !fxor %f0,%f0,%f0
271
.word 0x85b08d82 !fxor %f2,%f2,%f2
272
.word 0x97410000 !rd %tick,%o3
273
.word 0x81b00d80 !fxor %f0,%f0,%f0
274
.word 0x85b08d82 !fxor %f2,%f2,%f2
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.word 0x99410000 !rd %tick,%o4
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! calculate intervals
285
.word 0x38680002 !bgu,a %xcc,.+8
288
.word 0x38680002 !bgu,a %xcc,.+8
291
.word 0x38680002 !bgu,a %xcc,.+8
296
.type _sparcv9_vis1_instrument,#function
297
.size _sparcv9_vis1_instrument,.-_sparcv9_vis1_instrument
299
.global _sparcv9_vis2_probe
303
.word 0x81b00980 !bshuffle %f0,%f0,%f0
304
.type _sparcv9_vis2_probe,#function
305
.size _sparcv9_vis2_probe,.-_sparcv9_vis2_probe
307
.global _sparcv9_fmadd_probe
309
_sparcv9_fmadd_probe:
310
.word 0x81b00d80 !fxor %f0,%f0,%f0
311
.word 0x85b08d82 !fxor %f2,%f2,%f2
313
.word 0x81b80440 !fmaddd %f0,%f0,%f2,%f0
314
.type _sparcv9_fmadd_probe,#function
315
.size _sparcv9_fmadd_probe,.-_sparcv9_fmadd_probe
317
.global OPENSSL_cleanse
344
! see above for explanation
345
.word 0x83408000 !rd %ccr,%g1
351
.v9lot: andcc %o0,7,%g0
360
.word 0xc0720000 !stx %g0,[%o0]
364
.word 0x126ffffd !bnz %xcc,.v9aligned
366
.word 0x124ffffd !bnz %icc,.v9aligned
376
.v8lot: andcc %o0,3,%g0
397
.type OPENSSL_cleanse,#function
398
.size OPENSSL_cleanse,.-OPENSSL_cleanse
400
.section ".init",#alloc,#execinstr
401
call OPENSSL_cpuid_setup