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by arcachofo
Initial Commit 0.5.15-RC3 |
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/*
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Copyright (C) 1998 T. Scott Dattalo
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This file is part of the libgpsim library of gpsim
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, see
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<http://www.gnu.org/licenses/lgpl-2.1.html>.
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*/
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#ifndef __16BIT_INSTRUCTIONS_H__
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#define __16BIT_INSTRUCTIONS_H__
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#include "14bit-instructions.h" |
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#include "16bit-registers.h" |
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/*---------------------------------------------------------
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* 16bit-instructions.h
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*
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* This .h file contains the definitions for the 16-bit core
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* instructions (the 16bit core of the 18cxxx processors that
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* is). Most of the instructions are derived from the corresponding
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* 12 and 14 bit core instructions. However, the virtual function
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* 'execute' is replaced. This is because the memory addressing and
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* the status register are different for the 16bit core. The alternative is
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* is to patch the existing instructions with the 16bit stuff.
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* I feel that this is an unwarranted performance hit. So gpsim
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* is slightly bigger, but it's also slightly faster...
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*/
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class Branching : public Instruction |
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{
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public: |
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int destination_index; |
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uint absolute_destination_index; |
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Branching(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(){ } |
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virtual void debug(){ } |
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virtual char *name(char *,int); |
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virtual bool isBase() { return true;} |
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void decode(Processor *new_cpu, uint new_opcode); |
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};
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class multi_word_instruction : public Instruction |
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{
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public: |
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uint word2_opcode; |
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uint PMaddress; |
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uint PMindex; |
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bool initialized; |
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multi_word_instruction(Processor *new_cpu, uint new_opcode, uint address); |
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virtual int instruction_size() { return 2;} |
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virtual enum INSTRUCTION_TYPES isa() {return MULTIWORD_INSTRUCTION;} |
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virtual bool isBase() { return true;} |
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virtual void initialize(bool init_state) { initialized = init_state; } |
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};
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class multi_word_branch : public multi_word_instruction |
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{
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public: |
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uint destination_index; |
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multi_word_branch(Processor *new_cpu, uint new_opcode, uint address); |
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void runtime_initialize(); |
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virtual void execute(){} |
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virtual char *name(char *,int); |
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};
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class ADDULNK : public Instruction |
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{
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public: |
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ADDULNK(Processor *new_cpu, uint new_opcode,const char *, uint address); |
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virtual bool isBase() { return true;} |
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virtual void execute(); |
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virtual char *name(char *,int); |
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protected: |
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uint m_lit; |
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};
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class ADDFSR16 : public Instruction |
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{
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public: |
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ADDFSR16(Processor *new_cpu, uint new_opcode,const char *, uint address); |
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virtual bool isBase() { return true;} |
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virtual void execute(); |
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virtual char *name(char *,int); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{
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if (((new_opcode>>6)&3) == 3) |
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{
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if (new_opcode & 0x100) |
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return new ADDULNK(new_cpu,new_opcode,"subulnk", address); |
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else
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return new ADDULNK(new_cpu,new_opcode,"addulnk", address); |
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}
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if (new_opcode & 0x100) |
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return new ADDFSR16(new_cpu,new_opcode,"subfsr", address); |
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return new ADDFSR16(new_cpu,new_opcode,"addfsr", address); |
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}
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protected: |
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uint m_fsr; |
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uint m_lit; |
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Indirect_Addressing *ia; |
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};
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class CALLW16 : public CALLW |
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{
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public: |
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CALLW16(Processor *new_cpu, uint new_opcode, uint address) : |
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CALLW(new_cpu, new_opcode, address){} |
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virtual bool isBase() { return true;} |
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virtual void execute(); |
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static Instruction*construct(Processor *new_cpu, uint new_opcode, uint address) |
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{
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return new CALLW16(new_cpu,new_opcode,address); |
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}
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};
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class MOVSF : public multi_word_instruction |
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{
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public: |
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MOVSF(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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virtual char *name(char *,int); |
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void runtime_initialize(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new MOVSF(new_cpu,new_opcode,address);} |
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protected: |
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uint source,destination; |
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};
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class PUSHL : public Instruction |
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{
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public: |
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PUSHL(Processor *new_cpu, uint new_opcode, uint address); |
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virtual bool isBase() { return true;} |
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virtual void execute(); |
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virtual char *name(char *,int); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{ return new PUSHL(new_cpu,new_opcode,address); } |
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protected: |
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uint m_lit; |
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};
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class ADDLW16 : public ADDLW |
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{
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public: |
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ADDLW16(Processor *new_cpu, uint new_opcode, uint address) : |
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ADDLW(new_cpu, new_opcode,address) |
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{}
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new ADDLW16(new_cpu,new_opcode,address);} |
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};
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class ADDWF16 : public ADDWF |
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{
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public: |
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int i = 0; |
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ADDWF16(Processor *new_cpu, uint new_opcode, uint address) |
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: ADDWF(new_cpu,new_opcode,address){} |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new ADDWF16(new_cpu,new_opcode,address);} |
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};
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class ADDWFC16 : public ADDWFC |
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{
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public: |
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ADDWFC16(Processor *new_cpu, uint new_opcode, uint address) |
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: ADDWFC(new_cpu,new_opcode,address){} |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new ADDWFC16(new_cpu,new_opcode,address);} |
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};
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class ANDLW16 : public ANDLW |
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{
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public: |
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ANDLW16(Processor *new_cpu, uint new_opcode, uint address) : |
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ANDLW(new_cpu, new_opcode,address) |
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{}
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new ANDLW16(new_cpu,new_opcode,address);} |
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};
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class ANDWF16 : public ANDWF |
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{
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public: |
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ANDWF16(Processor *new_cpu, uint new_opcode, uint address) |
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: ANDWF(new_cpu,new_opcode,address){} |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new ANDWF16(new_cpu,new_opcode,address);} |
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};
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class BC : public Branching |
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{
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public: |
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BC(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new BC(new_cpu,new_opcode,address);} |
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};
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class BN : public Branching |
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{
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public: |
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BN(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new BN(new_cpu,new_opcode,address);} |
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};
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class BNC : public Branching |
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{
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public: |
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BNC(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new BNC(new_cpu,new_opcode,address);} |
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};
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class BNN : public Branching |
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{
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public: |
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BNN(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new BNN(new_cpu,new_opcode,address);} |
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};
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class BNOV : public Branching |
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{
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public: |
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BNOV(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new BNOV(new_cpu,new_opcode,address);} |
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};
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class BNZ : public Branching |
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{
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public: |
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BNZ(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new BNZ(new_cpu,new_opcode,address);} |
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};
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class BOV : public Branching |
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{
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public: |
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BOV(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new BOV(new_cpu,new_opcode,address);} |
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};
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class BRA16 : public Instruction |
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{
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public: |
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int destination_index; |
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uint absolute_destination_index; |
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BRA16(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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virtual char *name(char *,int); |
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virtual bool isBase() { return true;} |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new BRA16(new_cpu,new_opcode,address);} |
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};
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class BSF16 : public BSF |
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{
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public: |
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int i = 0; |
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BSF16(Processor *new_cpu, uint new_opcode, uint address) |
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: BSF(new_cpu,new_opcode,address){} |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new BSF16(new_cpu,new_opcode,address);} |
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};
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class BCF16 : public BCF |
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{
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public: |
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int i = 0; |
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BCF16(Processor *new_cpu, uint new_opcode, uint address) |
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: BCF(new_cpu,new_opcode,address){} |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new BCF16(new_cpu,new_opcode,address);} |
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};
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class BTFSC16 : public BTFSC |
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{
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public: |
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int i = 0; |
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BTFSC16(Processor *new_cpu, uint new_opcode, uint address) |
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: BTFSC(new_cpu,new_opcode,address){} |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new BTFSC16(new_cpu,new_opcode,address);} |
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};
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class BTFSS16 : public BTFSS |
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{
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public: |
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int i = 0; |
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BTFSS16(Processor *new_cpu, uint new_opcode, uint address) |
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: BTFSS(new_cpu,new_opcode,address){} |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new BTFSS16(new_cpu,new_opcode,address);} |
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};
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class BTG : public Bit_op |
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{
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public: |
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BTG(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new BTG(new_cpu,new_opcode,address);} |
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};
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class BZ : public Branching |
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{
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public: |
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BZ(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new BZ(new_cpu,new_opcode,address);} |
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};
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class CALL16 : public multi_word_branch |
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{
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public: |
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bool fast; |
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CALL16(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new CALL16(new_cpu,new_opcode,address);} |
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virtual char *name(char *,int); |
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};
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class CLRF16 : public CLRF |
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{
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public: |
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CLRF16(Processor *new_cpu, uint new_opcode, uint address) |
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: CLRF(new_cpu,new_opcode,address){} |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new CLRF16(new_cpu,new_opcode,address);} |
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};
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class COMF16 : public COMF |
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{
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public: |
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COMF16(Processor *new_cpu, uint new_opcode, uint address) |
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: COMF(new_cpu,new_opcode,address){} |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new COMF16(new_cpu,new_opcode,address);} |
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};
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class CPFSEQ : public Register_op |
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{
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public: |
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CPFSEQ(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new CPFSEQ(new_cpu,new_opcode,address);} |
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};
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class CPFSGT : public Register_op |
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{
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public: |
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CPFSGT(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new CPFSGT(new_cpu,new_opcode,address);} |
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};
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class CPFSLT : public Register_op |
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{
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public: |
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CPFSLT(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new CPFSLT(new_cpu,new_opcode,address);} |
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};
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class DAW : public Instruction |
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{
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public: |
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DAW(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
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virtual bool isBase() { return true;} |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new DAW(new_cpu,new_opcode,address);} |
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};
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class DECF16 : public DECF |
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{
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public: |
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DECF16(Processor *new_cpu, uint new_opcode, uint address) |
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: DECF(new_cpu,new_opcode,address){} |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new DECF16(new_cpu,new_opcode,address);} |
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};
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class DECFSZ16 : public DECFSZ |
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{
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public: |
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DECFSZ16(Processor *new_cpu, uint new_opcode, uint address) |
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: DECFSZ(new_cpu,new_opcode,address){} |
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virtual void execute(); |
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static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
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{return new DECFSZ16(new_cpu,new_opcode,address);} |
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};
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class DCFSNZ : public Register_op |
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{
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public: |
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DCFSNZ(Processor *new_cpu, uint new_opcode, uint address); |
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virtual void execute(); |
|
455 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
456 |
{return new DCFSNZ(new_cpu,new_opcode,address);} |
|
457 |
};
|
|
458 |
||
459 |
class GOTO16 : public multi_word_branch |
|
460 |
{
|
|
461 |
public: |
|
462 |
GOTO16(Processor *new_cpu, uint new_opcode, uint address); |
|
463 |
virtual void execute(); |
|
464 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
465 |
{return new GOTO16(new_cpu,new_opcode,address);} |
|
466 |
};
|
|
467 |
||
468 |
class INCF16 : public INCF |
|
469 |
{
|
|
470 |
public: |
|
471 |
INCF16(Processor *new_cpu, uint new_opcode, uint address) |
|
472 |
: INCF(new_cpu,new_opcode,address){} |
|
473 |
virtual void execute(); |
|
474 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
475 |
{return new INCF16(new_cpu,new_opcode,address);} |
|
476 |
};
|
|
477 |
||
478 |
class INCFSZ16 : public INCFSZ |
|
479 |
{
|
|
480 |
public: |
|
481 |
INCFSZ16(Processor *new_cpu, uint new_opcode, uint address) |
|
482 |
: INCFSZ(new_cpu,new_opcode,address){} |
|
483 |
virtual void execute(); |
|
484 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
485 |
{return new INCFSZ16(new_cpu,new_opcode,address);} |
|
486 |
||
487 |
};
|
|
488 |
||
489 |
class INFSNZ : public Register_op |
|
490 |
{
|
|
491 |
public: |
|
492 |
INFSNZ(Processor *new_cpu, uint new_opcode, uint address); |
|
493 |
virtual void execute(); |
|
494 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
495 |
{return new INFSNZ(new_cpu,new_opcode,address);} |
|
496 |
};
|
|
497 |
||
498 |
//---------------------------------------------------------
|
|
499 |
||
500 |
class IORLW16 : public IORLW |
|
501 |
{
|
|
502 |
public: |
|
503 |
IORLW16(Processor *new_cpu, uint new_opcode, uint address) : |
|
504 |
IORLW(new_cpu, new_opcode,address) |
|
505 |
{}
|
|
506 |
virtual void execute(); |
|
507 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
508 |
{return new IORLW16(new_cpu,new_opcode,address);} |
|
509 |
};
|
|
510 |
||
511 |
//---------------------------------------------------------
|
|
512 |
class IORWF16 : public IORWF |
|
513 |
{
|
|
514 |
public: |
|
515 |
IORWF16(Processor *new_cpu, uint new_opcode, uint address) |
|
516 |
: IORWF(new_cpu,new_opcode,address){} |
|
517 |
virtual void execute(); |
|
518 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
519 |
{return new IORWF16(new_cpu,new_opcode,address);} |
|
520 |
};
|
|
521 |
||
522 |
class LCALL16 : public multi_word_branch |
|
523 |
{
|
|
524 |
public: |
|
525 |
bool fast; |
|
526 |
||
527 |
LCALL16(Processor *new_cpu, uint new_opcode, uint address); |
|
528 |
virtual void execute(); |
|
529 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
530 |
{return new LCALL16(new_cpu,new_opcode,address);} |
|
531 |
virtual char *name(char *,int); |
|
532 |
};
|
|
533 |
||
534 |
class LFSR : public multi_word_instruction |
|
535 |
{
|
|
536 |
public: |
|
537 |
uint fsr,k; |
|
538 |
Indirect_Addressing *ia; |
|
539 |
||
540 |
LFSR(Processor *new_cpu, uint new_opcode, uint address); |
|
541 |
virtual void execute(); |
|
542 |
virtual char *name(char *,int); |
|
543 |
void runtime_initialize(); |
|
544 |
||
545 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
546 |
{return new LFSR(new_cpu,new_opcode,address);} |
|
547 |
};
|
|
548 |
||
549 |
class MOVF16 : public MOVF |
|
550 |
{
|
|
551 |
public: |
|
552 |
MOVF16(Processor *new_cpu, uint new_opcode, uint address) |
|
553 |
: MOVF(new_cpu,new_opcode,address){} |
|
554 |
virtual void execute(); |
|
555 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
556 |
{return new MOVF16(new_cpu,new_opcode,address);} |
|
557 |
};
|
|
558 |
||
559 |
class MOVFF : public multi_word_instruction |
|
560 |
{
|
|
561 |
public: |
|
562 |
uint source,destination; |
|
563 |
||
564 |
MOVFF(Processor *new_cpu, uint new_opcode, uint address); |
|
565 |
virtual void execute(); |
|
566 |
virtual char *name(char *,int); |
|
567 |
void runtime_initialize(); |
|
568 |
||
569 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
570 |
{return new MOVFF(new_cpu,new_opcode,address);} |
|
571 |
};
|
|
572 |
||
573 |
class MOVFP : public multi_word_instruction |
|
574 |
{
|
|
575 |
public: |
|
576 |
uint source,destination; |
|
577 |
||
578 |
MOVFP(Processor *new_cpu, uint new_opcode, uint address); |
|
579 |
virtual void execute(); |
|
580 |
virtual char *name(char *,int); |
|
581 |
void runtime_initialize(); |
|
582 |
||
583 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
584 |
{return new MOVFP(new_cpu,new_opcode,address);} |
|
585 |
};
|
|
586 |
||
587 |
class MOVLB16 : public Literal_op |
|
588 |
{
|
|
589 |
public: |
|
590 |
MOVLB16(Processor *new_cpu, uint new_opcode, uint address); |
|
591 |
virtual void execute(); |
|
592 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
593 |
{return new MOVLB16(new_cpu,new_opcode,address);} |
|
594 |
};
|
|
595 |
||
596 |
class MOVLR : public Literal_op |
|
597 |
{
|
|
598 |
public: |
|
599 |
MOVLR(Processor *new_cpu, uint new_opcode, uint address); |
|
600 |
virtual void execute(); |
|
601 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
602 |
{return new MOVLR(new_cpu,new_opcode,address);} |
|
603 |
};
|
|
604 |
||
605 |
class MOVPF : public multi_word_instruction |
|
606 |
{
|
|
607 |
public: |
|
608 |
uint source,destination; |
|
609 |
||
610 |
MOVPF(Processor *new_cpu, uint new_opcode, uint address); |
|
611 |
virtual void execute(); |
|
612 |
virtual char *name(char *,int); |
|
613 |
void runtime_initialize(); |
|
614 |
||
615 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
616 |
{return new MOVPF(new_cpu,new_opcode,address);} |
|
617 |
};
|
|
618 |
||
619 |
class MOVWF16 : public MOVWF |
|
620 |
{
|
|
621 |
public: |
|
622 |
MOVWF16(Processor *new_cpu, uint new_opcode, uint address); |
|
623 |
virtual void execute(); |
|
624 |
||
625 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
626 |
{return new MOVWF16(new_cpu,new_opcode,address);} |
|
627 |
};
|
|
628 |
||
629 |
class MULLW : public Literal_op |
|
630 |
{
|
|
631 |
public: |
|
632 |
MULLW(Processor *new_cpu, uint new_opcode, uint address); |
|
633 |
virtual void execute(); |
|
634 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
635 |
{return new MULLW(new_cpu,new_opcode,address);} |
|
636 |
};
|
|
637 |
||
638 |
class MULWF : public Register_op |
|
639 |
{
|
|
640 |
public: |
|
641 |
MULWF(Processor *new_cpu, uint new_opcode, uint address); |
|
642 |
virtual void execute(); |
|
643 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
644 |
{return new MULWF(new_cpu,new_opcode,address);} |
|
645 |
};
|
|
646 |
||
647 |
class NEGF : public Register_op |
|
648 |
{
|
|
649 |
public: |
|
650 |
NEGF(Processor *new_cpu, uint new_opcode, uint address); |
|
651 |
virtual void execute(); |
|
652 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
653 |
{return new NEGF(new_cpu,new_opcode,address);} |
|
654 |
};
|
|
655 |
||
656 |
class NEGW : public Register_op |
|
657 |
{
|
|
658 |
public: |
|
659 |
||
660 |
NEGW(Processor *new_cpu, uint new_opcode, uint address); |
|
661 |
virtual void execute(); |
|
662 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
663 |
{return new NEGW(new_cpu,new_opcode,address);} |
|
664 |
};
|
|
665 |
||
666 |
class POP : public Instruction |
|
667 |
{
|
|
668 |
public: |
|
669 |
POP(Processor *new_cpu, uint new_opcode, uint address); |
|
670 |
virtual void execute(); |
|
671 |
virtual bool isBase() { return true;} |
|
672 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
673 |
{return new POP(new_cpu,new_opcode,address);} |
|
674 |
};
|
|
675 |
||
676 |
class PUSH : public Instruction |
|
677 |
{
|
|
678 |
public: |
|
679 |
PUSH(Processor *new_cpu, uint new_opcode, uint address); |
|
680 |
virtual void execute(); |
|
681 |
virtual bool isBase() { return true;} |
|
682 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
683 |
{return new PUSH(new_cpu,new_opcode,address);} |
|
684 |
};
|
|
685 |
||
686 |
class RCALL : public Instruction |
|
687 |
{
|
|
688 |
public: |
|
689 |
int destination_index; |
|
690 |
uint absolute_destination_index; |
|
691 |
||
692 |
RCALL(Processor *new_cpu, uint new_opcode, uint address); |
|
693 |
virtual void execute(); |
|
694 |
virtual char *name(char *,int); |
|
695 |
virtual bool isBase() { return true;} |
|
696 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
697 |
{return new RCALL(new_cpu,new_opcode,address);} |
|
698 |
};
|
|
699 |
||
700 |
class RETFIE16 : public RETFIE |
|
701 |
{
|
|
702 |
public: |
|
703 |
bool fast; |
|
704 |
||
705 |
RETFIE16(Processor *new_cpu, uint new_opcode, uint address) : |
|
706 |
RETFIE(new_cpu,new_opcode,address) |
|
707 |
{
|
|
708 |
fast = (new_opcode & 1); |
|
709 |
};
|
|
710 |
virtual void execute(); |
|
711 |
virtual char *name(char *,int); |
|
712 |
||
713 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
714 |
{return new RETFIE16(new_cpu,new_opcode,address);} |
|
715 |
};
|
|
716 |
||
717 |
class RETURN16 : public RETURN |
|
718 |
{
|
|
719 |
public: |
|
720 |
bool fast; |
|
721 |
||
722 |
RETURN16(Processor *new_cpu, uint new_opcode, uint address) : |
|
723 |
RETURN(new_cpu,new_opcode,address) |
|
724 |
{ fast = (new_opcode & 1); } |
|
725 |
virtual void execute(); |
|
726 |
virtual char *name(char *,int); |
|
727 |
||
728 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
729 |
{return new RETURN16(new_cpu,new_opcode,address);} |
|
730 |
};
|
|
731 |
||
732 |
class RLCF : public Register_op |
|
733 |
{
|
|
734 |
public: |
|
735 |
RLCF(Processor *new_cpu, uint new_opcode, uint address); |
|
736 |
virtual void execute(); |
|
737 |
||
738 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
739 |
{return new RLCF(new_cpu,new_opcode,address);} |
|
740 |
};
|
|
741 |
||
742 |
class RLNCF : public Register_op |
|
743 |
{
|
|
744 |
public: |
|
745 |
RLNCF(Processor *new_cpu, uint new_opcode, uint address); |
|
746 |
virtual void execute(); |
|
747 |
||
748 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
749 |
{return new RLNCF(new_cpu,new_opcode,address);} |
|
750 |
};
|
|
751 |
||
752 |
class RRCF : public Register_op |
|
753 |
{
|
|
754 |
public: |
|
755 |
RRCF(Processor *new_cpu, uint new_opcode, uint address); |
|
756 |
virtual void execute(); |
|
757 |
||
758 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
759 |
{return new RRCF(new_cpu,new_opcode,address);} |
|
760 |
};
|
|
761 |
||
762 |
class RRNCF : public Register_op |
|
763 |
{
|
|
764 |
public: |
|
765 |
RRNCF(Processor *new_cpu, uint new_opcode, uint address); |
|
766 |
virtual void execute(); |
|
767 |
||
768 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
769 |
{return new RRNCF(new_cpu,new_opcode,address);} |
|
770 |
};
|
|
771 |
||
772 |
class SETF : public Register_op |
|
773 |
{
|
|
774 |
public: |
|
775 |
SETF(Processor *new_cpu, uint new_opcode, uint address); |
|
776 |
virtual void execute(); |
|
777 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
778 |
{return new SETF(new_cpu,new_opcode,address);} |
|
779 |
};
|
|
780 |
||
781 |
class SLEEP16 : public SLEEP |
|
782 |
{
|
|
783 |
public: |
|
784 |
SLEEP16(Processor *new_cpu, uint new_opcode, uint address) : |
|
785 |
SLEEP(new_cpu,new_opcode,address) { } |
|
786 |
virtual void execute(); |
|
787 |
||
788 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
789 |
{return new SLEEP16(new_cpu,new_opcode,address);} |
|
790 |
};
|
|
791 |
||
792 |
class SUBFWB : public Register_op |
|
793 |
{
|
|
794 |
public: |
|
795 |
SUBFWB(Processor *new_cpu, uint new_opcode, uint address); |
|
796 |
virtual void execute(); |
|
797 |
||
798 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
799 |
{return new SUBFWB(new_cpu,new_opcode,address);} |
|
800 |
};
|
|
801 |
||
802 |
class SUBLW16 : public SUBLW |
|
803 |
{
|
|
804 |
public: |
|
805 |
SUBLW16(Processor *new_cpu, uint new_opcode, uint address) : |
|
806 |
SUBLW(new_cpu,new_opcode,address) { } |
|
807 |
virtual void execute(); |
|
808 |
||
809 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
810 |
{return new SUBLW16(new_cpu,new_opcode,address);} |
|
811 |
};
|
|
812 |
||
813 |
class SUBWF16 : public SUBWF |
|
814 |
{
|
|
815 |
public: |
|
816 |
SUBWF16(Processor *new_cpu, uint new_opcode, uint address) : |
|
817 |
SUBWF(new_cpu,new_opcode,address) { } |
|
818 |
virtual void execute(); |
|
819 |
||
820 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
821 |
{return new SUBWF16(new_cpu,new_opcode,address);} |
|
822 |
};
|
|
823 |
||
824 |
class SUBWFB16 : public SUBWFB |
|
825 |
{
|
|
826 |
public: |
|
827 |
SUBWFB16(Processor *new_cpu, uint new_opcode, uint address) : |
|
828 |
SUBWFB(new_cpu,new_opcode,address){} |
|
829 |
virtual void execute(); |
|
830 |
||
831 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
832 |
{return new SUBWFB16(new_cpu,new_opcode,address);} |
|
833 |
};
|
|
834 |
||
835 |
class SWAPF16 : public SWAPF |
|
836 |
{
|
|
837 |
public: |
|
838 |
SWAPF16(Processor *new_cpu, uint new_opcode, uint address) : |
|
839 |
SWAPF(new_cpu,new_opcode,address){} |
|
840 |
virtual void execute(); |
|
841 |
||
842 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
843 |
{return new SWAPF16(new_cpu,new_opcode,address);} |
|
844 |
};
|
|
845 |
||
846 |
class TBLRD : public Instruction |
|
847 |
{
|
|
848 |
public: |
|
849 |
TBLRD(Processor *new_cpu, uint new_opcode, uint address); |
|
850 |
virtual void execute(); |
|
851 |
virtual char *name(char *,int); |
|
852 |
virtual bool isBase() { return true;} |
|
853 |
||
854 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
855 |
{return new TBLRD(new_cpu,new_opcode,address);} |
|
856 |
};
|
|
857 |
||
858 |
class TBLWT : public Instruction |
|
859 |
{
|
|
860 |
public: |
|
861 |
TBLWT(Processor *new_cpu, uint new_opcode, uint address); |
|
862 |
virtual void execute(); |
|
863 |
virtual char *name(char *,int); |
|
864 |
virtual bool isBase() { return true;} |
|
865 |
||
866 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
867 |
{return new TBLWT(new_cpu,new_opcode,address);} |
|
868 |
};
|
|
869 |
||
870 |
class TLRD : public Instruction |
|
871 |
{
|
|
872 |
public: |
|
873 |
TLRD(Processor *new_cpu, uint new_opcode, uint address); |
|
874 |
virtual void execute(); |
|
875 |
virtual char *name(char *,int); |
|
876 |
virtual bool isBase() { return true;} |
|
877 |
||
878 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
879 |
{return new TLRD(new_cpu,new_opcode,address);} |
|
880 |
};
|
|
881 |
||
882 |
class TLWT : public Instruction |
|
883 |
{
|
|
884 |
public: |
|
885 |
TLWT(Processor *new_cpu, uint new_opcode, uint address); |
|
886 |
virtual void execute(); |
|
887 |
virtual char *name(char *,int); |
|
888 |
virtual bool isBase() { return true;} |
|
889 |
||
890 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
891 |
{return new TLWT(new_cpu,new_opcode,address);} |
|
892 |
};
|
|
893 |
||
894 |
class TSTFSZ : public Register_op |
|
895 |
{
|
|
896 |
public: |
|
897 |
TSTFSZ(Processor *new_cpu, uint new_opcode, uint address); |
|
898 |
virtual void execute(); |
|
899 |
||
900 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
901 |
{return new TSTFSZ(new_cpu,new_opcode,address);} |
|
902 |
};
|
|
903 |
||
904 |
class XORLW16 : public XORLW |
|
905 |
{
|
|
906 |
public: |
|
907 |
XORLW16(Processor *new_cpu, uint new_opcode, uint address) : |
|
908 |
XORLW(new_cpu, new_opcode, address){} |
|
909 |
virtual void execute(); |
|
910 |
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address) |
|
911 |
{return new XORLW16(new_cpu,new_opcode,address);} |
|
912 |
};
|
|
913 |
||
914 |
class XORWF16 : public XORWF |
|
915 |
{
|
|
916 |
public: |
|
917 |
XORWF16(Processor *new_cpu, uint new_opcode, uint address) |
|
918 |
: XORWF(new_cpu,new_opcode, address){} |
|
919 |
virtual void execute(); |
|
920 |
static Instruction *construct( Processor *new_cpu, uint new_opcode, uint address ) |
|
921 |
{ return new XORWF16(new_cpu,new_opcode,address); } |
|
922 |
};
|
|
923 |
||
924 |
#endif /* __12BIT_INSTRUCTIONS_H__ */ |