1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
|
/*
Copyright (C) 1998 T. Scott Dattalo
This file is part of the libgpsim library of gpsim
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, see
<http://www.gnu.org/licenses/lgpl-2.1.html>.
*/
#ifndef __16BIT_INSTRUCTIONS_H__
#define __16BIT_INSTRUCTIONS_H__
#include "14bit-instructions.h"
#include "16bit-registers.h"
/*---------------------------------------------------------
* 16bit-instructions.h
*
* This .h file contains the definitions for the 16-bit core
* instructions (the 16bit core of the 18cxxx processors that
* is). Most of the instructions are derived from the corresponding
* 12 and 14 bit core instructions. However, the virtual function
* 'execute' is replaced. This is because the memory addressing and
* the status register are different for the 16bit core. The alternative is
* is to patch the existing instructions with the 16bit stuff.
* I feel that this is an unwarranted performance hit. So gpsim
* is slightly bigger, but it's also slightly faster...
*/
class Branching : public Instruction
{
public:
int destination_index;
uint absolute_destination_index;
Branching(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute(){ }
virtual void debug(){ }
virtual char *name(char *,int);
virtual bool isBase() { return true;}
void decode(Processor *new_cpu, uint new_opcode);
};
class multi_word_instruction : public Instruction
{
public:
uint word2_opcode;
uint PMaddress;
uint PMindex;
bool initialized;
multi_word_instruction(Processor *new_cpu, uint new_opcode, uint address);
virtual int instruction_size() { return 2;}
virtual enum INSTRUCTION_TYPES isa() {return MULTIWORD_INSTRUCTION;}
virtual bool isBase() { return true;}
virtual void initialize(bool init_state) { initialized = init_state; }
};
class multi_word_branch : public multi_word_instruction
{
public:
uint destination_index;
multi_word_branch(Processor *new_cpu, uint new_opcode, uint address);
void runtime_initialize();
virtual void execute(){}
virtual char *name(char *,int);
};
class ADDULNK : public Instruction
{
public:
ADDULNK(Processor *new_cpu, uint new_opcode,const char *, uint address);
virtual bool isBase() { return true;}
virtual void execute();
virtual char *name(char *,int);
protected:
uint m_lit;
};
class ADDFSR16 : public Instruction
{
public:
ADDFSR16(Processor *new_cpu, uint new_opcode,const char *, uint address);
virtual bool isBase() { return true;}
virtual void execute();
virtual char *name(char *,int);
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{
if (((new_opcode>>6)&3) == 3)
{
if (new_opcode & 0x100)
return new ADDULNK(new_cpu,new_opcode,"subulnk", address);
else
return new ADDULNK(new_cpu,new_opcode,"addulnk", address);
}
if (new_opcode & 0x100)
return new ADDFSR16(new_cpu,new_opcode,"subfsr", address);
return new ADDFSR16(new_cpu,new_opcode,"addfsr", address);
}
protected:
uint m_fsr;
uint m_lit;
Indirect_Addressing *ia;
};
class CALLW16 : public CALLW
{
public:
CALLW16(Processor *new_cpu, uint new_opcode, uint address) :
CALLW(new_cpu, new_opcode, address){}
virtual bool isBase() { return true;}
virtual void execute();
static Instruction*construct(Processor *new_cpu, uint new_opcode, uint address)
{
return new CALLW16(new_cpu,new_opcode,address);
}
};
class MOVSF : public multi_word_instruction
{
public:
MOVSF(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
virtual char *name(char *,int);
void runtime_initialize();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new MOVSF(new_cpu,new_opcode,address);}
protected:
uint source,destination;
};
class PUSHL : public Instruction
{
public:
PUSHL(Processor *new_cpu, uint new_opcode, uint address);
virtual bool isBase() { return true;}
virtual void execute();
virtual char *name(char *,int);
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{ return new PUSHL(new_cpu,new_opcode,address); }
protected:
uint m_lit;
};
class ADDLW16 : public ADDLW
{
public:
ADDLW16(Processor *new_cpu, uint new_opcode, uint address) :
ADDLW(new_cpu, new_opcode,address)
{}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new ADDLW16(new_cpu,new_opcode,address);}
};
class ADDWF16 : public ADDWF
{
public:
int i = 0;
ADDWF16(Processor *new_cpu, uint new_opcode, uint address)
: ADDWF(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new ADDWF16(new_cpu,new_opcode,address);}
};
class ADDWFC16 : public ADDWFC
{
public:
ADDWFC16(Processor *new_cpu, uint new_opcode, uint address)
: ADDWFC(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new ADDWFC16(new_cpu,new_opcode,address);}
};
class ANDLW16 : public ANDLW
{
public:
ANDLW16(Processor *new_cpu, uint new_opcode, uint address) :
ANDLW(new_cpu, new_opcode,address)
{}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new ANDLW16(new_cpu,new_opcode,address);}
};
class ANDWF16 : public ANDWF
{
public:
ANDWF16(Processor *new_cpu, uint new_opcode, uint address)
: ANDWF(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new ANDWF16(new_cpu,new_opcode,address);}
};
class BC : public Branching
{
public:
BC(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new BC(new_cpu,new_opcode,address);}
};
class BN : public Branching
{
public:
BN(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new BN(new_cpu,new_opcode,address);}
};
class BNC : public Branching
{
public:
BNC(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new BNC(new_cpu,new_opcode,address);}
};
class BNN : public Branching
{
public:
BNN(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new BNN(new_cpu,new_opcode,address);}
};
class BNOV : public Branching
{
public:
BNOV(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new BNOV(new_cpu,new_opcode,address);}
};
class BNZ : public Branching
{
public:
BNZ(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new BNZ(new_cpu,new_opcode,address);}
};
class BOV : public Branching
{
public:
BOV(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new BOV(new_cpu,new_opcode,address);}
};
class BRA16 : public Instruction
{
public:
int destination_index;
uint absolute_destination_index;
BRA16(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
virtual char *name(char *,int);
virtual bool isBase() { return true;}
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new BRA16(new_cpu,new_opcode,address);}
};
class BSF16 : public BSF
{
public:
int i = 0;
BSF16(Processor *new_cpu, uint new_opcode, uint address)
: BSF(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new BSF16(new_cpu,new_opcode,address);}
};
class BCF16 : public BCF
{
public:
int i = 0;
BCF16(Processor *new_cpu, uint new_opcode, uint address)
: BCF(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new BCF16(new_cpu,new_opcode,address);}
};
class BTFSC16 : public BTFSC
{
public:
int i = 0;
BTFSC16(Processor *new_cpu, uint new_opcode, uint address)
: BTFSC(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new BTFSC16(new_cpu,new_opcode,address);}
};
class BTFSS16 : public BTFSS
{
public:
int i = 0;
BTFSS16(Processor *new_cpu, uint new_opcode, uint address)
: BTFSS(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new BTFSS16(new_cpu,new_opcode,address);}
};
class BTG : public Bit_op
{
public:
BTG(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new BTG(new_cpu,new_opcode,address);}
};
class BZ : public Branching
{
public:
BZ(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new BZ(new_cpu,new_opcode,address);}
};
class CALL16 : public multi_word_branch
{
public:
bool fast;
CALL16(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new CALL16(new_cpu,new_opcode,address);}
virtual char *name(char *,int);
};
class CLRF16 : public CLRF
{
public:
CLRF16(Processor *new_cpu, uint new_opcode, uint address)
: CLRF(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new CLRF16(new_cpu,new_opcode,address);}
};
class COMF16 : public COMF
{
public:
COMF16(Processor *new_cpu, uint new_opcode, uint address)
: COMF(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new COMF16(new_cpu,new_opcode,address);}
};
class CPFSEQ : public Register_op
{
public:
CPFSEQ(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new CPFSEQ(new_cpu,new_opcode,address);}
};
class CPFSGT : public Register_op
{
public:
CPFSGT(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new CPFSGT(new_cpu,new_opcode,address);}
};
class CPFSLT : public Register_op
{
public:
CPFSLT(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new CPFSLT(new_cpu,new_opcode,address);}
};
class DAW : public Instruction
{
public:
DAW(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
virtual bool isBase() { return true;}
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new DAW(new_cpu,new_opcode,address);}
};
class DECF16 : public DECF
{
public:
DECF16(Processor *new_cpu, uint new_opcode, uint address)
: DECF(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new DECF16(new_cpu,new_opcode,address);}
};
class DECFSZ16 : public DECFSZ
{
public:
DECFSZ16(Processor *new_cpu, uint new_opcode, uint address)
: DECFSZ(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new DECFSZ16(new_cpu,new_opcode,address);}
};
class DCFSNZ : public Register_op
{
public:
DCFSNZ(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new DCFSNZ(new_cpu,new_opcode,address);}
};
class GOTO16 : public multi_word_branch
{
public:
GOTO16(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new GOTO16(new_cpu,new_opcode,address);}
};
class INCF16 : public INCF
{
public:
INCF16(Processor *new_cpu, uint new_opcode, uint address)
: INCF(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new INCF16(new_cpu,new_opcode,address);}
};
class INCFSZ16 : public INCFSZ
{
public:
INCFSZ16(Processor *new_cpu, uint new_opcode, uint address)
: INCFSZ(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new INCFSZ16(new_cpu,new_opcode,address);}
};
class INFSNZ : public Register_op
{
public:
INFSNZ(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new INFSNZ(new_cpu,new_opcode,address);}
};
//---------------------------------------------------------
class IORLW16 : public IORLW
{
public:
IORLW16(Processor *new_cpu, uint new_opcode, uint address) :
IORLW(new_cpu, new_opcode,address)
{}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new IORLW16(new_cpu,new_opcode,address);}
};
//---------------------------------------------------------
class IORWF16 : public IORWF
{
public:
IORWF16(Processor *new_cpu, uint new_opcode, uint address)
: IORWF(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new IORWF16(new_cpu,new_opcode,address);}
};
class LCALL16 : public multi_word_branch
{
public:
bool fast;
LCALL16(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new LCALL16(new_cpu,new_opcode,address);}
virtual char *name(char *,int);
};
class LFSR : public multi_word_instruction
{
public:
uint fsr,k;
Indirect_Addressing *ia;
LFSR(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
virtual char *name(char *,int);
void runtime_initialize();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new LFSR(new_cpu,new_opcode,address);}
};
class MOVF16 : public MOVF
{
public:
MOVF16(Processor *new_cpu, uint new_opcode, uint address)
: MOVF(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new MOVF16(new_cpu,new_opcode,address);}
};
class MOVFF : public multi_word_instruction
{
public:
uint source,destination;
MOVFF(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
virtual char *name(char *,int);
void runtime_initialize();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new MOVFF(new_cpu,new_opcode,address);}
};
class MOVFP : public multi_word_instruction
{
public:
uint source,destination;
MOVFP(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
virtual char *name(char *,int);
void runtime_initialize();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new MOVFP(new_cpu,new_opcode,address);}
};
class MOVLB16 : public Literal_op
{
public:
MOVLB16(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new MOVLB16(new_cpu,new_opcode,address);}
};
class MOVLR : public Literal_op
{
public:
MOVLR(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new MOVLR(new_cpu,new_opcode,address);}
};
class MOVPF : public multi_word_instruction
{
public:
uint source,destination;
MOVPF(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
virtual char *name(char *,int);
void runtime_initialize();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new MOVPF(new_cpu,new_opcode,address);}
};
class MOVWF16 : public MOVWF
{
public:
MOVWF16(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new MOVWF16(new_cpu,new_opcode,address);}
};
class MULLW : public Literal_op
{
public:
MULLW(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new MULLW(new_cpu,new_opcode,address);}
};
class MULWF : public Register_op
{
public:
MULWF(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new MULWF(new_cpu,new_opcode,address);}
};
class NEGF : public Register_op
{
public:
NEGF(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new NEGF(new_cpu,new_opcode,address);}
};
class NEGW : public Register_op
{
public:
NEGW(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new NEGW(new_cpu,new_opcode,address);}
};
class POP : public Instruction
{
public:
POP(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
virtual bool isBase() { return true;}
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new POP(new_cpu,new_opcode,address);}
};
class PUSH : public Instruction
{
public:
PUSH(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
virtual bool isBase() { return true;}
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new PUSH(new_cpu,new_opcode,address);}
};
class RCALL : public Instruction
{
public:
int destination_index;
uint absolute_destination_index;
RCALL(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
virtual char *name(char *,int);
virtual bool isBase() { return true;}
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new RCALL(new_cpu,new_opcode,address);}
};
class RETFIE16 : public RETFIE
{
public:
bool fast;
RETFIE16(Processor *new_cpu, uint new_opcode, uint address) :
RETFIE(new_cpu,new_opcode,address)
{
fast = (new_opcode & 1);
};
virtual void execute();
virtual char *name(char *,int);
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new RETFIE16(new_cpu,new_opcode,address);}
};
class RETURN16 : public RETURN
{
public:
bool fast;
RETURN16(Processor *new_cpu, uint new_opcode, uint address) :
RETURN(new_cpu,new_opcode,address)
{ fast = (new_opcode & 1); }
virtual void execute();
virtual char *name(char *,int);
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new RETURN16(new_cpu,new_opcode,address);}
};
class RLCF : public Register_op
{
public:
RLCF(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new RLCF(new_cpu,new_opcode,address);}
};
class RLNCF : public Register_op
{
public:
RLNCF(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new RLNCF(new_cpu,new_opcode,address);}
};
class RRCF : public Register_op
{
public:
RRCF(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new RRCF(new_cpu,new_opcode,address);}
};
class RRNCF : public Register_op
{
public:
RRNCF(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new RRNCF(new_cpu,new_opcode,address);}
};
class SETF : public Register_op
{
public:
SETF(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new SETF(new_cpu,new_opcode,address);}
};
class SLEEP16 : public SLEEP
{
public:
SLEEP16(Processor *new_cpu, uint new_opcode, uint address) :
SLEEP(new_cpu,new_opcode,address) { }
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new SLEEP16(new_cpu,new_opcode,address);}
};
class SUBFWB : public Register_op
{
public:
SUBFWB(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new SUBFWB(new_cpu,new_opcode,address);}
};
class SUBLW16 : public SUBLW
{
public:
SUBLW16(Processor *new_cpu, uint new_opcode, uint address) :
SUBLW(new_cpu,new_opcode,address) { }
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new SUBLW16(new_cpu,new_opcode,address);}
};
class SUBWF16 : public SUBWF
{
public:
SUBWF16(Processor *new_cpu, uint new_opcode, uint address) :
SUBWF(new_cpu,new_opcode,address) { }
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new SUBWF16(new_cpu,new_opcode,address);}
};
class SUBWFB16 : public SUBWFB
{
public:
SUBWFB16(Processor *new_cpu, uint new_opcode, uint address) :
SUBWFB(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new SUBWFB16(new_cpu,new_opcode,address);}
};
class SWAPF16 : public SWAPF
{
public:
SWAPF16(Processor *new_cpu, uint new_opcode, uint address) :
SWAPF(new_cpu,new_opcode,address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new SWAPF16(new_cpu,new_opcode,address);}
};
class TBLRD : public Instruction
{
public:
TBLRD(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
virtual char *name(char *,int);
virtual bool isBase() { return true;}
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new TBLRD(new_cpu,new_opcode,address);}
};
class TBLWT : public Instruction
{
public:
TBLWT(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
virtual char *name(char *,int);
virtual bool isBase() { return true;}
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new TBLWT(new_cpu,new_opcode,address);}
};
class TLRD : public Instruction
{
public:
TLRD(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
virtual char *name(char *,int);
virtual bool isBase() { return true;}
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new TLRD(new_cpu,new_opcode,address);}
};
class TLWT : public Instruction
{
public:
TLWT(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
virtual char *name(char *,int);
virtual bool isBase() { return true;}
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new TLWT(new_cpu,new_opcode,address);}
};
class TSTFSZ : public Register_op
{
public:
TSTFSZ(Processor *new_cpu, uint new_opcode, uint address);
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new TSTFSZ(new_cpu,new_opcode,address);}
};
class XORLW16 : public XORLW
{
public:
XORLW16(Processor *new_cpu, uint new_opcode, uint address) :
XORLW(new_cpu, new_opcode, address){}
virtual void execute();
static Instruction *construct(Processor *new_cpu, uint new_opcode, uint address)
{return new XORLW16(new_cpu,new_opcode,address);}
};
class XORWF16 : public XORWF
{
public:
XORWF16(Processor *new_cpu, uint new_opcode, uint address)
: XORWF(new_cpu,new_opcode, address){}
virtual void execute();
static Instruction *construct( Processor *new_cpu, uint new_opcode, uint address )
{ return new XORWF16(new_cpu,new_opcode,address); }
};
#endif /* __12BIT_INSTRUCTIONS_H__ */
|