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* Copyright (c) 2013 Beniamino Galvani
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef KERN_or32_ASM_H_
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#define KERN_or32_ASM_H_
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#define SR_INT_MASK (SPR_SR_IEE | SPR_SR_TEE)
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NO_TRACE static inline void asm_delay_loop(uint32_t usec)
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NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
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/* On real hardware this should stop processing further
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instructions on the CPU (and possibly putting it into
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low-power mode) without any possibility of exitting
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NO_TRACE static inline void cpu_sleep(void)
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/* On real hardware this should put the CPU into low-power
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mode. However, the CPU is free to continue processing
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futher instructions any time. The CPU also wakes up
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NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
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* @param port Port to write to
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* @param val Value to write
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NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
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/** Double word to port
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* Output double word to port
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* @param port Port to write to
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* @param val Value to write
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NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
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* @param port Port to read from
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NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
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* @param port Port to read from
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NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
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/** Double word from port
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* Get double word from port
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* @param port Port to read from
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NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
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NO_TRACE static inline ipl_t interrupts_enable(void)
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ipl_t ipl = (ipl_t) spr_sr_read();
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spr_sr_write(ipl | SR_INT_MASK);
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NO_TRACE static inline ipl_t interrupts_disable(void)
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ipl_t ipl = (ipl_t) spr_sr_read();
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spr_sr_write(ipl & ~SR_INT_MASK);
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NO_TRACE static inline void interrupts_restore(ipl_t ipl)
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spr_sr_write((spr_sr_read() & ~SR_INT_MASK) | (ipl & SR_INT_MASK));
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NO_TRACE static inline ipl_t interrupts_read(void)
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return spr_sr_read();
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NO_TRACE static inline bool interrupts_disabled(void)
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return !(spr_sr_read() & SR_INT_MASK);
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NO_TRACE static inline uintptr_t get_stack_base(void)
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"l.and %[base], r1, %[mask]\n"
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: [mask] "r" (~(STACK_SIZE - 1))