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; * Copyright (C) 2011 - Neil Kettle <neil@digit-labs.org>
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; * This file is part of cpuminer-ng.
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; * cpuminer-ng is free software: you can redistribute it and/or modify
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; * it under the terms of the GNU General Public License as published by
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; * the Free Software Foundation, either version 3 of the License, or
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; * (at your option) any later version.
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; * cpuminer-ng is distributed in the hope that it will be useful,
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; * but WITHOUT ANY WARRANTY; without even the implied warranty of
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; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; * GNU General Public License for more details.
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; * You should have received a copy of the GNU General Public License
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; * along with cpuminer-ng. If not, see <http://www.gnu.org/licenses/>.
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; %rbp, %rbx, and %r12-%r15 - callee save
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; 0 = (1024 - 256) (mod (LAB_CALC_UNROLL*LAB_CALC_PARA*16))
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%define SHA_CALC_W_PARA 2
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%define SHA_CALC_W_UNROLL 8
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%define SHA_ROUND_LOOP_UNROLL 16
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%ifidn __YASM_OBJFMT__, macho64
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extern _sha256_consts_m128i
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extern sha256_consts_m128i
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%ifidn __YASM_OBJFMT__, macho64
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global _sha256_sse2_64_new
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global sha256_sse2_64_new
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%macro sha_round_blk 0
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movdqa sr1, [data+rax] ; T1 = w;
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movdqa sr2, rE ; sr2 = rE
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pandn sr2, rG ; sr2 = ~rE & rG
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movdqa sr3, rF ; sr3 = rF
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paddd sr1, rH ; T1 = h + sha256_consts_m128i[i] + w;
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movdqa rH, rG ; rH = rG
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pand sr3, rE ; sr3 = rE & rF
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movdqa rG, rF ; rG = rF
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%ifidn __YASM_OBJFMT__, macho64
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paddd sr1, sha256_consts_m128i[rax] ; T1 = sha256_consts_m128i[i] + w;
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pxor sr2, sr3 ; sr2 = (rE & rF) ^ (~rE & rG) = Ch (e, f, g)
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movdqa rF, rE ; rF = rE
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paddd sr1, sr2 ; T1 = h + Ch (e, f, g) + sha256_consts_m128i[i] + w;
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movdqa sr2, rE ; sr2 = rE
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movdqa sr3, rE ; e >> 6
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psrld sr3, 5 ; e >> 11
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pxor rE, sr2 ; e >> 6 ^ e << 7
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pslld sr2, 14 ; e << 21
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pxor rE, sr3 ; e >> 6 ^ e << 7 ^ e >> 11
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psrld sr3, 14 ; e >> 25
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pxor rE, sr2 ; e >> 6 ^ e << 7 ^ e >> 11 ^ e << 21
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pslld sr2, 5 ; e << 26
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pxor rE, sr3 ; e >> 6 ^ e << 7 ^ e >> 11 ^ e << 21 ^ e >> 25
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pxor rE, sr2 ; e >> 6 ^ e << 7 ^ e >> 11 ^ e << 21 ^ e >> 25 ^ e << 26
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movdqa sr2, rB ; sr2 = rB
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paddd sr1, rE ; sr1 = h + BIGSIGMA1_256(e) + Ch (e, f, g) + sha256_consts_m128i[i] + w;
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movdqa rE, rD ; rE = rD
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movdqa rD, rC ; rD = rC
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paddd rE, sr1 ; rE = rD + T1
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movdqa sr3, rC ; sr3 = rC
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pand rC, rA ; rC = rC & rA
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pand sr3, rB ; sr3 = rB & rC
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pand sr2, rA ; sr2 = rB & rA
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pxor sr2, rC ; sr2 = (rB & rA) ^ (rC & rA)
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movdqa rC, rB ; rC = rB
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pxor sr2, sr3 ; sr2 = (rB & rA) ^ (rC & rA) ^ (rB & rC)
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movdqa rB, rA ; rB = rA
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paddd sr1, sr2 ; sr1 = T1 + (rB & rA) ^ (rC & rA) ^ (rB & rC)
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movdqa sr3, rA ; sr3 = rA
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pslld sr3, 10 ; a << 10
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movdqa sr2, rA ; a >> 2
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pxor rA, sr3 ; a >> 2 ^ a << 10
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psrld sr2, 11 ; a >> 13
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pxor rA, sr2 ; a >> 2 ^ a << 10 ^ a >> 13
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pslld sr3, 9 ; a << 19
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pxor rA, sr3 ; a >> 2 ^ a << 10 ^ a >> 13 ^ a << 19
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psrld sr2, 9 ; a >> 21
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pxor rA, sr2 ; a >> 2 ^ a << 10 ^ a >> 13 ^ a << 19 ^ a >> 21
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pslld sr3, 11 ; a << 30
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pxor rA, sr3 ; a >> 2 ^ a << 10 ^ a >> 13 ^ a << 19 ^ a >> 21 ^ a << 30
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paddd rA, sr1 ; T1 + BIGSIGMA0_256(a) + Maj(a, b, c);
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%macro sha_calc_w_blk 1
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movdqa xmm0, [r11-(15-%1)*16] ; xmm0 = W[I-15]
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movdqa xmm4, [r11-(15-(%1+1))*16] ; xmm4 = W[I-15+1]
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movdqa xmm2, xmm0 ; xmm2 = W[I-15]
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movdqa xmm6, xmm4 ; xmm6 = W[I-15+1]
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psrld xmm0, 3 ; xmm0 = W[I-15] >> 3
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psrld xmm4, 3 ; xmm4 = W[I-15+1] >> 3
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movdqa xmm1, xmm0 ; xmm1 = W[I-15] >> 3
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movdqa xmm5, xmm4 ; xmm5 = W[I-15+1] >> 3
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pslld xmm2, 14 ; xmm2 = W[I-15] << 14
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pslld xmm6, 14 ; xmm6 = W[I-15+1] << 14
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psrld xmm1, 4 ; xmm1 = W[I-15] >> 7
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psrld xmm5, 4 ; xmm5 = W[I-15+1] >> 7
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pxor xmm0, xmm1 ; xmm0 = (W[I-15] >> 3) ^ (W[I-15] >> 7)
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pxor xmm4, xmm5 ; xmm4 = (W[I-15+1] >> 3) ^ (W[I-15+1] >> 7)
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psrld xmm1, 11 ; xmm1 = W[I-15] >> 18
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psrld xmm5, 11 ; xmm5 = W[I-15+1] >> 18
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pxor xmm0, xmm2 ; xmm0 = (W[I-15] >> 3) ^ (W[I-15] >> 7) ^ (W[I-15] << 14)
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pxor xmm4, xmm6 ; xmm4 = (W[I-15+1] >> 3) ^ (W[I-15+1] >> 7) ^ (W[I-15+1] << 14)
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pslld xmm2, 11 ; xmm2 = W[I-15] << 25
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pslld xmm6, 11 ; xmm6 = W[I-15+1] << 25
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pxor xmm0, xmm1 ; xmm0 = (W[I-15] >> 3) ^ (W[I-15] >> 7) ^ (W[I-15] << 14) ^ (W[I-15] >> 18)
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pxor xmm4, xmm5 ; xmm4 = (W[I-15+1] >> 3) ^ (W[I-15+1] >> 7) ^ (W[I-15+1] << 14) ^ (W[I-15+1] >> 18)
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pxor xmm0, xmm2 ; xmm0 = (W[I-15] >> 3) ^ (W[I-15] >> 7) ^ (W[I-15] << 14) ^ (W[I-15] >> 18) ^ (W[I-15] << 25)
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pxor xmm4, xmm6 ; xmm4 = (W[I-15+1] >> 3) ^ (W[I-15+1] >> 7) ^ (W[I-15+1] << 14) ^ (W[I-15+1] >> 18) ^ (W[I-15+1] << 25)
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movdqa xmm3, [r11-(2-%1)*16] ; xmm3 = W[I-2]
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movdqa xmm7, [r11-(2-(%1+1))*16] ; xmm7 = W[I-2+1]
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paddd xmm0, [r11-(16-%1)*16] ; xmm0 = s0(W[I-15]) + W[I-16]
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paddd xmm4, [r11-(16-(%1+1))*16] ; xmm4 = s0(W[I-15+1]) + W[I-16+1]
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movdqa xmm2, xmm3 ; xmm2 = W[I-2]
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movdqa xmm6, xmm7 ; xmm6 = W[I-2+1]
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psrld xmm3, 10 ; xmm3 = W[I-2] >> 10
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psrld xmm7, 10 ; xmm7 = W[I-2+1] >> 10
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movdqa xmm1, xmm3 ; xmm1 = W[I-2] >> 10
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movdqa xmm5, xmm7 ; xmm5 = W[I-2+1] >> 10
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paddd xmm0, [r11-(7-%1)*16] ; xmm0 = s0(W[I-15]) + W[I-16] + W[I-7]
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pslld xmm2, 13 ; xmm2 = W[I-2] << 13
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pslld xmm6, 13 ; xmm6 = W[I-2+1] << 13
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psrld xmm1, 7 ; xmm1 = W[I-2] >> 17
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psrld xmm5, 7 ; xmm5 = W[I-2+1] >> 17
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paddd xmm4, [r11-(7-(%1+1))*16] ; xmm4 = s0(W[I-15+1]) + W[I-16+1] + W[I-7+1]
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pxor xmm3, xmm1 ; xmm3 = (W[I-2] >> 10) ^ (W[I-2] >> 17)
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pxor xmm7, xmm5 ; xmm7 = (W[I-2+1] >> 10) ^ (W[I-2+1] >> 17)
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psrld xmm1, 2 ; xmm1 = W[I-2] >> 19
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psrld xmm5, 2 ; xmm5 = W[I-2+1] >> 19
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pxor xmm3, xmm2 ; xmm3 = (W[I-2] >> 10) ^ (W[I-2] >> 17) ^ (W[I-2] << 13)
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pxor xmm7, xmm6 ; xmm7 = (W[I-2+1] >> 10) ^ (W[I-2+1] >> 17) ^ (W[I-2+1] << 13)
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pslld xmm2, 2 ; xmm2 = W[I-2] << 15
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pslld xmm6, 2 ; xmm6 = W[I-2+1] << 15
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pxor xmm3, xmm1 ; xmm3 = (W[I-2] >> 10) ^ (W[I-2] >> 17) ^ (W[I-2] << 13) ^ (W[I-2] >> 19)
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pxor xmm7, xmm5 ; xmm7 = (W[I-2+1] >> 10) ^ (W[I-2+1] >> 17) ^ (W[I-2+1] << 13) ^ (W[I-2+1] >> 19)
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pxor xmm3, xmm2 ; xmm3 = (W[I-2] >> 10) ^ (W[I-2] >> 17) ^ (W[I-2] << 13) ^ (W[I-2] >> 19) ^ (W[I-2] << 15)
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pxor xmm7, xmm6 ; xmm7 = (W[I-2+1] >> 10) ^ (W[I-2+1] >> 17) ^ (W[I-2+1] << 13) ^ (W[I-2+1] >> 19) ^ (W[I-2+1] << 15)
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paddd xmm0, xmm3 ; xmm0 = s0(W[I-15]) + W[I-16] + s1(W[I-2]) + W[I-7]
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paddd xmm4, xmm7 ; xmm4 = s0(W[I-15+1]) + W[I-16+1] + s1(W[I-2+1]) + W[I-7+1]
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movdqa [r11+(%1*16)], xmm0
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movdqa [r11+((%1+1)*16)], xmm4
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; _sha256_sse2_64_new hash(rdi), hash1(rsi), data(rdx), init(rcx),
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%ifidn __YASM_OBJFMT__, macho64
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mov rbx, 64*4 ; rbx is # of SHA-2 rounds
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mov rax, 16*4 ; rax is where we expand to
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lea rbx, qword [data+rbx*4]
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lea r11, qword [data+rax*4]
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%rep SHA_CALC_W_UNROLL
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%assign i i+SHA_CALC_W_PARA
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add r11, SHA_CALC_W_UNROLL*SHA_CALC_W_PARA*16
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pshufd rB, rA, 0x55 ; rB == B
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pshufd rC, rA, 0xAA ; rC == C
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pshufd rD, rA, 0xFF ; rD == D
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pshufd rA, rA, 0 ; rA == A
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movdqa rE, [init+4*4]
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pshufd rF, rE, 0x55 ; rF == F
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pshufd rG, rE, 0xAA ; rG == G
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pshufd rH, rE, 0xFF ; rH == H
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pshufd rE, rE, 0 ; rE == E
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%ifidn __YASM_OBJFMT__, macho64
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lea rcx, [_sha256_consts_m128i wrt rip]
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%rep SHA_ROUND_LOOP_UNROLL
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; Finished the 64 rounds, calculate hash and save
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pshufd sr2, sr1, 0x55
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pshufd sr3, sr1, 0xAA
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pshufd sr4, sr1, 0xFF
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movdqa sr1, [init+4*4]
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pshufd sr2, sr1, 0x55
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pshufd sr3, sr1, 0xAA
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pshufd sr4, sr1, 0xFF
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movdqa [hash1+0*16], rA
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movdqa [hash1+1*16], rB
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movdqa [hash1+2*16], rC
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movdqa [hash1+3*16], rD
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movdqa [hash1+4*16], rE
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movdqa [hash1+5*16], rF
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movdqa [hash1+6*16], rG
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movdqa [hash1+7*16], rH
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mov init, sha256_init
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movdqa [hash+7*16], rH
added
removed
x86_64/sha256_xmm_amd64.asm
