2
* TPR optimization for 32-bit Windows guests (XP and Server 2003)
4
* Copyright (C) 2007-2008 Qumranet Technologies
5
* Copyright (C) 2012 Jan Kiszka, Siemens AG
7
* This work is licensed under the terms of the GNU GPL version 2, or
8
* (at your option) any later version. See the COPYING file in the
14
#include "apic_internal.h"
16
#define APIC_DEFAULT_ADDRESS 0xfee00000
18
#define VAPIC_IO_PORT 0x7e
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#define VAPIC_CPU_SHIFT 7
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#define ROM_BLOCK_SIZE 512
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#define ROM_BLOCK_MASK (~(ROM_BLOCK_SIZE - 1))
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typedef enum VAPICMode {
31
typedef struct VAPICHandlers {
35
uint32_t get_tpr_stack;
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} QEMU_PACKED VAPICHandlers;
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typedef struct GuestROMState {
46
uint32_t real_tpr_addr;
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} QEMU_PACKED GuestROMState;
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typedef struct VAPICROMState {
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uint32_t rom_state_paddr;
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uint32_t rom_state_vaddr;
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uint32_t real_tpr_addr;
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GuestROMState rom_state;
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bool rom_mapped_writable;
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#define TPR_INSTR_ABS_MODRM 0x1
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#define TPR_INSTR_MATCH_MODRM_REG 0x2
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typedef struct TPRInstruction {
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/* must be sorted by length, shortest first */
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static const TPRInstruction tpr_instr[] = {
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{ /* mov abs to eax */
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.access = TPR_ACCESS_READ,
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{ /* mov eax to abs */
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.access = TPR_ACCESS_WRITE,
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{ /* mov r32 to r/m32 */
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.flags = TPR_INSTR_ABS_MODRM,
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.access = TPR_ACCESS_WRITE,
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{ /* mov r/m32 to r32 */
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.flags = TPR_INSTR_ABS_MODRM,
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.access = TPR_ACCESS_READ,
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.flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG,
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.access = TPR_ACCESS_READ,
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{ /* mov imm32, r/m32 (c7/0) */
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.flags = TPR_INSTR_ABS_MODRM | TPR_INSTR_MATCH_MODRM_REG,
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.access = TPR_ACCESS_WRITE,
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static void read_guest_rom_state(VAPICROMState *s)
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cpu_physical_memory_rw(s->rom_state_paddr, (void *)&s->rom_state,
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sizeof(GuestROMState), 0);
129
static void write_guest_rom_state(VAPICROMState *s)
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cpu_physical_memory_rw(s->rom_state_paddr, (void *)&s->rom_state,
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sizeof(GuestROMState), 1);
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static void update_guest_rom_state(VAPICROMState *s)
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read_guest_rom_state(s);
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s->rom_state.real_tpr_addr = cpu_to_le32(s->real_tpr_addr);
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s->rom_state.vcpu_shift = cpu_to_le32(VAPIC_CPU_SHIFT);
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write_guest_rom_state(s);
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static int find_real_tpr_addr(VAPICROMState *s, CPUState *env)
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target_phys_addr_t paddr;
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if (s->state == VAPIC_ACTIVE) {
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* If there is no prior TPR access instruction we could analyze (which is
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* the case after resume from hibernation), we need to scan the possible
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* virtual address space for the APIC mapping.
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for (addr = 0xfffff000; addr >= 0x80000000; addr -= TARGET_PAGE_SIZE) {
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paddr = cpu_get_phys_page_debug(env, addr);
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if (paddr != APIC_DEFAULT_ADDRESS) {
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s->real_tpr_addr = addr + 0x80;
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update_guest_rom_state(s);
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static uint8_t modrm_reg(uint8_t modrm)
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return (modrm >> 3) & 7;
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static bool is_abs_modrm(uint8_t modrm)
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return (modrm & 0xc7) == 0x05;
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static bool opcode_matches(uint8_t *opcode, const TPRInstruction *instr)
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return opcode[0] == instr->opcode &&
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(!(instr->flags & TPR_INSTR_ABS_MODRM) || is_abs_modrm(opcode[1])) &&
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(!(instr->flags & TPR_INSTR_MATCH_MODRM_REG) ||
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modrm_reg(opcode[1]) == instr->modrm_reg);
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static int evaluate_tpr_instruction(VAPICROMState *s, CPUState *env,
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target_ulong *pip, TPRAccess access)
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const TPRInstruction *instr;
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target_ulong ip = *pip;
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uint32_t real_tpr_addr;
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if ((ip & 0xf0000000ULL) != 0x80000000ULL &&
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(ip & 0xf0000000ULL) != 0xe0000000ULL) {
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* Early Windows 2003 SMP initialization contains a
207
* instruction that is patched by TPR optimization. The problem is that
208
* RSP, used by the patched instruction, is zero, so the guest gets a
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* double fault and dies.
211
if (env->regs[R_ESP] == 0) {
215
if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
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* KVM without kernel-based TPR access reporting will pass an IP that
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* points after the accessing instruction. So we need to look backward
219
* to find the reason.
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for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
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instr = &tpr_instr[i];
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if (instr->access != access) {
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if (cpu_memory_rw_debug(env, ip - instr->length, opcode,
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sizeof(opcode), 0) < 0) {
230
if (opcode_matches(opcode, instr)) {
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if (cpu_memory_rw_debug(env, ip, opcode, sizeof(opcode), 0) < 0) {
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for (i = 0; i < ARRAY_SIZE(tpr_instr); i++) {
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instr = &tpr_instr[i];
242
if (opcode_matches(opcode, instr)) {
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* Grab the virtual TPR address from the instruction
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* and update the cached values.
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if (cpu_memory_rw_debug(env, ip + instr->addr_offset,
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(void *)&real_tpr_addr,
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sizeof(real_tpr_addr), 0) < 0) {
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real_tpr_addr = le32_to_cpu(real_tpr_addr);
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if ((real_tpr_addr & 0xfff) != 0x80) {
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s->real_tpr_addr = real_tpr_addr;
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update_guest_rom_state(s);
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static int update_rom_mapping(VAPICROMState *s, CPUState *env, target_ulong ip)
272
target_phys_addr_t paddr;
273
uint32_t rom_state_vaddr;
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uint32_t pos, patch, offset;
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/* nothing to do if already activated */
277
if (s->state == VAPIC_ACTIVE) {
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/* bail out if ROM init code was not executed (missing ROM?) */
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if (s->state == VAPIC_INACTIVE) {
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/* find out virtual address of the ROM */
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rom_state_vaddr = s->rom_state_paddr + (ip & 0xf0000000);
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paddr = cpu_get_phys_page_debug(env, rom_state_vaddr);
292
paddr += rom_state_vaddr & ~TARGET_PAGE_MASK;
293
if (paddr != s->rom_state_paddr) {
296
read_guest_rom_state(s);
297
if (memcmp(s->rom_state.signature, "kvm aPiC", 8) != 0) {
300
s->rom_state_vaddr = rom_state_vaddr;
302
/* fixup addresses in ROM if needed */
303
if (rom_state_vaddr == le32_to_cpu(s->rom_state.vaddr)) {
306
for (pos = le32_to_cpu(s->rom_state.fixup_start);
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pos < le32_to_cpu(s->rom_state.fixup_end);
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cpu_physical_memory_rw(paddr + pos - s->rom_state.vaddr,
310
(void *)&offset, sizeof(offset), 0);
311
offset = le32_to_cpu(offset);
312
cpu_physical_memory_rw(paddr + offset, (void *)&patch,
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patch = le32_to_cpu(patch);
315
patch += rom_state_vaddr - le32_to_cpu(s->rom_state.vaddr);
316
patch = cpu_to_le32(patch);
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cpu_physical_memory_rw(paddr + offset, (void *)&patch,
320
read_guest_rom_state(s);
321
s->vapic_paddr = paddr + le32_to_cpu(s->rom_state.vapic_vaddr) -
322
le32_to_cpu(s->rom_state.vaddr);
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* Tries to read the unique processor number from the Kernel Processor Control
329
* Region (KPCR) of 32-bit Windows XP and Server 2003. Returns -1 if the KPCR
330
* cannot be accessed or is considered invalid. This also ensures that we are
331
* not patching the wrong guest.
333
static int get_kpcr_number(CPUState *env)
342
if (cpu_memory_rw_debug(env, env->segs[R_FS].base,
343
(void *)&kpcr, sizeof(kpcr), 0) < 0 ||
344
kpcr.self != env->segs[R_FS].base) {
350
static int vapic_enable(VAPICROMState *s, CPUState *env)
352
int cpu_number = get_kpcr_number(env);
353
target_phys_addr_t vapic_paddr;
354
static const uint8_t enabled = 1;
356
if (cpu_number < 0) {
359
vapic_paddr = s->vapic_paddr +
360
(((target_phys_addr_t)cpu_number) << VAPIC_CPU_SHIFT);
361
cpu_physical_memory_rw(vapic_paddr + offsetof(VAPICState, enabled),
362
(void *)&enabled, sizeof(enabled), 1);
363
apic_enable_vapic(env->apic_state, vapic_paddr);
365
s->state = VAPIC_ACTIVE;
370
static void patch_byte(CPUState *env, target_ulong addr, uint8_t byte)
372
cpu_memory_rw_debug(env, addr, &byte, 1, 1);
375
static void patch_call(VAPICROMState *s, CPUState *env, target_ulong ip,
380
offset = cpu_to_le32(target - ip - 5);
381
patch_byte(env, ip, 0xe8); /* call near */
382
cpu_memory_rw_debug(env, ip + 1, (void *)&offset, sizeof(offset), 1);
385
static void patch_instruction(VAPICROMState *s, CPUState *env, target_ulong ip)
387
target_phys_addr_t paddr;
388
VAPICHandlers *handlers;
393
handlers = &s->rom_state.up;
395
handlers = &s->rom_state.mp;
400
cpu_memory_rw_debug(env, ip, opcode, sizeof(opcode), 0);
403
case 0x89: /* mov r32 to r/m32 */
404
patch_byte(env, ip, 0x50 + modrm_reg(opcode[1])); /* push reg */
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patch_call(s, env, ip + 1, handlers->set_tpr);
407
case 0x8b: /* mov r/m32 to r32 */
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patch_byte(env, ip, 0x90);
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patch_call(s, env, ip + 1, handlers->get_tpr[modrm_reg(opcode[1])]);
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case 0xa1: /* mov abs to eax */
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patch_call(s, env, ip, handlers->get_tpr[0]);
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case 0xa3: /* mov eax to abs */
415
patch_call(s, env, ip, handlers->set_tpr_eax);
417
case 0xc7: /* mov imm32, r/m32 (c7/0) */
418
patch_byte(env, ip, 0x68); /* push imm32 */
419
cpu_memory_rw_debug(env, ip + 6, (void *)&imm32, sizeof(imm32), 0);
420
cpu_memory_rw_debug(env, ip + 1, (void *)&imm32, sizeof(imm32), 1);
421
patch_call(s, env, ip + 5, handlers->set_tpr);
423
case 0xff: /* push r/m32 */
424
patch_byte(env, ip, 0x50); /* push eax */
425
patch_call(s, env, ip + 1, handlers->get_tpr_stack);
433
paddr = cpu_get_phys_page_debug(env, ip);
434
paddr += ip & ~TARGET_PAGE_MASK;
435
tb_invalidate_phys_page_range(paddr, paddr + 1, 1);
438
void vapic_report_tpr_access(DeviceState *dev, void *cpu, target_ulong ip,
441
VAPICROMState *s = DO_UPCAST(VAPICROMState, busdev.qdev, dev);
444
cpu_synchronize_state(env);
446
if (evaluate_tpr_instruction(s, env, &ip, access) < 0) {
447
if (s->state == VAPIC_ACTIVE) {
448
vapic_enable(s, env);
452
if (update_rom_mapping(s, env, ip) < 0) {
455
if (vapic_enable(s, env) < 0) {
458
patch_instruction(s, env, ip);
461
typedef struct VAPICEnableTPRReporting {
464
} VAPICEnableTPRReporting;
466
static void vapic_do_enable_tpr_reporting(void *data)
468
VAPICEnableTPRReporting *info = data;
470
apic_enable_tpr_access_reporting(info->apic, info->enable);
473
static void vapic_enable_tpr_reporting(bool enable)
475
VAPICEnableTPRReporting info = {
480
for (env = first_cpu; env != NULL; env = env->next_cpu) {
481
info.apic = env->apic_state;
482
run_on_cpu(env, vapic_do_enable_tpr_reporting, &info);
486
static void vapic_reset(DeviceState *dev)
488
VAPICROMState *s = DO_UPCAST(VAPICROMState, busdev.qdev, dev);
490
if (s->state == VAPIC_ACTIVE) {
491
s->state = VAPIC_STANDBY;
493
vapic_enable_tpr_reporting(false);
497
* Set the IRQ polling hypercalls to the supported variant:
498
* - vmcall if using KVM in-kernel irqchip
499
* - 32-bit VAPIC port write otherwise
501
static int patch_hypercalls(VAPICROMState *s)
503
target_phys_addr_t rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
504
static const uint8_t vmcall_pattern[] = { /* vmcall */
505
0xb8, 0x1, 0, 0, 0, 0xf, 0x1, 0xc1
507
static const uint8_t outl_pattern[] = { /* nop; outl %eax,0x7e */
508
0xb8, 0x1, 0, 0, 0, 0x90, 0xe7, 0x7e
510
uint8_t alternates[2];
511
const uint8_t *pattern;
512
const uint8_t *patch;
517
rom = g_malloc(s->rom_size);
518
cpu_physical_memory_rw(rom_paddr, rom, s->rom_size, 0);
520
for (pos = 0; pos < s->rom_size - sizeof(vmcall_pattern); pos++) {
521
if (kvm_irqchip_in_kernel()) {
522
pattern = outl_pattern;
523
alternates[0] = outl_pattern[7];
524
alternates[1] = outl_pattern[7];
525
patch = &vmcall_pattern[5];
527
pattern = vmcall_pattern;
528
alternates[0] = vmcall_pattern[7];
529
alternates[1] = 0xd9; /* AMD's VMMCALL */
530
patch = &outl_pattern[5];
532
if (memcmp(rom + pos, pattern, 7) == 0 &&
533
(rom[pos + 7] == alternates[0] || rom[pos + 7] == alternates[1])) {
534
cpu_physical_memory_rw(rom_paddr + pos + 5, (uint8_t *)patch,
537
* Don't flush the tb here. Under ordinary conditions, the patched
538
* calls are miles away from the current IP. Under malicious
539
* conditions, the guest could trick us to crash.
546
if (patches != 0 && patches != 2) {
554
* For TCG mode or the time KVM honors read-only memory regions, we need to
555
* enable write access to the option ROM so that variables can be updated by
558
static void vapic_map_rom_writable(VAPICROMState *s)
560
target_phys_addr_t rom_paddr = s->rom_state_paddr & ROM_BLOCK_MASK;
561
MemoryRegionSection section;
566
as = sysbus_address_space(&s->busdev);
568
if (s->rom_mapped_writable) {
569
memory_region_del_subregion(as, &s->rom);
570
memory_region_destroy(&s->rom);
573
/* grab RAM memory region (region @rom_paddr may still be pc.rom) */
574
section = memory_region_find(as, 0, 1);
576
/* read ROM size from RAM region */
577
ram = memory_region_get_ram_ptr(section.mr);
578
rom_size = ram[rom_paddr + 2] * ROM_BLOCK_SIZE;
579
s->rom_size = rom_size;
581
/* We need to round up to avoid creating subpages
582
* from which we cannot run code. */
583
rom_size = TARGET_PAGE_ALIGN(rom_size);
585
memory_region_init_alias(&s->rom, "kvmvapic-rom", section.mr, rom_paddr,
587
memory_region_add_subregion_overlap(as, rom_paddr, &s->rom, 1000);
588
s->rom_mapped_writable = true;
591
static int vapic_prepare(VAPICROMState *s)
593
vapic_map_rom_writable(s);
595
if (patch_hypercalls(s) < 0) {
599
vapic_enable_tpr_reporting(true);
604
static void vapic_write(void *opaque, target_phys_addr_t addr, uint64_t data,
607
CPUState *env = cpu_single_env;
608
target_phys_addr_t rom_paddr;
609
VAPICROMState *s = opaque;
611
cpu_synchronize_state(env);
614
* The VAPIC supports two PIO-based hypercalls, both via port 0x7E.
615
* o 16-bit write access:
616
* Reports the option ROM initialization to the hypervisor. Written
617
* value is the offset of the state structure in the ROM.
618
* o 8-bit write access:
619
* Reactivates the VAPIC after a guest hibernation, i.e. after the
620
* option ROM content has been re-initialized by a guest power cycle.
621
* o 32-bit write access:
622
* Poll for pending IRQs, considering the current VAPIC state.
626
if (s->state == VAPIC_INACTIVE) {
627
rom_paddr = (env->segs[R_CS].base + env->eip) & ROM_BLOCK_MASK;
628
s->rom_state_paddr = rom_paddr + data;
630
s->state = VAPIC_STANDBY;
632
if (vapic_prepare(s) < 0) {
633
s->state = VAPIC_INACTIVE;
640
* Disable triggering instruction in ROM by writing a NOP.
642
* We cannot do this in TCG mode as the reported IP is not
646
patch_byte(env, env->eip - 2, 0x66);
647
patch_byte(env, env->eip - 1, 0x90);
651
if (s->state == VAPIC_ACTIVE) {
654
if (update_rom_mapping(s, env, env->eip) < 0) {
657
if (find_real_tpr_addr(s, env) < 0) {
660
vapic_enable(s, env);
664
if (!kvm_irqchip_in_kernel()) {
665
apic_poll_irq(env->apic_state);
671
static const MemoryRegionOps vapic_ops = {
672
.write = vapic_write,
673
.endianness = DEVICE_NATIVE_ENDIAN,
676
static int vapic_init(SysBusDevice *dev)
678
VAPICROMState *s = FROM_SYSBUS(VAPICROMState, dev);
680
memory_region_init_io(&s->io, &vapic_ops, s, "kvmvapic", 2);
681
sysbus_add_io(dev, VAPIC_IO_PORT, &s->io);
682
sysbus_init_ioports(dev, VAPIC_IO_PORT, 2);
684
option_rom[nb_option_roms].name = "kvmvapic.bin";
685
option_rom[nb_option_roms].bootindex = -1;
691
static void do_vapic_enable(void *data)
693
VAPICROMState *s = data;
695
vapic_enable(s, first_cpu);
698
static int vapic_post_load(void *opaque, int version_id)
700
VAPICROMState *s = opaque;
704
* The old implementation of qemu-kvm did not provide the state
705
* VAPIC_STANDBY. Reconstruct it.
707
if (s->state == VAPIC_INACTIVE && s->rom_state_paddr != 0) {
708
s->state = VAPIC_STANDBY;
711
if (s->state != VAPIC_INACTIVE) {
712
if (vapic_prepare(s) < 0) {
716
if (s->state == VAPIC_ACTIVE) {
718
run_on_cpu(first_cpu, do_vapic_enable, s);
720
zero = g_malloc0(s->rom_state.vapic_size);
721
cpu_physical_memory_rw(s->vapic_paddr, zero,
722
s->rom_state.vapic_size, 1);
730
static const VMStateDescription vmstate_handlers = {
731
.name = "kvmvapic-handlers",
733
.minimum_version_id = 1,
734
.minimum_version_id_old = 1,
735
.fields = (VMStateField[]) {
736
VMSTATE_UINT32(set_tpr, VAPICHandlers),
737
VMSTATE_UINT32(set_tpr_eax, VAPICHandlers),
738
VMSTATE_UINT32_ARRAY(get_tpr, VAPICHandlers, 8),
739
VMSTATE_UINT32(get_tpr_stack, VAPICHandlers),
740
VMSTATE_END_OF_LIST()
744
static const VMStateDescription vmstate_guest_rom = {
745
.name = "kvmvapic-guest-rom",
747
.minimum_version_id = 1,
748
.minimum_version_id_old = 1,
749
.fields = (VMStateField[]) {
750
VMSTATE_UNUSED(8), /* signature */
751
VMSTATE_UINT32(vaddr, GuestROMState),
752
VMSTATE_UINT32(fixup_start, GuestROMState),
753
VMSTATE_UINT32(fixup_end, GuestROMState),
754
VMSTATE_UINT32(vapic_vaddr, GuestROMState),
755
VMSTATE_UINT32(vapic_size, GuestROMState),
756
VMSTATE_UINT32(vcpu_shift, GuestROMState),
757
VMSTATE_UINT32(real_tpr_addr, GuestROMState),
758
VMSTATE_STRUCT(up, GuestROMState, 0, vmstate_handlers, VAPICHandlers),
759
VMSTATE_STRUCT(mp, GuestROMState, 0, vmstate_handlers, VAPICHandlers),
760
VMSTATE_END_OF_LIST()
764
static const VMStateDescription vmstate_vapic = {
765
.name = "kvm-tpr-opt", /* compatible with qemu-kvm VAPIC */
767
.minimum_version_id = 1,
768
.minimum_version_id_old = 1,
769
.post_load = vapic_post_load,
770
.fields = (VMStateField[]) {
771
VMSTATE_STRUCT(rom_state, VAPICROMState, 0, vmstate_guest_rom,
773
VMSTATE_UINT32(state, VAPICROMState),
774
VMSTATE_UINT32(real_tpr_addr, VAPICROMState),
775
VMSTATE_UINT32(rom_state_vaddr, VAPICROMState),
776
VMSTATE_UINT32(vapic_paddr, VAPICROMState),
777
VMSTATE_UINT32(rom_state_paddr, VAPICROMState),
778
VMSTATE_END_OF_LIST()
782
static void vapic_class_init(ObjectClass *klass, void *data)
784
SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
785
DeviceClass *dc = DEVICE_CLASS(klass);
788
dc->reset = vapic_reset;
789
dc->vmsd = &vmstate_vapic;
790
sc->init = vapic_init;
793
static TypeInfo vapic_type = {
795
.parent = TYPE_SYS_BUS_DEVICE,
796
.instance_size = sizeof(VAPICROMState),
797
.class_init = vapic_class_init,
800
static void vapic_register(void)
802
type_register_static(&vapic_type);
805
type_init(vapic_register);