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Viewing changes to libdrm-poulsbo/shared-core/nv50_fifo.c

  • Committer: Luca Forina
  • Date: 2011-02-14 09:55:00 UTC
  • Revision ID: luca.forina@gmail.com-20110214095500-kq7o333fbjuoquqs
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libdrm-poulsbo/shared-core/nv50_fifo.c
 
1
/*
 
2
 * Copyright (C) 2007 Ben Skeggs.
 
3
 * All Rights Reserved.
 
4
 *
 
5
 * Permission is hereby granted, free of charge, to any person obtaining
 
6
 * a copy of this software and associated documentation files (the
 
7
 * "Software"), to deal in the Software without restriction, including
 
8
 * without limitation the rights to use, copy, modify, merge, publish,
 
9
 * distribute, sublicense, and/or sell copies of the Software, and to
 
10
 * permit persons to whom the Software is furnished to do so, subject to
 
11
 * the following conditions:
 
12
 *
 
13
 * The above copyright notice and this permission notice (including the
 
14
 * next paragraph) shall be included in all copies or substantial
 
15
 * portions of the Software.
 
16
 *
 
17
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 
18
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 
19
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 
20
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 
21
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 
22
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 
23
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
24
 *
 
25
 */
 
26
 
 
27
#include "drmP.h"
 
28
#include "drm.h"
 
29
#include "nouveau_drv.h"
 
30
 
 
31
typedef struct {
 
32
        struct nouveau_gpuobj_ref *thingo;
 
33
} nv50_fifo_priv;
 
34
 
 
35
#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)
 
36
 
 
37
static void
 
38
nv50_fifo_init_thingo(struct drm_device *dev)
 
39
{
 
40
        struct drm_nouveau_private *dev_priv = dev->dev_private;
 
41
        nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
 
42
        struct nouveau_gpuobj_ref *thingo = priv->thingo;
 
43
        int i, fi=2;
 
44
 
 
45
        DRM_DEBUG("\n");
 
46
 
 
47
        INSTANCE_WR(thingo->gpuobj, 0, 0x7e);
 
48
        INSTANCE_WR(thingo->gpuobj, 1, 0x7e);
 
49
        for (i = 1; i < 127; i++, fi) {
 
50
                if (dev_priv->fifos[i]) {
 
51
                        INSTANCE_WR(thingo->gpuobj, fi, i);
 
52
                        fi++;
 
53
                }
 
54
        }
 
55
 
 
56
        NV_WRITE(0x32f4, thingo->instance >> 12);
 
57
        NV_WRITE(0x32ec, fi);
 
58
        NV_WRITE(0x2500, 0x101);
 
59
}
 
60
 
 
61
static int
 
62
nv50_fifo_channel_enable(struct drm_device *dev, int channel, int nt)
 
63
{
 
64
        struct drm_nouveau_private *dev_priv = dev->dev_private;
 
65
        struct nouveau_channel *chan = dev_priv->fifos[channel];
 
66
        uint32_t inst;
 
67
 
 
68
        DRM_DEBUG("ch%d\n", channel);
 
69
 
 
70
        if (!chan->ramfc)
 
71
                return -EINVAL;
 
72
 
 
73
        if (IS_G80) inst = chan->ramfc->instance >> 12;
 
74
        else        inst = chan->ramfc->instance >> 8;
 
75
        NV_WRITE(NV50_PFIFO_CTX_TABLE(channel),
 
76
                 inst | NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
 
77
 
 
78
        if (!nt) nv50_fifo_init_thingo(dev);
 
79
        return 0;
 
80
}
 
81
 
 
82
static void
 
83
nv50_fifo_channel_disable(struct drm_device *dev, int channel, int nt)
 
84
{
 
85
        struct drm_nouveau_private *dev_priv = dev->dev_private;
 
86
        uint32_t inst;
 
87
 
 
88
        DRM_DEBUG("ch%d, nt=%d\n", channel, nt);
 
89
 
 
90
        if (IS_G80) inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80;
 
91
        else        inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84;
 
92
        NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), inst);
 
93
 
 
94
        if (!nt) nv50_fifo_init_thingo(dev);
 
95
}
 
96
 
 
97
static void
 
98
nv50_fifo_init_reset(struct drm_device *dev)
 
99
{
 
100
        struct drm_nouveau_private *dev_priv = dev->dev_private;
 
101
        uint32_t pmc_e;
 
102
 
 
103
        DRM_DEBUG("\n");
 
104
 
 
105
        pmc_e = NV_READ(NV03_PMC_ENABLE);
 
106
        NV_WRITE(NV03_PMC_ENABLE, pmc_e & ~NV_PMC_ENABLE_PFIFO);
 
107
        pmc_e = NV_READ(NV03_PMC_ENABLE);
 
108
        NV_WRITE(NV03_PMC_ENABLE, pmc_e |  NV_PMC_ENABLE_PFIFO);
 
109
}
 
110
 
 
111
static void
 
112
nv50_fifo_init_intr(struct drm_device *dev)
 
113
{
 
114
        struct drm_nouveau_private *dev_priv = dev->dev_private;
 
115
 
 
116
        DRM_DEBUG("\n");
 
117
 
 
118
        NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF);
 
119
        NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
 
120
}
 
121
 
 
122
static void
 
123
nv50_fifo_init_context_table(struct drm_device *dev)
 
124
{
 
125
        int i;
 
126
 
 
127
        DRM_DEBUG("\n");
 
128
 
 
129
        for (i = 0; i < NV50_PFIFO_CTX_TABLE__SIZE; i++)
 
130
                nv50_fifo_channel_disable(dev, i, 1);
 
131
        nv50_fifo_init_thingo(dev);
 
132
}
 
133
 
 
134
static void
 
135
nv50_fifo_init_regs__nv(struct drm_device *dev)
 
136
{
 
137
        struct drm_nouveau_private *dev_priv = dev->dev_private;
 
138
 
 
139
        DRM_DEBUG("\n");
 
140
 
 
141
        NV_WRITE(0x250c, 0x6f3cfc34);
 
142
}
 
143
 
 
144
static int
 
145
nv50_fifo_init_regs(struct drm_device *dev)
 
146
{
 
147
        struct drm_nouveau_private *dev_priv = dev->dev_private;
 
148
 
 
149
        DRM_DEBUG("\n");
 
150
 
 
151
        NV_WRITE(0x2500, 0);
 
152
        NV_WRITE(0x3250, 0);
 
153
        NV_WRITE(0x3220, 0);
 
154
        NV_WRITE(0x3204, 0);
 
155
        NV_WRITE(0x3210, 0);
 
156
        NV_WRITE(0x3270, 0);
 
157
 
 
158
        /* Enable dummy channels setup by nv50_instmem.c */
 
159
        nv50_fifo_channel_enable(dev, 0, 1);
 
160
        nv50_fifo_channel_enable(dev, 127, 1);
 
161
 
 
162
        return 0;
 
163
}
 
164
 
 
165
int
 
166
nv50_fifo_init(struct drm_device *dev)
 
167
{
 
168
        struct drm_nouveau_private *dev_priv = dev->dev_private;
 
169
        nv50_fifo_priv *priv;
 
170
        int ret;
 
171
 
 
172
        DRM_DEBUG("\n");
 
173
 
 
174
        priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER);
 
175
        if (!priv)
 
176
                return -ENOMEM;
 
177
        dev_priv->Engine.fifo.priv = priv;
 
178
 
 
179
        nv50_fifo_init_reset(dev);
 
180
        nv50_fifo_init_intr(dev);
 
181
 
 
182
        if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, (128+2)*4, 0x1000,
 
183
                                   NVOBJ_FLAG_ZERO_ALLOC,
 
184
                                   &priv->thingo))) {
 
185
                DRM_ERROR("error creating thingo: %d\n", ret);
 
186
                return ret;
 
187
        }
 
188
 
 
189
        nv50_fifo_init_context_table(dev);
 
190
 
 
191
        nv50_fifo_init_regs__nv(dev);
 
192
        if ((ret = nv50_fifo_init_regs(dev)))
 
193
                return ret;
 
194
 
 
195
        return 0;
 
196
}
 
197
 
 
198
void
 
199
nv50_fifo_takedown(struct drm_device *dev)
 
200
{
 
201
        struct drm_nouveau_private *dev_priv = dev->dev_private;
 
202
        nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
 
203
 
 
204
        DRM_DEBUG("\n");
 
205
 
 
206
        if (!priv)
 
207
                return;
 
208
 
 
209
        nouveau_gpuobj_ref_del(dev, &priv->thingo);
 
210
 
 
211
        dev_priv->Engine.fifo.priv = NULL;
 
212
        drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER);
 
213
}
 
214
 
 
215
int
 
216
nv50_fifo_create_context(struct nouveau_channel *chan)
 
217
{
 
218
        struct drm_device *dev = chan->dev;
 
219
        struct drm_nouveau_private *dev_priv = dev->dev_private;
 
220
        struct nouveau_gpuobj *ramfc = NULL;
 
221
        int ret;
 
222
 
 
223
        DRM_DEBUG("ch%d\n", chan->id);
 
224
 
 
225
        if (IS_G80) {
 
226
                uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start;
 
227
                uint32_t vram_offset = chan->ramin->gpuobj->im_backing->start;
 
228
                if ((ret = nouveau_gpuobj_new_fake(dev, ramfc_offset,
 
229
                                                   vram_offset, 0x100,
 
230
                                                   NVOBJ_FLAG_ZERO_ALLOC |
 
231
                                                   NVOBJ_FLAG_ZERO_FREE,
 
232
                                                   &ramfc, &chan->ramfc)))
 
233
                                return ret;
 
234
        } else {
 
235
                if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100,
 
236
                                                  256,
 
237
                                                  NVOBJ_FLAG_ZERO_ALLOC |
 
238
                                                  NVOBJ_FLAG_ZERO_FREE,
 
239
                                                  &chan->ramfc)))
 
240
                        return ret;
 
241
                ramfc = chan->ramfc->gpuobj;
 
242
        }
 
243
 
 
244
        INSTANCE_WR(ramfc, 0x48/4, chan->pushbuf->instance >> 4);
 
245
        INSTANCE_WR(ramfc, 0x80/4, (0xc << 24) | (chan->ramht->instance >> 4));
 
246
        INSTANCE_WR(ramfc, 0x3c/4, 0x000f0078); /* fetch? */
 
247
        INSTANCE_WR(ramfc, 0x44/4, 0x2101ffff);
 
248
        INSTANCE_WR(ramfc, 0x60/4, 0x7fffffff);
 
249
        INSTANCE_WR(ramfc, 0x10/4, 0x00000000);
 
250
        INSTANCE_WR(ramfc, 0x08/4, 0x00000000);
 
251
        INSTANCE_WR(ramfc, 0x40/4, 0x00000000);
 
252
        INSTANCE_WR(ramfc, 0x50/4, 0x2039b2e0);
 
253
        INSTANCE_WR(ramfc, 0x54/4, 0x000f0000);
 
254
        INSTANCE_WR(ramfc, 0x7c/4, 0x30000001);
 
255
        INSTANCE_WR(ramfc, 0x78/4, 0x00000000);
 
256
        INSTANCE_WR(ramfc, 0x4c/4, chan->pushbuf_mem->size - 1);
 
257
 
 
258
        if (!IS_G80) {
 
259
                INSTANCE_WR(chan->ramin->gpuobj, 0, chan->id);
 
260
                INSTANCE_WR(chan->ramin->gpuobj, 1, chan->ramfc->instance);
 
261
 
 
262
                INSTANCE_WR(ramfc, 0x88/4, 0x3d520); /* some vram addy >> 10 */
 
263
                INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12);
 
264
        }
 
265
 
 
266
        if ((ret = nv50_fifo_channel_enable(dev, chan->id, 0))) {
 
267
                DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret);
 
268
                nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 
269
                return ret;
 
270
        }
 
271
 
 
272
        return 0;
 
273
}
 
274
 
 
275
void
 
276
nv50_fifo_destroy_context(struct nouveau_channel *chan)
 
277
{
 
278
        struct drm_device *dev = chan->dev;
 
279
 
 
280
        DRM_DEBUG("ch%d\n", chan->id);
 
281
 
 
282
        nv50_fifo_channel_disable(dev, chan->id, 0);
 
283
 
 
284
        /* Dummy channel, also used on ch 127 */
 
285
        if (chan->id == 0)
 
286
                nv50_fifo_channel_disable(dev, 127, 0);
 
287
 
 
288
        nouveau_gpuobj_ref_del(dev, &chan->ramfc);
 
289
}
 
290
 
 
291
int
 
292
nv50_fifo_load_context(struct nouveau_channel *chan)
 
293
{
 
294
        struct drm_device *dev = chan->dev;
 
295
        struct drm_nouveau_private *dev_priv = dev->dev_private;
 
296
        struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj;
 
297
 
 
298
        DRM_DEBUG("ch%d\n", chan->id);
 
299
 
 
300
        /*XXX: incomplete, only touches the regs that NV does */
 
301
 
 
302
        NV_WRITE(0x3244, 0);
 
303
        NV_WRITE(0x3240, 0);
 
304
 
 
305
        NV_WRITE(0x3224, INSTANCE_RD(ramfc, 0x3c/4));
 
306
        NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, INSTANCE_RD(ramfc, 0x48/4));
 
307
        NV_WRITE(0x3234, INSTANCE_RD(ramfc, 0x4c/4));
 
308
        NV_WRITE(0x3254, 1);
 
309
        NV_WRITE(NV03_PFIFO_RAMHT, INSTANCE_RD(ramfc, 0x80/4));
 
310
 
 
311
        if (!IS_G80) {
 
312
                NV_WRITE(0x340c, INSTANCE_RD(ramfc, 0x88/4));
 
313
                NV_WRITE(0x3410, INSTANCE_RD(ramfc, 0x98/4));
 
314
        }
 
315
 
 
316
        NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
 
317
        return 0;
 
318
}
 
319
 
 
320
int
 
321
nv50_fifo_save_context(struct nouveau_channel *chan)
 
322
{
 
323
        DRM_DEBUG("ch%d\n", chan->id);
 
324
        DRM_ERROR("stub!\n");
 
325
        return 0;
 
326
}
 
327