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*-----------------------------------------------------------------------------
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* Filename: ovl_regs_plb.h
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*-----------------------------------------------------------------------------
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* Copyright © 2002-2010, Intel Corporation.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*-----------------------------------------------------------------------------
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* This is the internal header file for overlay. It should be not be
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* by any other module besides the overlay module itself. It contains the
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* neccessary hardware virtualized register dependant information including
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* values, structures and addresses specifically for the Napa core
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*-----------------------------------------------------------------------------
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#ifndef OVL_REGS_PLB_H_
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#define OVL_REGS_PLB_H_
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/* Overlay Update Register Image Structure.*/
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typedef struct _ovl_reg_image_plb{
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volatile unsigned int buffer0_yrgb_ptr;
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volatile unsigned int buffer1_yrgb_ptr;
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volatile unsigned int buffer0_u_ptr;
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volatile unsigned int buffer0_v_ptr;
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volatile unsigned int buffer1_u_ptr;
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volatile unsigned int buffer1_v_ptr;
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volatile unsigned short yrgb_stride;
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volatile unsigned short uv_stride;
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volatile unsigned short yrgb_vert_phase_field0;
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volatile unsigned short yrgb_vert_phase_field1;
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volatile unsigned short uv_vert_phase_field0;
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volatile unsigned short uv_vert_phase_field1;
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volatile unsigned short yrgb_hphase;
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volatile unsigned short uv_hphase;
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volatile unsigned int init_phase_shift;
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volatile unsigned short dest_pos_x_left;
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volatile unsigned short dest_pos_y_top;
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volatile unsigned short dest_width_x;
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volatile unsigned short dest_height_y;
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volatile unsigned short source_yrgb_width;
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volatile unsigned short source_uv_width;
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volatile unsigned short source_yrgb_width_swords;
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volatile unsigned short source_uv_width_swords;
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volatile unsigned short source_yrgb_height;
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volatile unsigned short source_uv_height;
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volatile unsigned int yrgb_scale;
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volatile unsigned int uv_scale;
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volatile unsigned int col_ctl_brt_con;
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volatile unsigned int col_ctl_sat_hue;
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volatile unsigned int dest_ckey_val;
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volatile unsigned int dest_ckey_mask;
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volatile unsigned int source_ckey_high;
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volatile unsigned int source_ckey_low;
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volatile unsigned int source_ckey_mask;
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volatile unsigned int config;
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volatile unsigned int command;
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volatile unsigned int reserved1;
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volatile unsigned short alpha_pos_x_left;
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volatile unsigned short alpha_pos_y_top;
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volatile unsigned short alpha_width_x;
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volatile unsigned short alpha_height_y;
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volatile unsigned int reserved2;
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volatile unsigned int reserved3;
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volatile unsigned int reserved4;
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volatile unsigned int reserved5;
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volatile unsigned int reserved6;
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volatile unsigned int reserved7;
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volatile unsigned int reserved8;
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volatile unsigned int reserved9;
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volatile unsigned int reserved10;
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volatile unsigned int reserved11;
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volatile unsigned int reserved11a; /*ovl_fast_horz_downscale;*/
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volatile unsigned int vert_downscale;
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volatile unsigned int reserved12[86];
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volatile unsigned short y_vert_coeff_single[52]; /*offset 0x200 --> 3*17/2 + 1*/
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volatile unsigned int reserved13[38];
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volatile unsigned short y_horz_coeff_single[86]; /*offset 0x300 --> 5*17/2 + 1*/
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volatile unsigned int reserved14[85];
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volatile unsigned short uv_vert_coeff_single[52]; /*offset 0x500 --> 3*17/2 + 1*/
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volatile unsigned int reserved15[38];
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volatile unsigned short uv_horz_coeff_single[52]; /*offset 0x600 --> 3*17/2 + 1*/
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volatile unsigned int reserved16[38];
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} ovl_reg_image_plb_t;
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/* Color Correction */
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#define OVL_YUV_COLOR_DEF_CONT_BRGHT 0x10c00fb
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#define OVL_YUV_COLOR_DEF_SATN_HUE 0x0000091
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#define OVL_RGB_COLOR_DEF_CONT_BRGHT 0x1000000
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#define OVL_RGB_COLOR_DEF_SATN_HUE 0x0000080
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#define OVL_CONFIG_NO_LINE_BUFF 0xffffffff
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#define OVL_CONFIG_TWO_LINE_BUFF 0x00000000
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#define OVL_CONFIG_THREE_LINE_BUFF 0x00000001
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#define OVL_CONFIG_LINE_BUFF_MASK 0x00000001
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/* Overlay Command Definitions */
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#define OVL_CMD_UV_SWAP 0x00004000
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#define OVL_CMD_Y_SWAP 0x00008000
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#define OVL_CMD_YUV_SWAP 0x0000C000
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#define OVL_CMD_RGB_8888 0x00000400
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#define OVL_CMD_RGB_565 0x00000C00
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#define OVL_CMD_RGB_555 0x00000800
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#define OVL_CMD_YUV_NV12Alt 0x00001C00 /*planar NV12, Alternate?*/
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#define OVL_CMD_YUV_NV12 0x00002C00 /*planar NV12*/
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#define OVL_CMD_YUV_422 0x00002000 /*packed YUV422*/
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#define OVL_CMD_YUV_411 0x00002400 /*packed YUV411*/
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#define OVL_CMD_YUV_420P 0x00003000 /*planar YUV420*/
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#define OVL_CMD_YUV_422P 0x00003400 /*planar YUV422*/
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#define OVL_CMD_YUV_410P 0x00003800 /*planar YUV410*/
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#define OVL_CMD_YUV_444P 0x00003C00 /*planar YUV444*/
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#define OVL_CMD_SRC_FMT_MASK 0x00003C00 /*mask for above*/
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#define OVL_CMD_FRAME_MODE 0x00000000
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#define OVL_CMD_FIELD_MODE 0x00000020
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/* Field Sync Flip Enable */
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#define OVL_CMD_FIELD_SYNC_FLIP 0x00000080
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/* Buffer and Field */
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#define OVL_CMD_ACT_BUF0 0x00000000
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#define OVL_CMD_ACT_BUF1 0x00000004
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#define OVL_CMD_ACT_FLD0 0x00000000
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#define OVL_CMD_ACT_FLD1 0x00000002
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/* Initial phase register */
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#define Y_VPP_FLD0_PLUS1 0x100000
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#define Y_VPP_FLD0_PLUS2 0x200000
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#define Y_VPP_FLD0_MINUS1 0xF00000
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#define Y_VPP_FLD1_PLUS1 0x010000
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#define Y_VPP_FLD1_PLUS2 0x020000
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#define Y_VPP_FLD1_MINUS1 0x0F0000
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#define Y_HPP_PLUS1 0x001000
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#define Y_HPP_PLUS2 0x002000
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#define Y_HPP_MINUS1 0x00F000
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#define UV_VPP_FLD0_PLUS1 0x000100
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#define UV_VPP_FLD0_PLUS2 0x000200
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#define UV_VPP_FLD0_MINUS1 0x000F00
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#define UV_VPP_FLD1_PLUS1 0x000010
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#define UV_VPP_FLD1_PLUS2 0x000020
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#define UV_VPP_FLD1_MINUS1 0x0000F0
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#define UV_HPP_PLUS1 0x000001
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#define UV_HPP_PLUS2 0x000002
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#define UV_HPP_MINUS1 0x00000F
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#define OVL_REG_ADDR_GAMMA5 0x30010
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#define OVL_REG_ADDR_GAMMA4 0x30014
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#define OVL_REG_ADDR_GAMMA3 0x30018
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#define OVL_REG_ADDR_GAMMA2 0x3001C
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#define OVL_REG_ADDR_GAMMA1 0x30020
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#define OVL_REG_ADDR_GAMMA0 0x30024
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#define OVL_TOTAL_GAMMA_REG 6
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/* following value are needed because hardware seems to display yuv slightly dimmer
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than RGB when color data is calculated out to be equal */
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#define MID_CONTRAST_YUV 0x43//4a
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#define MID_SATURATION_YUV 0x91//92
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#define MID_BRIGHTNESS_YUV -5
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#endif /* OVL_REGISTER_IMAGE_H_ */