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Viewing changes to data/general-hooks/parse_segv.py

  • Committer: Kees Cook
  • Date: 2009-09-13 01:14:15 UTC
  • Revision ID: kees@outflux.net-20090913011415-okr0u8eys436ho90
add test for 64bit modulo branch too

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data/general-hooks/parse_segv.py
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def add_info(report):
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    # Only interested in segmentation faults...
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    if report.get('Signal') != '11':
 
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    if report.get('Signal','0') != '11':
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        return
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    needed = ['Signal', 'Architecture', 'Disassembly', 'ProcMaps', 'Registers']
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fs             0x4  4
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gs             0x33 51
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'''
 
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        regs64 = '''rax            0xffffffffffffffff   -1
 
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rbx            0x26eff4 2551796
 
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rcx            0xffffffffffffffff   -1
 
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rdx            0xffffffffff600180   -10485376
 
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rsi            0x0  0
 
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rdi            0x7fffffffe3b0   140737488348080
 
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rbp            0x0  0x0
 
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rsp            0x7fffffffe388   0x7fffffffe388
 
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r8             0x0  0
 
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r9             0x0  0
 
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r10            0x7fffffffe140   140737488347456
 
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r11            0x246    582
 
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r12            0x7fffffffe400   140737488348160
 
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r13            0x7fffffffe468   140737488348264
 
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r14            0x1  1
 
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r15            0x7fffffffe460   140737488348256
 
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rip            0x7ffff790be10   0x7ffff790be10 <nanosleep+16>
 
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eflags         0x246    [ PF ZF IF ]
 
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cs             0x33 51
 
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ss             0x2b 43
 
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ds             0x0  0
 
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es             0x0  0
 
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fs             0x0  0
 
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gs             0x0  0
 
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fctrl          0x37f    895
 
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fstat          0x0  0
 
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ftag           0xffff   65535
 
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fiseg          0x0  0
 
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fioff          0x40303a 4206650
 
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foseg          0x0  0
 
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fooff          0x0  0
 
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fop            0x5d8    1496
 
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mxcsr          0x1f80   [ IM DM ZM OM UM PM ]
 
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'''
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        maps = '''00110000-0026c000 r-xp 00000000 08:06 375131     /lib/tls/i686/cmov/libc-2.9.so
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0026c000-0026d000 ---p 0015c000 08:06 375131     /lib/tls/i686/cmov/libc-2.9.so
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0026d000-0026f000 r--p 0015c000 08:06 375131     /lib/tls/i686/cmov/libc-2.9.so
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                self.assertEqual(segv.calculate_arg('(%edx,%ebx,1)'), 0x26eff5, segv.regs['ebx'])
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                self.assertEqual(segv.calculate_arg('(%eax,%ebx,1)'), 0x26eff3, segv.regs['ebx'])
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                # Again, but 64bit
 
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                disasm = '''0x08083540 <main+0>:    mov    $1,%rcx'''
 
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                segv = ParseSegv(regs64, disasm, maps)
 
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                understood, reason, details = segv.report()
 
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                self.assertFalse(understood, details)
 
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                self.assertEqual(segv.calculate_arg('(%rax,%rbx,1)'), 0x26eff3, segv.regs['rbx'])
 
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            def test_segv_pc_missing(self):
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                '''Handles PC in missing VMA'''
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