2
* TI OMAP DMA gigacell.
4
* Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5
* Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br>
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* This program is free software; you can redistribute it and/or
8
* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
13
* but WITHOUT ANY WARRANTY; without even the implied warranty of
14
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
20
#include "qemu-common.h"
21
#include "qemu-timer.h"
26
struct omap_dma_channel_s {
33
enum omap_dma_port port[2];
34
target_phys_addr_t addr[2];
35
omap_dma_addressing_t mode[2];
38
int32_t frame_index[2];
39
int16_t element_index[2];
48
/* auto init and linked channel data */
55
/* interruption data */
75
int omap_3_1_compatible_disable;
78
struct omap_dma_channel_s *sibling;
80
struct omap_dma_reg_set_s {
81
target_phys_addr_t src, dest;
92
struct soc_dma_ch_s *dma;
94
/* unused parameters */
97
int interleave_disabled;
104
struct soc_dma_s *dma;
107
struct omap_mpu_state_s *mpu;
110
void (*intr_update)(struct omap_dma_s *s);
111
enum omap_dma_model model;
112
int omap_3_1_mapping_disabled;
121
struct omap_dma_channel_s ch[32];
122
struct omap_dma_lcd_channel_s lcd_ch;
126
#define TIMEOUT_INTR (1 << 0)
127
#define EVENT_DROP_INTR (1 << 1)
128
#define HALF_FRAME_INTR (1 << 2)
129
#define END_FRAME_INTR (1 << 3)
130
#define LAST_FRAME_INTR (1 << 4)
131
#define END_BLOCK_INTR (1 << 5)
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#define SYNC (1 << 6)
133
#define END_PKT_INTR (1 << 7)
134
#define TRANS_ERR_INTR (1 << 8)
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#define MISALIGN_INTR (1 << 11)
137
static inline void omap_dma_interrupts_update(struct omap_dma_s *s)
139
return s->intr_update(s);
142
static void omap_dma_channel_load(struct omap_dma_channel_s *ch)
144
struct omap_dma_reg_set_s *a = &ch->active_set;
146
int omap_3_1 = !ch->omap_3_1_compatible_disable;
149
* TODO: verify address ranges and alignment
150
* TODO: port endianness
153
a->src = ch->addr[0];
154
a->dest = ch->addr[1];
155
a->frames = ch->frames;
156
a->elements = ch->elements;
157
a->pck_elements = ch->frame_index[!ch->src_sync];
162
if (unlikely(!ch->elements || !ch->frames)) {
163
printf("%s: bad DMA request\n", __FUNCTION__);
167
for (i = 0; i < 2; i ++)
168
switch (ch->mode[i]) {
170
a->elem_delta[i] = 0;
171
a->frame_delta[i] = 0;
173
case post_incremented:
174
a->elem_delta[i] = ch->data_type;
175
a->frame_delta[i] = 0;
178
a->elem_delta[i] = ch->data_type +
179
ch->element_index[omap_3_1 ? 0 : i] - 1;
180
a->frame_delta[i] = 0;
183
a->elem_delta[i] = ch->data_type +
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ch->element_index[omap_3_1 ? 0 : i] - 1;
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a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
186
ch->element_index[omap_3_1 ? 0 : i];
192
normal = !ch->transparent_copy && !ch->constant_fill &&
193
/* FIFO is big-endian so either (ch->endian[n] == 1) OR
194
* (ch->endian_lock[n] == 1) mean no endianism conversion. */
195
(ch->endian[0] | ch->endian_lock[0]) ==
196
(ch->endian[1] | ch->endian_lock[1]);
197
for (i = 0; i < 2; i ++) {
198
/* TODO: for a->frame_delta[i] > 0 still use the fast path, just
199
* limit min_elems in omap_dma_transfer_setup to the nearest frame
201
if (!a->elem_delta[i] && normal &&
202
(a->frames == 1 || !a->frame_delta[i]))
203
ch->dma->type[i] = soc_dma_access_const;
204
else if (a->elem_delta[i] == ch->data_type && normal &&
205
(a->frames == 1 || !a->frame_delta[i]))
206
ch->dma->type[i] = soc_dma_access_linear;
208
ch->dma->type[i] = soc_dma_access_other;
210
ch->dma->vaddr[i] = ch->addr[i];
212
soc_dma_ch_update(ch->dma);
215
static void omap_dma_activate_channel(struct omap_dma_s *s,
216
struct omap_dma_channel_s *ch)
219
if (ch->set_update) {
220
/* It's not clear when the active set is supposed to be
221
* loaded from registers. We're already loading it when the
222
* channel is enabled, and for some guests this is not enough
223
* but that may be also because of a race condition (no
224
* delays in qemu) in the guest code, which we're just
225
* working around here. */
226
omap_dma_channel_load(ch);
231
soc_dma_set_request(ch->dma, 1);
237
static void omap_dma_deactivate_channel(struct omap_dma_s *s,
238
struct omap_dma_channel_s *ch)
241
ch->cpc = ch->active_set.dest & 0xffff;
243
if (ch->pending_request && !ch->waiting_end_prog && ch->enable) {
244
/* Don't deactivate the channel */
245
ch->pending_request = 0;
249
/* Don't deactive the channel if it is synchronized and the DMA request is
251
if (ch->sync && ch->enable && (s->dma->drqbmp & (1 << ch->sync)))
257
soc_dma_set_request(ch->dma, 0);
261
static void omap_dma_enable_channel(struct omap_dma_s *s,
262
struct omap_dma_channel_s *ch)
266
ch->waiting_end_prog = 0;
267
omap_dma_channel_load(ch);
268
/* TODO: theoretically if ch->sync && ch->prefetch &&
269
* !s->dma->drqbmp[ch->sync], we should also activate and fetch
270
* from source and then stall until signalled. */
271
if ((!ch->sync) || (s->dma->drqbmp & (1 << ch->sync)))
272
omap_dma_activate_channel(s, ch);
276
static void omap_dma_disable_channel(struct omap_dma_s *s,
277
struct omap_dma_channel_s *ch)
281
/* Discard any pending request */
282
ch->pending_request = 0;
283
omap_dma_deactivate_channel(s, ch);
287
static void omap_dma_channel_end_prog(struct omap_dma_s *s,
288
struct omap_dma_channel_s *ch)
290
if (ch->waiting_end_prog) {
291
ch->waiting_end_prog = 0;
292
if (!ch->sync || ch->pending_request) {
293
ch->pending_request = 0;
294
omap_dma_activate_channel(s, ch);
299
static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s)
301
struct omap_dma_channel_s *ch = s->ch;
303
/* First three interrupts are shared between two channels each. */
304
if (ch[0].status | ch[6].status)
305
qemu_irq_raise(ch[0].irq);
306
if (ch[1].status | ch[7].status)
307
qemu_irq_raise(ch[1].irq);
308
if (ch[2].status | ch[8].status)
309
qemu_irq_raise(ch[2].irq);
311
qemu_irq_raise(ch[3].irq);
313
qemu_irq_raise(ch[4].irq);
315
qemu_irq_raise(ch[5].irq);
318
static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s)
320
struct omap_dma_channel_s *ch = s->ch;
323
for (i = s->chans; i; ch ++, i --)
325
qemu_irq_raise(ch->irq);
328
static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s)
330
s->omap_3_1_mapping_disabled = 0;
332
s->intr_update = omap_dma_interrupts_3_1_update;
335
static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s)
337
s->omap_3_1_mapping_disabled = 1;
339
s->intr_update = omap_dma_interrupts_3_2_update;
342
static void omap_dma_process_request(struct omap_dma_s *s, int request)
346
struct omap_dma_channel_s *ch = s->ch;
348
for (channel = 0; channel < s->chans; channel ++, ch ++) {
349
if (ch->enable && ch->sync == request) {
351
omap_dma_activate_channel(s, ch);
352
else if (!ch->pending_request)
353
ch->pending_request = 1;
355
/* Request collision */
356
/* Second request received while processing other request */
357
ch->status |= EVENT_DROP_INTR;
364
omap_dma_interrupts_update(s);
367
static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma)
370
struct omap_dma_channel_s *ch = dma->opaque;
371
struct omap_dma_reg_set_s *a = &ch->active_set;
372
int bytes = dma->bytes;
374
uint16_t status = ch->status;
378
/* Transfer a single element */
379
/* FIXME: check the endianness */
380
if (!ch->constant_fill)
381
cpu_physical_memory_read(a->src, value, ch->data_type);
383
*(uint32_t *) value = ch->color;
385
if (!ch->transparent_copy || *(uint32_t *) value != ch->color)
386
cpu_physical_memory_write(a->dest, value, ch->data_type);
388
a->src += a->elem_delta[0];
389
a->dest += a->elem_delta[1];
393
if (a->element == a->elements) {
396
a->src += a->frame_delta[0];
397
a->dest += a->frame_delta[1];
400
/* If the channel is async, update cpc */
402
ch->cpc = a->dest & 0xffff;
404
} while ((bytes -= ch->data_type));
406
/* If the channel is element synchronized, deactivate it */
407
if (ch->sync && !ch->fs && !ch->bs)
408
omap_dma_deactivate_channel(s, ch);
410
/* If it is the last frame, set the LAST_FRAME interrupt */
411
if (a->element == 1 && a->frame == a->frames - 1)
412
if (ch->interrupts & LAST_FRAME_INTR)
413
ch->status |= LAST_FRAME_INTR;
415
/* If the half of the frame was reached, set the HALF_FRAME
417
if (a->element == (a->elements >> 1))
418
if (ch->interrupts & HALF_FRAME_INTR)
419
ch->status |= HALF_FRAME_INTR;
421
if (ch->fs && ch->bs) {
423
/* Check if a full packet has beed transferred. */
424
if (a->pck_element == a->pck_elements) {
427
/* Set the END_PKT interrupt */
428
if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync)
429
ch->status |= END_PKT_INTR;
431
/* If the channel is packet-synchronized, deactivate it */
433
omap_dma_deactivate_channel(s, ch);
437
if (a->element == a->elements) {
440
a->src += a->frame_delta[0];
441
a->dest += a->frame_delta[1];
444
/* If the channel is frame synchronized, deactivate it */
445
if (ch->sync && ch->fs && !ch->bs)
446
omap_dma_deactivate_channel(s, ch);
448
/* If the channel is async, update cpc */
450
ch->cpc = a->dest & 0xffff;
452
/* Set the END_FRAME interrupt */
453
if (ch->interrupts & END_FRAME_INTR)
454
ch->status |= END_FRAME_INTR;
456
if (a->frame == a->frames) {
458
/* Disable the channel */
460
if (ch->omap_3_1_compatible_disable) {
461
omap_dma_disable_channel(s, ch);
462
if (ch->link_enabled)
463
omap_dma_enable_channel(s,
464
&s->ch[ch->link_next_ch]);
467
omap_dma_disable_channel(s, ch);
468
else if (ch->repeat || ch->end_prog)
469
omap_dma_channel_load(ch);
471
ch->waiting_end_prog = 1;
472
omap_dma_deactivate_channel(s, ch);
476
if (ch->interrupts & END_BLOCK_INTR)
477
ch->status |= END_BLOCK_INTR;
480
} while (status == ch->status && ch->active);
482
omap_dma_interrupts_update(s);
487
omap_dma_intr_element_sync,
488
omap_dma_intr_last_frame,
489
omap_dma_intr_half_frame,
491
omap_dma_intr_frame_sync,
492
omap_dma_intr_packet,
493
omap_dma_intr_packet_sync,
495
__omap_dma_intr_last,
498
static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma)
500
struct omap_dma_port_if_s *src_p, *dest_p;
501
struct omap_dma_reg_set_s *a;
502
struct omap_dma_channel_s *ch = dma->opaque;
503
struct omap_dma_s *s = dma->dma->opaque;
504
int frames, min_elems, elements[__omap_dma_intr_last];
508
src_p = &s->mpu->port[ch->port[0]];
509
dest_p = &s->mpu->port[ch->port[1]];
510
if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
511
(!dest_p->addr_valid(s->mpu, a->dest))) {
514
if (ch->interrupts & TIMEOUT_INTR)
515
ch->status |= TIMEOUT_INTR;
516
omap_dma_deactivate_channel(s, ch);
519
printf("%s: Bus time-out in DMA%i operation\n",
520
__FUNCTION__, dma->num);
525
/* Check all the conditions that terminate the transfer starting
526
* with those that can occur the soonest. */
527
#define INTR_CHECK(cond, id, nelements) \
529
elements[id] = nelements; \
530
if (elements[id] < min_elems) \
531
min_elems = elements[id]; \
533
elements[id] = INT_MAX;
537
ch->sync && !ch->fs && !ch->bs,
538
omap_dma_intr_element_sync,
542
/* TODO: for transfers where entire frames can be read and written
543
* using memcpy() but a->frame_delta is non-zero, try to still do
544
* transfers using soc_dma but limit min_elems to a->elements - ...
545
* See also the TODO in omap_dma_channel_load. */
547
(ch->interrupts & LAST_FRAME_INTR) &&
548
((a->frame < a->frames - 1) || !a->element),
549
omap_dma_intr_last_frame,
550
(a->frames - a->frame - 2) * a->elements +
551
(a->elements - a->element + 1))
553
ch->interrupts & HALF_FRAME_INTR,
554
omap_dma_intr_half_frame,
556
(a->element >= (a->elements >> 1) ? a->elements : 0) -
559
ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR),
561
a->elements - a->element)
563
ch->sync && ch->fs && !ch->bs,
564
omap_dma_intr_frame_sync,
565
a->elements - a->element)
570
(ch->interrupts & END_PKT_INTR) && !ch->src_sync,
571
omap_dma_intr_packet,
572
a->pck_elements - a->pck_element)
574
ch->fs && ch->bs && ch->sync,
575
omap_dma_intr_packet_sync,
576
a->pck_elements - a->pck_element)
582
(a->frames - a->frame - 1) * a->elements +
583
(a->elements - a->element))
585
dma->bytes = min_elems * ch->data_type;
587
/* Set appropriate interrupts and/or deactivate channels */
590
/* TODO: should all of this only be done if dma->update, and otherwise
591
* inside omap_dma_transfer_generic below - check what's faster. */
595
/* If the channel is element synchronized, deactivate it */
596
if (min_elems == elements[omap_dma_intr_element_sync])
597
omap_dma_deactivate_channel(s, ch);
599
/* If it is the last frame, set the LAST_FRAME interrupt */
600
if (min_elems == elements[omap_dma_intr_last_frame])
601
ch->status |= LAST_FRAME_INTR;
603
/* If exactly half of the frame was reached, set the HALF_FRAME
605
if (min_elems == elements[omap_dma_intr_half_frame])
606
ch->status |= HALF_FRAME_INTR;
608
/* If a full packet has been transferred, set the END_PKT interrupt */
609
if (min_elems == elements[omap_dma_intr_packet])
610
ch->status |= END_PKT_INTR;
612
/* If the channel is packet-synchronized, deactivate it */
613
if (min_elems == elements[omap_dma_intr_packet_sync])
614
omap_dma_deactivate_channel(s, ch);
616
/* If the channel is frame synchronized, deactivate it */
617
if (min_elems == elements[omap_dma_intr_frame_sync])
618
omap_dma_deactivate_channel(s, ch);
620
/* Set the END_FRAME interrupt */
621
if (min_elems == elements[omap_dma_intr_frame])
622
ch->status |= END_FRAME_INTR;
624
if (min_elems == elements[omap_dma_intr_block]) {
626
/* Disable the channel */
628
if (ch->omap_3_1_compatible_disable) {
629
omap_dma_disable_channel(s, ch);
630
if (ch->link_enabled)
631
omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]);
634
omap_dma_disable_channel(s, ch);
635
else if (ch->repeat || ch->end_prog)
636
omap_dma_channel_load(ch);
638
ch->waiting_end_prog = 1;
639
omap_dma_deactivate_channel(s, ch);
643
if (ch->interrupts & END_BLOCK_INTR)
644
ch->status |= END_BLOCK_INTR;
647
/* Update packet number */
648
if (ch->fs && ch->bs) {
649
a->pck_element += min_elems;
650
a->pck_element %= a->pck_elements;
653
/* TODO: check if we really need to update anything here or perhaps we
654
* can skip part of this. */
658
a->element += min_elems;
660
frames = a->element / a->elements;
661
a->element = a->element % a->elements;
663
a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0];
664
a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1];
666
/* If the channel is async, update cpc */
667
if (!ch->sync && frames)
668
ch->cpc = a->dest & 0xffff;
670
/* TODO: if the destination port is IMIF or EMIFF, set the dirty
678
omap_dma_interrupts_update(s);
681
void omap_dma_reset(struct soc_dma_s *dma)
684
struct omap_dma_s *s = dma->opaque;
686
soc_dma_reset(s->dma);
687
if (s->model < omap_dma_4)
692
memset(&s->irqstat, 0, sizeof(s->irqstat));
693
memset(&s->irqen, 0, sizeof(s->irqen));
694
s->lcd_ch.src = emiff;
695
s->lcd_ch.condition = 0;
696
s->lcd_ch.interrupts = 0;
698
if (s->model < omap_dma_4)
699
omap_dma_enable_3_1_mapping(s);
700
for (i = 0; i < s->chans; i ++) {
701
s->ch[i].suspend = 0;
702
s->ch[i].prefetch = 0;
703
s->ch[i].buf_disable = 0;
704
s->ch[i].src_sync = 0;
705
memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));
706
memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));
707
memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));
708
memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));
709
memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));
710
memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian));
711
memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock));
712
memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate));
713
s->ch[i].write_mode = 0;
714
s->ch[i].data_type = 0;
715
s->ch[i].transparent_copy = 0;
716
s->ch[i].constant_fill = 0;
717
s->ch[i].color = 0x00000000;
718
s->ch[i].end_prog = 0;
720
s->ch[i].auto_init = 0;
721
s->ch[i].link_enabled = 0;
722
if (s->model < omap_dma_4)
723
s->ch[i].interrupts = 0x0003;
725
s->ch[i].interrupts = 0x0000;
727
s->ch[i].cstatus = 0;
731
s->ch[i].pending_request = 0;
732
s->ch[i].waiting_end_prog = 0;
733
s->ch[i].cpc = 0x0000;
736
s->ch[i].omap_3_1_compatible_disable = 0;
737
memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));
738
s->ch[i].priority = 0;
739
s->ch[i].interleave_disabled = 0;
744
static int omap_dma_ch_reg_read(struct omap_dma_s *s,
745
struct omap_dma_channel_s *ch, int reg, uint16_t *value)
748
case 0x00: /* SYS_DMA_CSDP_CH0 */
749
*value = (ch->burst[1] << 14) |
750
(ch->pack[1] << 13) |
752
(ch->burst[0] << 7) |
755
(ch->data_type >> 1);
758
case 0x02: /* SYS_DMA_CCR_CH0 */
759
if (s->model <= omap_dma_3_1)
760
*value = 0 << 10; /* FIFO_FLUSH reads as 0 */
762
*value = ch->omap_3_1_compatible_disable << 10;
763
*value |= (ch->mode[1] << 14) |
764
(ch->mode[0] << 12) |
765
(ch->end_prog << 11) |
767
(ch->auto_init << 8) |
769
(ch->priority << 6) |
770
(ch->fs << 5) | ch->sync;
773
case 0x04: /* SYS_DMA_CICR_CH0 */
774
*value = ch->interrupts;
777
case 0x06: /* SYS_DMA_CSR_CH0 */
780
if (!ch->omap_3_1_compatible_disable && ch->sibling) {
781
*value |= (ch->sibling->status & 0x3f) << 6;
782
ch->sibling->status &= SYNC;
784
qemu_irq_lower(ch->irq);
787
case 0x08: /* SYS_DMA_CSSA_L_CH0 */
788
*value = ch->addr[0] & 0x0000ffff;
791
case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
792
*value = ch->addr[0] >> 16;
795
case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
796
*value = ch->addr[1] & 0x0000ffff;
799
case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
800
*value = ch->addr[1] >> 16;
803
case 0x10: /* SYS_DMA_CEN_CH0 */
804
*value = ch->elements;
807
case 0x12: /* SYS_DMA_CFN_CH0 */
811
case 0x14: /* SYS_DMA_CFI_CH0 */
812
*value = ch->frame_index[0];
815
case 0x16: /* SYS_DMA_CEI_CH0 */
816
*value = ch->element_index[0];
819
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
820
if (ch->omap_3_1_compatible_disable)
821
*value = ch->active_set.src & 0xffff; /* CSAC */
826
case 0x1a: /* DMA_CDAC */
827
*value = ch->active_set.dest & 0xffff; /* CDAC */
830
case 0x1c: /* DMA_CDEI */
831
*value = ch->element_index[1];
834
case 0x1e: /* DMA_CDFI */
835
*value = ch->frame_index[1];
838
case 0x20: /* DMA_COLOR_L */
839
*value = ch->color & 0xffff;
842
case 0x22: /* DMA_COLOR_U */
843
*value = ch->color >> 16;
846
case 0x24: /* DMA_CCR2 */
847
*value = (ch->bs << 2) |
848
(ch->transparent_copy << 1) |
852
case 0x28: /* DMA_CLNK_CTRL */
853
*value = (ch->link_enabled << 15) |
854
(ch->link_next_ch & 0xf);
857
case 0x2a: /* DMA_LCH_CTRL */
858
*value = (ch->interleave_disabled << 15) |
868
static int omap_dma_ch_reg_write(struct omap_dma_s *s,
869
struct omap_dma_channel_s *ch, int reg, uint16_t value)
872
case 0x00: /* SYS_DMA_CSDP_CH0 */
873
ch->burst[1] = (value & 0xc000) >> 14;
874
ch->pack[1] = (value & 0x2000) >> 13;
875
ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
876
ch->burst[0] = (value & 0x0180) >> 7;
877
ch->pack[0] = (value & 0x0040) >> 6;
878
ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
879
ch->data_type = 1 << (value & 3);
880
if (ch->port[0] >= __omap_dma_port_last)
881
printf("%s: invalid DMA port %i\n", __FUNCTION__,
883
if (ch->port[1] >= __omap_dma_port_last)
884
printf("%s: invalid DMA port %i\n", __FUNCTION__,
886
if ((value & 3) == 3)
887
printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
890
case 0x02: /* SYS_DMA_CCR_CH0 */
891
ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
892
ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
893
ch->end_prog = (value & 0x0800) >> 11;
894
if (s->model >= omap_dma_3_2)
895
ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
896
ch->repeat = (value & 0x0200) >> 9;
897
ch->auto_init = (value & 0x0100) >> 8;
898
ch->priority = (value & 0x0040) >> 6;
899
ch->fs = (value & 0x0020) >> 5;
900
ch->sync = value & 0x001f;
903
omap_dma_enable_channel(s, ch);
905
omap_dma_disable_channel(s, ch);
908
omap_dma_channel_end_prog(s, ch);
912
case 0x04: /* SYS_DMA_CICR_CH0 */
913
ch->interrupts = value & 0x3f;
916
case 0x06: /* SYS_DMA_CSR_CH0 */
917
OMAP_RO_REG((target_phys_addr_t) reg);
920
case 0x08: /* SYS_DMA_CSSA_L_CH0 */
921
ch->addr[0] &= 0xffff0000;
922
ch->addr[0] |= value;
925
case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
926
ch->addr[0] &= 0x0000ffff;
927
ch->addr[0] |= (uint32_t) value << 16;
930
case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
931
ch->addr[1] &= 0xffff0000;
932
ch->addr[1] |= value;
935
case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
936
ch->addr[1] &= 0x0000ffff;
937
ch->addr[1] |= (uint32_t) value << 16;
940
case 0x10: /* SYS_DMA_CEN_CH0 */
941
ch->elements = value;
944
case 0x12: /* SYS_DMA_CFN_CH0 */
948
case 0x14: /* SYS_DMA_CFI_CH0 */
949
ch->frame_index[0] = (int16_t) value;
952
case 0x16: /* SYS_DMA_CEI_CH0 */
953
ch->element_index[0] = (int16_t) value;
956
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
957
OMAP_RO_REG((target_phys_addr_t) reg);
960
case 0x1c: /* DMA_CDEI */
961
ch->element_index[1] = (int16_t) value;
964
case 0x1e: /* DMA_CDFI */
965
ch->frame_index[1] = (int16_t) value;
968
case 0x20: /* DMA_COLOR_L */
969
ch->color &= 0xffff0000;
973
case 0x22: /* DMA_COLOR_U */
975
ch->color |= value << 16;
978
case 0x24: /* DMA_CCR2 */
979
ch->bs = (value >> 2) & 0x1;
980
ch->transparent_copy = (value >> 1) & 0x1;
981
ch->constant_fill = value & 0x1;
984
case 0x28: /* DMA_CLNK_CTRL */
985
ch->link_enabled = (value >> 15) & 0x1;
986
if (value & (1 << 14)) { /* Stop_Lnk */
987
ch->link_enabled = 0;
988
omap_dma_disable_channel(s, ch);
990
ch->link_next_ch = value & 0x1f;
993
case 0x2a: /* DMA_LCH_CTRL */
994
ch->interleave_disabled = (value >> 15) & 0x1;
995
ch->type = value & 0xf;
1004
static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1008
case 0xbc0: /* DMA_LCD_CSDP */
1009
s->brust_f2 = (value >> 14) & 0x3;
1010
s->pack_f2 = (value >> 13) & 0x1;
1011
s->data_type_f2 = (1 << ((value >> 11) & 0x3));
1012
s->brust_f1 = (value >> 7) & 0x3;
1013
s->pack_f1 = (value >> 6) & 0x1;
1014
s->data_type_f1 = (1 << ((value >> 0) & 0x3));
1017
case 0xbc2: /* DMA_LCD_CCR */
1018
s->mode_f2 = (value >> 14) & 0x3;
1019
s->mode_f1 = (value >> 12) & 0x3;
1020
s->end_prog = (value >> 11) & 0x1;
1021
s->omap_3_1_compatible_disable = (value >> 10) & 0x1;
1022
s->repeat = (value >> 9) & 0x1;
1023
s->auto_init = (value >> 8) & 0x1;
1024
s->running = (value >> 7) & 0x1;
1025
s->priority = (value >> 6) & 0x1;
1026
s->bs = (value >> 4) & 0x1;
1029
case 0xbc4: /* DMA_LCD_CTRL */
1030
s->dst = (value >> 8) & 0x1;
1031
s->src = ((value >> 6) & 0x3) << 1;
1033
/* Assume no bus errors and thus no BUS_ERROR irq bits. */
1034
s->interrupts = (value >> 1) & 1;
1035
s->dual = value & 1;
1038
case 0xbc8: /* TOP_B1_L */
1039
s->src_f1_top &= 0xffff0000;
1040
s->src_f1_top |= 0x0000ffff & value;
1043
case 0xbca: /* TOP_B1_U */
1044
s->src_f1_top &= 0x0000ffff;
1045
s->src_f1_top |= value << 16;
1048
case 0xbcc: /* BOT_B1_L */
1049
s->src_f1_bottom &= 0xffff0000;
1050
s->src_f1_bottom |= 0x0000ffff & value;
1053
case 0xbce: /* BOT_B1_U */
1054
s->src_f1_bottom &= 0x0000ffff;
1055
s->src_f1_bottom |= (uint32_t) value << 16;
1058
case 0xbd0: /* TOP_B2_L */
1059
s->src_f2_top &= 0xffff0000;
1060
s->src_f2_top |= 0x0000ffff & value;
1063
case 0xbd2: /* TOP_B2_U */
1064
s->src_f2_top &= 0x0000ffff;
1065
s->src_f2_top |= (uint32_t) value << 16;
1068
case 0xbd4: /* BOT_B2_L */
1069
s->src_f2_bottom &= 0xffff0000;
1070
s->src_f2_bottom |= 0x0000ffff & value;
1073
case 0xbd6: /* BOT_B2_U */
1074
s->src_f2_bottom &= 0x0000ffff;
1075
s->src_f2_bottom |= (uint32_t) value << 16;
1078
case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1079
s->element_index_f1 = value;
1082
case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1083
s->frame_index_f1 &= 0xffff0000;
1084
s->frame_index_f1 |= 0x0000ffff & value;
1087
case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1088
s->frame_index_f1 &= 0x0000ffff;
1089
s->frame_index_f1 |= (uint32_t) value << 16;
1092
case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1093
s->element_index_f2 = value;
1096
case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1097
s->frame_index_f2 &= 0xffff0000;
1098
s->frame_index_f2 |= 0x0000ffff & value;
1101
case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1102
s->frame_index_f2 &= 0x0000ffff;
1103
s->frame_index_f2 |= (uint32_t) value << 16;
1106
case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1107
s->elements_f1 = value;
1110
case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1111
s->frames_f1 = value;
1114
case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1115
s->elements_f2 = value;
1118
case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1119
s->frames_f2 = value;
1122
case 0xbea: /* DMA_LCD_LCH_CTRL */
1123
s->lch_type = value & 0xf;
1132
static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1136
case 0xbc0: /* DMA_LCD_CSDP */
1137
*ret = (s->brust_f2 << 14) |
1138
(s->pack_f2 << 13) |
1139
((s->data_type_f2 >> 1) << 11) |
1140
(s->brust_f1 << 7) |
1142
((s->data_type_f1 >> 1) << 0);
1145
case 0xbc2: /* DMA_LCD_CCR */
1146
*ret = (s->mode_f2 << 14) |
1147
(s->mode_f1 << 12) |
1148
(s->end_prog << 11) |
1149
(s->omap_3_1_compatible_disable << 10) |
1151
(s->auto_init << 8) |
1153
(s->priority << 6) |
1157
case 0xbc4: /* DMA_LCD_CTRL */
1158
qemu_irq_lower(s->irq);
1159
*ret = (s->dst << 8) |
1160
((s->src & 0x6) << 5) |
1161
(s->condition << 3) |
1162
(s->interrupts << 1) |
1166
case 0xbc8: /* TOP_B1_L */
1167
*ret = s->src_f1_top & 0xffff;
1170
case 0xbca: /* TOP_B1_U */
1171
*ret = s->src_f1_top >> 16;
1174
case 0xbcc: /* BOT_B1_L */
1175
*ret = s->src_f1_bottom & 0xffff;
1178
case 0xbce: /* BOT_B1_U */
1179
*ret = s->src_f1_bottom >> 16;
1182
case 0xbd0: /* TOP_B2_L */
1183
*ret = s->src_f2_top & 0xffff;
1186
case 0xbd2: /* TOP_B2_U */
1187
*ret = s->src_f2_top >> 16;
1190
case 0xbd4: /* BOT_B2_L */
1191
*ret = s->src_f2_bottom & 0xffff;
1194
case 0xbd6: /* BOT_B2_U */
1195
*ret = s->src_f2_bottom >> 16;
1198
case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1199
*ret = s->element_index_f1;
1202
case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1203
*ret = s->frame_index_f1 & 0xffff;
1206
case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1207
*ret = s->frame_index_f1 >> 16;
1210
case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1211
*ret = s->element_index_f2;
1214
case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1215
*ret = s->frame_index_f2 & 0xffff;
1218
case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1219
*ret = s->frame_index_f2 >> 16;
1222
case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1223
*ret = s->elements_f1;
1226
case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1227
*ret = s->frames_f1;
1230
case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1231
*ret = s->elements_f2;
1234
case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1235
*ret = s->frames_f2;
1238
case 0xbea: /* DMA_LCD_LCH_CTRL */
1248
static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1252
case 0x300: /* SYS_DMA_LCD_CTRL */
1253
s->src = (value & 0x40) ? imif : emiff;
1255
/* Assume no bus errors and thus no BUS_ERROR irq bits. */
1256
s->interrupts = (value >> 1) & 1;
1257
s->dual = value & 1;
1260
case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1261
s->src_f1_top &= 0xffff0000;
1262
s->src_f1_top |= 0x0000ffff & value;
1265
case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1266
s->src_f1_top &= 0x0000ffff;
1267
s->src_f1_top |= value << 16;
1270
case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1271
s->src_f1_bottom &= 0xffff0000;
1272
s->src_f1_bottom |= 0x0000ffff & value;
1275
case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1276
s->src_f1_bottom &= 0x0000ffff;
1277
s->src_f1_bottom |= value << 16;
1280
case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1281
s->src_f2_top &= 0xffff0000;
1282
s->src_f2_top |= 0x0000ffff & value;
1285
case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1286
s->src_f2_top &= 0x0000ffff;
1287
s->src_f2_top |= value << 16;
1290
case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1291
s->src_f2_bottom &= 0xffff0000;
1292
s->src_f2_bottom |= 0x0000ffff & value;
1295
case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1296
s->src_f2_bottom &= 0x0000ffff;
1297
s->src_f2_bottom |= value << 16;
1306
static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1312
case 0x300: /* SYS_DMA_LCD_CTRL */
1315
qemu_irq_lower(s->irq);
1316
*ret = ((s->src == imif) << 6) | (i << 3) |
1317
(s->interrupts << 1) | s->dual;
1320
case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1321
*ret = s->src_f1_top & 0xffff;
1324
case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1325
*ret = s->src_f1_top >> 16;
1328
case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1329
*ret = s->src_f1_bottom & 0xffff;
1332
case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1333
*ret = s->src_f1_bottom >> 16;
1336
case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1337
*ret = s->src_f2_top & 0xffff;
1340
case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1341
*ret = s->src_f2_top >> 16;
1344
case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1345
*ret = s->src_f2_bottom & 0xffff;
1348
case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1349
*ret = s->src_f2_bottom >> 16;
1358
static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value)
1361
case 0x400: /* SYS_DMA_GCR */
1365
case 0x404: /* DMA_GSCR */
1367
omap_dma_disable_3_1_mapping(s);
1369
omap_dma_enable_3_1_mapping(s);
1372
case 0x408: /* DMA_GRST */
1374
omap_dma_reset(s->dma);
1383
static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
1387
case 0x400: /* SYS_DMA_GCR */
1391
case 0x404: /* DMA_GSCR */
1392
*ret = s->omap_3_1_mapping_disabled << 3;
1395
case 0x408: /* DMA_GRST */
1399
case 0x442: /* DMA_HW_ID */
1400
case 0x444: /* DMA_PCh2_ID */
1401
case 0x446: /* DMA_PCh0_ID */
1402
case 0x448: /* DMA_PCh1_ID */
1403
case 0x44a: /* DMA_PChG_ID */
1404
case 0x44c: /* DMA_PChD_ID */
1408
case 0x44e: /* DMA_CAPS_0_U */
1409
*ret = (s->caps[0] >> 16) & 0xffff;
1411
case 0x450: /* DMA_CAPS_0_L */
1412
*ret = (s->caps[0] >> 0) & 0xffff;
1415
case 0x452: /* DMA_CAPS_1_U */
1416
*ret = (s->caps[1] >> 16) & 0xffff;
1418
case 0x454: /* DMA_CAPS_1_L */
1419
*ret = (s->caps[1] >> 0) & 0xffff;
1422
case 0x456: /* DMA_CAPS_2 */
1426
case 0x458: /* DMA_CAPS_3 */
1430
case 0x45a: /* DMA_CAPS_4 */
1434
case 0x460: /* DMA_PCh2_SR */
1435
case 0x480: /* DMA_PCh0_SR */
1436
case 0x482: /* DMA_PCh1_SR */
1437
case 0x4c0: /* DMA_PChD_SR_0 */
1438
printf("%s: Physical Channel Status Registers not implemented.\n",
1449
static uint64_t omap_dma_read(void *opaque, target_phys_addr_t addr,
1452
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1457
return omap_badwidth_read16(opaque, addr);
1461
case 0x300 ... 0x3fe:
1462
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1463
if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))
1468
case 0x000 ... 0x2fe:
1470
ch = (addr >> 6) & 0x0f;
1471
if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
1475
case 0x404 ... 0x4fe:
1476
if (s->model <= omap_dma_3_1)
1480
if (omap_dma_sys_read(s, addr, &ret))
1484
case 0xb00 ... 0xbfe:
1485
if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1486
if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))
1497
static void omap_dma_write(void *opaque, target_phys_addr_t addr,
1498
uint64_t value, unsigned size)
1500
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1504
return omap_badwidth_write16(opaque, addr, value);
1508
case 0x300 ... 0x3fe:
1509
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1510
if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))
1515
case 0x000 ... 0x2fe:
1517
ch = (addr >> 6) & 0x0f;
1518
if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
1522
case 0x404 ... 0x4fe:
1523
if (s->model <= omap_dma_3_1)
1527
if (omap_dma_sys_write(s, addr, value))
1531
case 0xb00 ... 0xbfe:
1532
if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1533
if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))
1543
static const MemoryRegionOps omap_dma_ops = {
1544
.read = omap_dma_read,
1545
.write = omap_dma_write,
1546
.endianness = DEVICE_NATIVE_ENDIAN,
1549
static void omap_dma_request(void *opaque, int drq, int req)
1551
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1552
/* The request pins are level triggered in QEMU. */
1554
if (~s->dma->drqbmp & (1 << drq)) {
1555
s->dma->drqbmp |= 1 << drq;
1556
omap_dma_process_request(s, drq);
1559
s->dma->drqbmp &= ~(1 << drq);
1562
/* XXX: this won't be needed once soc_dma knows about clocks. */
1563
static void omap_dma_clk_update(void *opaque, int line, int on)
1565
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1568
s->dma->freq = omap_clk_getrate(s->clk);
1570
for (i = 0; i < s->chans; i ++)
1571
if (s->ch[i].active)
1572
soc_dma_set_request(s->ch[i].dma, on);
1575
static void omap_dma_setcaps(struct omap_dma_s *s)
1583
/* XXX Only available for sDMA */
1585
(1 << 19) | /* Constant Fill Capability */
1586
(1 << 18); /* Transparent BLT Capability */
1588
(1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */
1590
(1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */
1591
(1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */
1592
(1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */
1593
(1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */
1594
(1 << 4) | /* DST_CONST_ADRS_CPBLTY */
1595
(1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */
1596
(1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */
1597
(1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */
1598
(1 << 0); /* SRC_CONST_ADRS_CPBLTY */
1600
(1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */
1601
(1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */
1602
(1 << 5) | /* CHANNEL_CHAINING_CPBLTY */
1603
(1 << 4) | /* LCh_INTERLEAVE_CPBLTY */
1604
(1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */
1605
(1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */
1606
(1 << 1) | /* FRAME_SYNCHR_CPBLTY */
1607
(1 << 0); /* ELMNT_SYNCHR_CPBLTY */
1609
(1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */
1610
(1 << 6) | /* SYNC_STATUS_CPBLTY */
1611
(1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */
1612
(1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */
1613
(1 << 3) | /* FRAME_INTERRUPT_CPBLTY */
1614
(1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */
1615
(1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */
1616
(1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */
1621
struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
1622
MemoryRegion *sysmem,
1623
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
1624
enum omap_dma_model model)
1626
int num_irqs, memsize, i;
1627
struct omap_dma_s *s = (struct omap_dma_s *)
1628
g_malloc0(sizeof(struct omap_dma_s));
1630
if (model <= omap_dma_3_1) {
1640
s->lcd_ch.irq = lcd_irq;
1641
s->lcd_ch.mpu = mpu;
1643
s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16);
1644
s->dma->freq = omap_clk_getrate(clk);
1645
s->dma->transfer_fn = omap_dma_transfer_generic;
1646
s->dma->setup_fn = omap_dma_transfer_setup;
1647
s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
1651
s->ch[num_irqs].irq = irqs[num_irqs];
1652
for (i = 0; i < 3; i ++) {
1653
s->ch[i].sibling = &s->ch[i + 6];
1654
s->ch[i + 6].sibling = &s->ch[i];
1656
for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) {
1657
s->ch[i].dma = &s->dma->ch[i];
1658
s->dma->ch[i].opaque = &s->ch[i];
1661
omap_dma_setcaps(s);
1662
omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
1663
omap_dma_reset(s->dma);
1664
omap_dma_clk_update(s, 0, 1);
1666
memory_region_init_io(&s->iomem, &omap_dma_ops, s, "omap.dma", memsize);
1667
memory_region_add_subregion(sysmem, base, &s->iomem);
1669
mpu->drq = s->dma->drq;
1674
static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
1676
struct omap_dma_channel_s *ch = s->ch;
1679
for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1)
1682
ch->cstatus |= ch->status;
1685
if ((s->irqstat[0] |= s->irqen[0] & bmp))
1686
qemu_irq_raise(s->irq[0]);
1687
if ((s->irqstat[1] |= s->irqen[1] & bmp))
1688
qemu_irq_raise(s->irq[1]);
1689
if ((s->irqstat[2] |= s->irqen[2] & bmp))
1690
qemu_irq_raise(s->irq[2]);
1691
if ((s->irqstat[3] |= s->irqen[3] & bmp))
1692
qemu_irq_raise(s->irq[3]);
1695
static uint64_t omap_dma4_read(void *opaque, target_phys_addr_t addr,
1698
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1699
int irqn = 0, chnum;
1700
struct omap_dma_channel_s *ch;
1703
return omap_badwidth_read16(opaque, addr);
1707
case 0x00: /* DMA4_REVISION */
1710
case 0x14: /* DMA4_IRQSTATUS_L3 */
1712
case 0x10: /* DMA4_IRQSTATUS_L2 */
1714
case 0x0c: /* DMA4_IRQSTATUS_L1 */
1716
case 0x08: /* DMA4_IRQSTATUS_L0 */
1717
return s->irqstat[irqn];
1719
case 0x24: /* DMA4_IRQENABLE_L3 */
1721
case 0x20: /* DMA4_IRQENABLE_L2 */
1723
case 0x1c: /* DMA4_IRQENABLE_L1 */
1725
case 0x18: /* DMA4_IRQENABLE_L0 */
1726
return s->irqen[irqn];
1728
case 0x28: /* DMA4_SYSSTATUS */
1729
return 1; /* RESETDONE */
1731
case 0x2c: /* DMA4_OCP_SYSCONFIG */
1734
case 0x64: /* DMA4_CAPS_0 */
1736
case 0x6c: /* DMA4_CAPS_2 */
1738
case 0x70: /* DMA4_CAPS_3 */
1740
case 0x74: /* DMA4_CAPS_4 */
1743
case 0x78: /* DMA4_GCR */
1746
case 0x80 ... 0xfff:
1748
chnum = addr / 0x60;
1750
addr -= chnum * 0x60;
1758
/* Per-channel registers */
1760
case 0x00: /* DMA4_CCR */
1761
return (ch->buf_disable << 25) |
1762
(ch->src_sync << 24) |
1763
(ch->prefetch << 23) |
1764
((ch->sync & 0x60) << 14) |
1766
(ch->transparent_copy << 17) |
1767
(ch->constant_fill << 16) |
1768
(ch->mode[1] << 14) |
1769
(ch->mode[0] << 12) |
1770
(0 << 10) | (0 << 9) |
1771
(ch->suspend << 8) |
1773
(ch->priority << 6) |
1774
(ch->fs << 5) | (ch->sync & 0x1f);
1776
case 0x04: /* DMA4_CLNK_CTRL */
1777
return (ch->link_enabled << 15) | ch->link_next_ch;
1779
case 0x08: /* DMA4_CICR */
1780
return ch->interrupts;
1782
case 0x0c: /* DMA4_CSR */
1785
case 0x10: /* DMA4_CSDP */
1786
return (ch->endian[0] << 21) |
1787
(ch->endian_lock[0] << 20) |
1788
(ch->endian[1] << 19) |
1789
(ch->endian_lock[1] << 18) |
1790
(ch->write_mode << 16) |
1791
(ch->burst[1] << 14) |
1792
(ch->pack[1] << 13) |
1793
(ch->translate[1] << 9) |
1794
(ch->burst[0] << 7) |
1795
(ch->pack[0] << 6) |
1796
(ch->translate[0] << 2) |
1797
(ch->data_type >> 1);
1799
case 0x14: /* DMA4_CEN */
1800
return ch->elements;
1802
case 0x18: /* DMA4_CFN */
1805
case 0x1c: /* DMA4_CSSA */
1808
case 0x20: /* DMA4_CDSA */
1811
case 0x24: /* DMA4_CSEI */
1812
return ch->element_index[0];
1814
case 0x28: /* DMA4_CSFI */
1815
return ch->frame_index[0];
1817
case 0x2c: /* DMA4_CDEI */
1818
return ch->element_index[1];
1820
case 0x30: /* DMA4_CDFI */
1821
return ch->frame_index[1];
1823
case 0x34: /* DMA4_CSAC */
1824
return ch->active_set.src & 0xffff;
1826
case 0x38: /* DMA4_CDAC */
1827
return ch->active_set.dest & 0xffff;
1829
case 0x3c: /* DMA4_CCEN */
1830
return ch->active_set.element;
1832
case 0x40: /* DMA4_CCFN */
1833
return ch->active_set.frame;
1835
case 0x44: /* DMA4_COLOR */
1836
/* XXX only in sDMA */
1845
static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
1846
uint64_t value, unsigned size)
1848
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1849
int chnum, irqn = 0;
1850
struct omap_dma_channel_s *ch;
1853
return omap_badwidth_write16(opaque, addr, value);
1857
case 0x14: /* DMA4_IRQSTATUS_L3 */
1859
case 0x10: /* DMA4_IRQSTATUS_L2 */
1861
case 0x0c: /* DMA4_IRQSTATUS_L1 */
1863
case 0x08: /* DMA4_IRQSTATUS_L0 */
1864
s->irqstat[irqn] &= ~value;
1865
if (!s->irqstat[irqn])
1866
qemu_irq_lower(s->irq[irqn]);
1869
case 0x24: /* DMA4_IRQENABLE_L3 */
1871
case 0x20: /* DMA4_IRQENABLE_L2 */
1873
case 0x1c: /* DMA4_IRQENABLE_L1 */
1875
case 0x18: /* DMA4_IRQENABLE_L0 */
1876
s->irqen[irqn] = value;
1879
case 0x2c: /* DMA4_OCP_SYSCONFIG */
1880
if (value & 2) /* SOFTRESET */
1881
omap_dma_reset(s->dma);
1882
s->ocp = value & 0x3321;
1883
if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */
1884
fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__);
1887
case 0x78: /* DMA4_GCR */
1888
s->gcr = value & 0x00ff00ff;
1889
if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */
1890
fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__);
1893
case 0x80 ... 0xfff:
1895
chnum = addr / 0x60;
1897
addr -= chnum * 0x60;
1900
case 0x00: /* DMA4_REVISION */
1901
case 0x28: /* DMA4_SYSSTATUS */
1902
case 0x64: /* DMA4_CAPS_0 */
1903
case 0x6c: /* DMA4_CAPS_2 */
1904
case 0x70: /* DMA4_CAPS_3 */
1905
case 0x74: /* DMA4_CAPS_4 */
1914
/* Per-channel registers */
1916
case 0x00: /* DMA4_CCR */
1917
ch->buf_disable = (value >> 25) & 1;
1918
ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */
1919
if (ch->buf_disable && !ch->src_sync)
1920
fprintf(stderr, "%s: Buffering disable is not allowed in "
1921
"destination synchronised mode\n", __FUNCTION__);
1922
ch->prefetch = (value >> 23) & 1;
1923
ch->bs = (value >> 18) & 1;
1924
ch->transparent_copy = (value >> 17) & 1;
1925
ch->constant_fill = (value >> 16) & 1;
1926
ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
1927
ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
1928
ch->suspend = (value & 0x0100) >> 8;
1929
ch->priority = (value & 0x0040) >> 6;
1930
ch->fs = (value & 0x0020) >> 5;
1931
if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1])
1932
fprintf(stderr, "%s: For a packet transfer at least one port "
1933
"must be constant-addressed\n", __FUNCTION__);
1934
ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060);
1935
/* XXX must be 0x01 for CamDMA */
1938
omap_dma_enable_channel(s, ch);
1940
omap_dma_disable_channel(s, ch);
1944
case 0x04: /* DMA4_CLNK_CTRL */
1945
ch->link_enabled = (value >> 15) & 0x1;
1946
ch->link_next_ch = value & 0x1f;
1949
case 0x08: /* DMA4_CICR */
1950
ch->interrupts = value & 0x09be;
1953
case 0x0c: /* DMA4_CSR */
1954
ch->cstatus &= ~value;
1957
case 0x10: /* DMA4_CSDP */
1958
ch->endian[0] =(value >> 21) & 1;
1959
ch->endian_lock[0] =(value >> 20) & 1;
1960
ch->endian[1] =(value >> 19) & 1;
1961
ch->endian_lock[1] =(value >> 18) & 1;
1962
if (ch->endian[0] != ch->endian[1])
1963
fprintf(stderr, "%s: DMA endiannes conversion enable attempt\n",
1965
ch->write_mode = (value >> 16) & 3;
1966
ch->burst[1] = (value & 0xc000) >> 14;
1967
ch->pack[1] = (value & 0x2000) >> 13;
1968
ch->translate[1] = (value & 0x1e00) >> 9;
1969
ch->burst[0] = (value & 0x0180) >> 7;
1970
ch->pack[0] = (value & 0x0040) >> 6;
1971
ch->translate[0] = (value & 0x003c) >> 2;
1972
if (ch->translate[0] | ch->translate[1])
1973
fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n",
1975
ch->data_type = 1 << (value & 3);
1976
if ((value & 3) == 3)
1977
printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
1980
case 0x14: /* DMA4_CEN */
1982
ch->elements = value & 0xffffff;
1985
case 0x18: /* DMA4_CFN */
1986
ch->frames = value & 0xffff;
1990
case 0x1c: /* DMA4_CSSA */
1991
ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
1995
case 0x20: /* DMA4_CDSA */
1996
ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
2000
case 0x24: /* DMA4_CSEI */
2001
ch->element_index[0] = (int16_t) value;
2005
case 0x28: /* DMA4_CSFI */
2006
ch->frame_index[0] = (int32_t) value;
2010
case 0x2c: /* DMA4_CDEI */
2011
ch->element_index[1] = (int16_t) value;
2015
case 0x30: /* DMA4_CDFI */
2016
ch->frame_index[1] = (int32_t) value;
2020
case 0x44: /* DMA4_COLOR */
2021
/* XXX only in sDMA */
2025
case 0x34: /* DMA4_CSAC */
2026
case 0x38: /* DMA4_CDAC */
2027
case 0x3c: /* DMA4_CCEN */
2028
case 0x40: /* DMA4_CCFN */
2037
static const MemoryRegionOps omap_dma4_ops = {
2038
.read = omap_dma4_read,
2039
.write = omap_dma4_write,
2040
.endianness = DEVICE_NATIVE_ENDIAN,
2043
struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
2044
MemoryRegion *sysmem,
2045
struct omap_mpu_state_s *mpu, int fifo,
2046
int chans, omap_clk iclk, omap_clk fclk)
2049
struct omap_dma_s *s = (struct omap_dma_s *)
2050
g_malloc0(sizeof(struct omap_dma_s));
2052
s->model = omap_dma_4;
2057
s->dma = soc_dma_init(s->chans);
2058
s->dma->freq = omap_clk_getrate(fclk);
2059
s->dma->transfer_fn = omap_dma_transfer_generic;
2060
s->dma->setup_fn = omap_dma_transfer_setup;
2061
s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 64);
2063
for (i = 0; i < s->chans; i ++) {
2064
s->ch[i].dma = &s->dma->ch[i];
2065
s->dma->ch[i].opaque = &s->ch[i];
2068
memcpy(&s->irq, irqs, sizeof(s->irq));
2069
s->intr_update = omap_dma_interrupts_4_update;
2071
omap_dma_setcaps(s);
2072
omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
2073
omap_dma_reset(s->dma);
2074
omap_dma_clk_update(s, 0, !!s->dma->freq);
2076
memory_region_init_io(&s->iomem, &omap_dma4_ops, s, "omap.dma4", 0x1000);
2077
memory_region_add_subregion(sysmem, base, &s->iomem);
2079
mpu->drq = s->dma->drq;
2084
struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct soc_dma_s *dma)
2086
struct omap_dma_s *s = dma->opaque;
added
removed
.pc/patches-arm-1.2.0/0007-hw-omap_dma.c-Support-more-than-64-channels-of-DMA.patch/hw/omap_dma.c
