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* Copyright (c) 2012 Jan Vesely
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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/** @addtogroup genarch
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* @brief Texas Instruments AM/DM37x SDRAM Memory Scheduler.
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#ifndef KERN_AMDM37x_DISPC_H_
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#define KERN_AMDM37x_DISPC_H_
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/* AMDM37x TRM p. 1813 */
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#define AMDM37x_DISPC_BASE_ADDRESS 0x48050400
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#define AMDM37x_DISPC_SIZE 1024
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#define __paddname(line) PADD32_ ## line
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#define _paddname(line) __paddname(line)
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#define PADD32(count) uint32_t _paddname(__LINE__)[count]
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const ioport32_t revision;
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#define AMDM37X_DISPC_REVISION_MASK 0xff
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#define AMDM37X_DISPC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0)
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#define AMDM37X_DISPC_SYSCONFIG_SOFTRESET_FLAG (1 << 1)
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#define AMDM37X_DISPC_SYSCONFIG_ENWAKEUP_FLAG (1 << 2)
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#define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_MASK 0x3
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#define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_SHIFT 3
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#define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_MASK 0x3
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#define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_SHIFT 8
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#define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_MASK 0x3
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#define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_SHIFT 12
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const ioport32_t sysstatus;
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#define AMDM37X_DISPC_SYSSTATUS_RESETDONE_FLAG (1 << 0)
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#define AMDM37X_DISPC_IRQ_FRAMEDONE_FLAG (1 << 0)
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#define AMDM37X_DISPC_IRQ_VSYNC_FLAG (1 << 1)
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#define AMDM37X_DISPC_IRQ_EVSYNCEVEN_FLAG (1 << 2)
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#define AMDM37X_DISPC_IRQ_EVSYNCODD_FLAG (1 << 3)
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#define AMDM37X_DISPC_IRQ_ACBIASCOUNTSTATUS_FLAG (1 << 4)
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#define AMDM37X_DISPC_IRQ_PROGRAMMEDLINENUMBER_FLAG (1 << 5)
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#define AMDM37X_DISPC_IRQ_GFXFIFOUNDERFLOW_FLAG (1 << 6)
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#define AMDM37X_DISPC_IRQ_GFXENDWINDOW_FLAG (1 << 7)
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#define AMDM37X_DISPC_IRQ_PALETTEGAMMALOADING_FLAG (1 << 8)
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#define AMDM37X_DISPC_IRQ_OPCERROR_FLAG (1 << 9)
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#define AMDM37X_DISPC_IRQ_VID1FIFOUNDERFLOW_FLAG (1 << 10)
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#define AMDM37X_DISPC_IRQ_VID1ENDWINDOW_FLAG (1 << 11)
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#define AMDM37X_DISPC_IRQ_VID2FIFOUNDERFLOW_FLAG (1 << 12)
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#define AMDM37X_DISPC_IRQ_VID2ENDWINDOW_FLAG (1 << 13)
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#define AMDM37X_DISPC_IRQ_SYNCLOST_FLAG (1 << 14)
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#define AMDM37X_DISPC_IRQ_SYNCLOSTDIGITAL_FLAG (1 << 15)
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#define AMDM37X_DISPC_IRQ_WAKEUP_FLAG (1 << 16)
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#define AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG (1 << 0)
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#define AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG (1 << 1)
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#define AMDM37X_DISPC_CONTROL_MONOCOLOR_FLAG (1 << 2)
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#define AMDM37X_DISPC_CONTROL_STNTFT_FLAG (1 << 3)
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#define AMDM37X_DISPC_CONTROL_M8B_FLAG (1 << 4)
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#define AMDM37X_DISPC_CONTROL_GOLCD_FLAG (1 << 5)
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#define AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG (1 << 6)
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#define AMDM37X_DISPC_CONTROL_STDITHERENABLE_FLAG (1 << 7)
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#define AMDM37X_DISPC_CONTROL_TFTDATALINES_MASK 0x3
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#define AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT 8
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#define AMDM37X_DISPC_CONTROL_TFTDATALINES_12B 0
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#define AMDM37X_DISPC_CONTROL_TFTDATALINES_16B 1
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#define AMDM37X_DISPC_CONTROL_TFTDATALINES_18B 2
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#define AMDM37X_DISPC_CONTROL_TFTDATALINES_24B 3
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#define AMDM37X_DISPC_CONTROL_STALLMODE_FLAG (1 << 11)
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#define AMDM37X_DISPC_CONTROL_OVERLAYOPTIMIZATION_FLAG (1 << 12)
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#define AMDM37X_DISPC_CONTROL_GPIN0_FLAG (1 << 13)
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#define AMDM37X_DISPC_CONTROL_GPIN1_FLAG (1 << 14)
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#define AMDM37X_DISPC_CONTROL_GPOUT0_FLAG (1 << 15)
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#define AMDM37X_DISPC_CONTROL_GPOUT1_FLAG (1 << 16)
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#define AMDM37X_DISPC_CONTROL_HT_MASK 0x7
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#define AMDM37X_DISPC_CONTROL_HT_SHIFT 17
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#define AMDM37X_DISPC_CONTROL_TDMENABLE_FLAG (1 << 20)
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#define AMDM37X_DISPC_CONTROL_TDMPARALLELMODE_MASK 0x3
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#define AMDM37X_DISPC_CONTROL_TDMPARELLELMODE_SHIFT 21
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#define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_MASK 0x3
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#define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_SHIFT 23
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#define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_MASK 0x3
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#define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_SHIFT 25
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#define AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG (1 << 27)
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#define AMDM37X_DISPC_CONTROL_LCDENABLESIGNAL_FLAG (1 << 28)
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#define AMDM37X_DISPC_CONTROL_KCDENABLEPOL_FLAG (1 << 29)
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#define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK 0x3
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#define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT 30
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#define AMDM37X_DISPC_CONFIG_PIXELGATED_FLAG (1 << 0)
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#define AMDM37X_DISPC_CONFIG_LOADMODE_MASK 0x3
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#define AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT 1
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#define AMDM37X_DISPC_CONFIG_LOADMODE_PGDATAEVERYFRAME 0x0
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#define AMDM37X_DISPC_CONFIG_LOADMODE_PGUSER 0x1
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#define AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME 0x2
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#define AMDM37X_DISPC_CONFIG_LOADMODE_PGDFIRSTFRAME 0x3
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#define AMDM37X_DISPC_CONFIG_PALETTEGAMMATABLE_FLAG (1 << 3)
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#define AMDM37X_DISPC_CONFIG_PIXELDATAGATED_FLAG (1 << 4)
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#define AMDM37X_DISPC_CONFIG_PIXELCLOCKGATED_FLAG (1 << 5)
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#define AMDM37X_DISPC_CONFIG_HSYNCGATED_FLAG (1 << 6)
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#define AMDM37X_DISPC_CONFIG_VSYNCGATED_FLAG (1 << 7)
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#define AMDM37X_DISPC_CONFIG_ACBIASGATED_FLAG (1 << 8)
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#define AMDM37X_DISPC_CONFIG_FUNCGATED_FLAG (1 << 9)
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#define AMDM37X_DISPC_CONFIG_TCKLCDENABLE_FLAG (1 << 10)
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#define AMDM37X_DISPC_CONFIG_TCKLCDSELECTION_FLAG (1 << 11)
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#define AMDM37X_DISPC_CONFIG_TCKDIGENABLE_FLAG (1 << 12)
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#define AMDM37X_DISPC_CONFIG_TCKDIGSELECTION_FLAG (1 << 13)
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#define AMDM37X_DISPC_CONFIG_FIFOMERGE_FLAG (1 << 14)
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#define AMDM37X_DISPC_CONFIG_CPR_FLAG (1 << 15)
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#define AMDM37X_DISPC_CONFIG_FIFOHANDCHECK_FLAG (1 << 16)
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#define AMDM37X_DISPC_CONFIG_FIFOFILLING_FLAG (1 << 17)
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#define AMDM37X_DISPC_CONFIG_LCDPALPHABLENDERENABLDE_FLAG (1 << 18)
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#define AMDM37X_DISPC_CONFIG_TVALPHABLENDERENABLE_FLAG (1 << 19)
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ioport32_t default_color[2];
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ioport32_t trans_color[2];
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#define AMDM37X_DISPC_COLOR_MASK 0xffffff
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const ioport32_t line_status;
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ioport32_t line_number;
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#define AMDM37X_DISPC_LINE_NUMBER_MASK 0x3ff
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#define AMDM37X_DISPC_TIMING_H_HSW_MASK 0xff
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#define AMDM37X_DISPC_TIMING_H_HSW_SHIFT 0
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#define AMDM37X_DISPC_TIMING_H_HFP_MASK 0xfff
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#define AMDM37X_DISPC_TIMING_H_HFP_SHIFT 8
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#define AMDM37X_DISPC_TIMING_H_HBP_MASK 0xfff
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#define AMDM37X_DISPC_TIMING_H_HBP_SHIFT 20
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#define AMDM37X_DISPC_TIMING_V_VSW_MASK 0xff
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#define AMDM37X_DISPC_TIMING_V_VSW_SHIFT 0
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#define AMDM37X_DISPC_TIMING_V_VFP_MASK 0xfff
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#define AMDM37X_DISPC_TIMING_V_VFP_SHIFT 8
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#define AMDM37X_DISPC_TIMING_V_VBP_MASK 0xfff
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#define AMDM37X_DISPC_TIMING_V_VBP_SHIFT 20
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#define AMDM37X_DISPC_POL_FREQ_ACB_MASK 0xff
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#define AMDM37X_DISPC_POL_FREQ_ACB_SHIFT 0
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#define AMDM37X_DISPC_POL_FREQ_ACBI_MASK 0xf
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#define AMDM37X_DISPC_POL_FREQ_ACBI_SHIFT 8
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#define AMDM37X_DISPC_POL_FREQ_IVS_FLAG (1 << 12)
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#define AMDM37X_DISPC_POL_FREQ_IHS_FLAG (1 << 13)
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#define AMDM37X_DISPC_POL_FREQ_IPC_FLAG (1 << 14)
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#define AMDM37X_DISPC_POL_FREQ_IEO_FLAG (1 << 15)
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#define AMDM37X_DISPC_POL_FREQ_RF_FLAG (1 << 16)
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#define AMDM37X_DISPC_POL_FREQ_ONOFF_FLAG (1 << 17)
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#define AMDM37X_DISPC_DIVISOR_PCD_MASK 0xff
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#define AMDM37X_DISPC_DIVISOR_PCD_SHIFT 0
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#define AMDM37X_DISPC_DIVISOR_LCD_MASK 0xff
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#define AMDM37X_DISPC_DIVISOR_LCD_SHIFT 16
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ioport32_t global_alpha;
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#define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_MASK 0xff
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#define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_SHIFT 0
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#define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_MASK 0xff
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#define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_SHIFT 16
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#define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_MASK 0x7ff
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#define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_SHIFT 0
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#define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_MASK 0x7ff
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#define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_SHIFT 16
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#define AMDM37X_DISPC_SIZE_WIDTH_MASK 0x7ff
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#define AMDM37X_DISPC_SIZE_WIDTH_SHIFT 0
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#define AMDM37X_DISPC_SIZE_HEIGHT_MASK 0x7ff
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#define AMDM37X_DISPC_SIZE_HEIGHT_SHIFT 16
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ioport32_t attributes;
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG (1 << 0)
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_MASK 0xf
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT 1
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB16 0x5
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16 0x6
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24_32 0x8
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24 0x9
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB 0xc
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBA 0xd
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX 0xe
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_REPLICATIONENABLE_FLAG (1 << 5)
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_MASK 0x3
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_SHIFT 6
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT_FLAG (1 << 8)
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXNIBBLEMODE_FLAG (1 << 9)
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXENDIANNES_FLAG (1 << 10)
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXFIFOPRELOAD_FLAG (1 << 11)
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_MASK 0x3
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_SHIFT 12
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXARBITRATION_FLAG (1 << 14)
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXSELFREFRESH_FLAG (1 << 15)
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#define AMDM37X_DISPC_GFX_ATTRIBUTES_PREMULTIALPHA_FLAG (1 << 28)
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ioport32_t fifo_threshold;
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const ioport32_t fifo_size_status;
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ioport32_t pixel_inc;
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ioport32_t window_skip;
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ioport32_t attributes;
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ioport32_t fifo_threshold;
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const ioport32_t fifo_size_status;
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ioport32_t pixel_inc;
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ioport32_t picture_size;
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ioport32_t conv_coef[5];
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ioport32_t data_cycle[3];
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ioport32_t vid_fir_coef_v[8];
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ioport32_t cpr_coef_r;
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ioport32_t cpr_coef_g;
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ioport32_t cpr_coef_b;
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ioport32_t gfx_preload;
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ioport32_t vid_preload[2];
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} __attribute__((packed)) amdm37x_dispc_regs_t;
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static inline void amdm37x_dispc_setup_fb(amdm37x_dispc_regs_t *regs,
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unsigned x, unsigned y, unsigned bpp, uintptr_t pa)
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/* Init sequence for dispc is in chapter 7.6.5.1.4 p. 1810,
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* no idea what parts of that work. */
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/* Disable all interrupts */
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/* Pixel format specifics*/
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uint32_t attrib_pixel_format = 0;
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uint32_t control_data_lanes = 0;
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attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX;
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control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B;
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attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24;
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control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B;
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attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16;
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control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_16B;
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const uint32_t size_reg =
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(((x - 1) & AMDM37X_DISPC_SIZE_WIDTH_MASK)
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<< AMDM37X_DISPC_SIZE_WIDTH_SHIFT) |
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(((y - 1) & AMDM37X_DISPC_SIZE_HEIGHT_MASK)
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<< AMDM37X_DISPC_SIZE_HEIGHT_SHIFT);
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/* modes taken from u-boot, for 1024x768 */
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// TODO replace magic values with actual correct values
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// regs->timing_h = 0x1a4024c9;
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// regs->timing_v = 0x02c00509;
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// regs->pol_freq = 0x00007028;
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// regs->divisor = 0x00010001;
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regs->size_lcd = size_reg;
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regs->size_dig = size_reg;
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/* Nice blue default color */
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regs->default_color[0] = 0x0000ff;
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regs->default_color[1] = 0x0000ff;
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/* Setup control register */
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uint32_t control = 0 |
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AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG |
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(control_data_lanes << AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT) |
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AMDM37X_DISPC_CONTROL_GPOUT0_FLAG |
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AMDM37X_DISPC_CONTROL_GPOUT1_FLAG;
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regs->control = control;
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/* No gamma stuff only data */
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uint32_t config = (AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME
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<< AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT);
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regs->config = config;
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/* Set framebuffer base address */
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regs->gfx.ba[0] = pa;
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regs->gfx.ba[1] = pa;
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regs->gfx.position = 0;
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regs->gfx.size = size_reg;
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/* Set pixel format */
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uint32_t attribs = 0 |
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(attrib_pixel_format << AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT);
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regs->gfx.attributes = attribs;
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/* 0x03ff03c0 is the default */
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regs->gfx.fifo_threshold = 0x03ff03c0;
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/* This value should be stride - width, 1 means next pixel i.e.
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regs->gfx.row_inc = 1;
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/* number of bytes to next pixel in BPP multiples */
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regs->gfx.pixel_inc = 1;
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/* only used if video is played over fb */
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regs->gfx.window_skip = 0;
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/* Gamma and palette table */
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regs->gfx.table_ba = 0;
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/* enable frame buffer graphics */
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regs->gfx.attributes |= AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG;
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/* Update register values */
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regs->control |= AMDM37X_DISPC_CONTROL_GOLCD_FLAG;
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regs->control |= AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG;
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regs->control |= AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG;
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regs->control |= AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG;
added
removed
kernel/genarch/include/drivers/amdm37x_dispc/amdm37x_dispc.h
