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- Committer: Michael Hope
- Date: 2010-08-26 22:19:29 UTC
- Revision ID: michael.hope@linaro.org-20100826221929-ppeg01mnpx34aqrp
Pulled in the initial versions
- files added:
- src
- src/reference
- src/reference/bionic
- src/reference/glibc
- src/reference/helpers
- src/reference/newlib
- src/reference/plain
added
removed
src/reference/bionic/memcmp16.S
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/*
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* Copyright (C) 2008 The Android Open Source Project
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/cpu-features.h>
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.text
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.global __memcmp16
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.type __memcmp16, %function
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.align 4
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/*
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* Optimized memcmp16() for ARM9.
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* This would not be optimal on XScale or ARM11, where more prefetching
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* and use of PLD will be needed.
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* The 2 major optimzations here are
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* (1) The main loop compares 16 bytes at a time
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* (2) The loads are scheduled in a way they won't stall
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*/
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__memcmp16:
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.fnstart
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PLD (r0, #0)
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PLD (r1, #0)
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/* take of the case where length is nul or the buffers are the same */
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cmp r0, r1
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cmpne r2, #0
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moveq r0, #0
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bxeq lr
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/* since r0 hold the result, move the first source
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* pointer somewhere else
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*/
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mov r3, r0
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/* make sure we have at least 12 words, this simplify things below
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* and avoid some overhead for small blocks
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*/
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cmp r2, #12
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bpl 0f
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/* small blocks (less then 12 words) */
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PLD (r0, #32)
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PLD (r1, #32)
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1: ldrh r0, [r3], #2
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ldrh ip, [r1], #2
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subs r0, r0, ip
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bxne lr
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subs r2, r2, #1
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bne 1b
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bx lr
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.save {r4, lr}
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/* save registers */
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0: stmfd sp!, {r4, lr}
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/* align first pointer to word boundary */
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tst r3, #2
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beq 0f
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ldrh r0, [r3], #2
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ldrh ip, [r1], #2
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sub r2, r2, #1
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subs r0, r0, ip
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/* restore registers and return */
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ldmnefd sp!, {r4, lr}
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bxne lr
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.fnend
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0: /* here the first pointer is aligned, and we have at least 3 words
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* to process.
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*/
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/* see if the pointers are congruent */
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eor r0, r3, r1
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ands r0, r0, #2
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bne 5f
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/* congruent case, 16 half-words per iteration
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* We need to make sure there are at least 16+2 words left
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* because we effectively read ahead one long word, and we could
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* read past the buffer (and segfault) if we're not careful.
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*/
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ldr ip, [r1]
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subs r2, r2, #(16 + 2)
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bmi 1f
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0:
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PLD (r3, #64)
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PLD (r1, #64)
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ldr r0, [r3], #4
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ldr lr, [r1, #4]!
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eors r0, r0, ip
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ldreq r0, [r3], #4
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ldreq ip, [r1, #4]!
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eoreqs r0, r0, lr
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ldreq r0, [r3], #4
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ldreq lr, [r1, #4]!
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eoreqs r0, r0, ip
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ldreq r0, [r3], #4
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ldreq ip, [r1, #4]!
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eoreqs r0, r0, lr
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ldreq r0, [r3], #4
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ldreq lr, [r1, #4]!
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eoreqs r0, r0, ip
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ldreq r0, [r3], #4
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ldreq ip, [r1, #4]!
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eoreqs r0, r0, lr
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ldreq r0, [r3], #4
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ldreq lr, [r1, #4]!
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eoreqs r0, r0, ip
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ldreq r0, [r3], #4
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ldreq ip, [r1, #4]!
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eoreqs r0, r0, lr
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bne 2f
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subs r2, r2, #16
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bhs 0b
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/* do we have at least 2 words left? */
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1: adds r2, r2, #(16 - 2 + 2)
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bmi 4f
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/* finish off 2 words at a time */
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3: ldr r0, [r3], #4
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ldr ip, [r1], #4
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eors r0, r0, ip
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bne 2f
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subs r2, r2, #2
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bhs 3b
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/* are we done? */
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4: adds r2, r2, #2
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bne 8f
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/* restore registers and return */
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mov r0, #0
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ldmfd sp!, {r4, lr}
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bx lr
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2: /* the last 2 words are different, restart them */
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ldrh r0, [r3, #-4]
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ldrh ip, [r1, #-4]
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subs r0, r0, ip
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ldreqh r0, [r3, #-2]
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ldreqh ip, [r1, #-2]
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subeqs r0, r0, ip
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/* restore registers and return */
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ldmfd sp!, {r4, lr}
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bx lr
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/* process the last few words */
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8: ldrh r0, [r3], #2
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ldrh ip, [r1], #2
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subs r0, r0, ip
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bne 9f
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subs r2, r2, #1
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bne 8b
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9: /* restore registers and return */
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ldmfd sp!, {r4, lr}
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bx lr
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5: /*************** non-congruent case ***************/
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/* align the unaligned pointer */
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bic r1, r1, #3
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ldr lr, [r1], #4
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sub r2, r2, #8
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6:
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PLD (r3, #64)
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PLD (r1, #64)
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mov ip, lr, lsr #16
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ldr lr, [r1], #4
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ldr r0, [r3], #4
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orr ip, ip, lr, lsl #16
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eors r0, r0, ip
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moveq ip, lr, lsr #16
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ldreq lr, [r1], #4
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ldreq r0, [r3], #4
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orreq ip, ip, lr, lsl #16
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eoreqs r0, r0, ip
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moveq ip, lr, lsr #16
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ldreq lr, [r1], #4
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ldreq r0, [r3], #4
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orreq ip, ip, lr, lsl #16
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eoreqs r0, r0, ip
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moveq ip, lr, lsr #16
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ldreq lr, [r1], #4
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ldreq r0, [r3], #4
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orreq ip, ip, lr, lsl #16
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eoreqs r0, r0, ip
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bne 7f
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subs r2, r2, #8
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bhs 6b
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sub r1, r1, #2
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/* are we done? */
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adds r2, r2, #8
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moveq r0, #0
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beq 9b
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/* finish off the remaining bytes */
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b 8b
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7: /* fix up the 2 pointers and fallthrough... */
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sub r1, r1, #2
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b 2b
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