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- Committer: Will Newton
- Date: 2013-04-30 14:31:08 UTC
- Revision ID: will.newton@linaro.org-20130430143108-ww31c741wek8dnus
Split bionic reference code into A15 and A9 versions.
- files added:
- reference/bionic-a15
- reference/bionic-a9
- files removed:
- reference/bionic
- files modified:
- Makefile.am
added
removed
reference/bionic-a9/memcpy.S
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/*
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* Copyright (C) 2008 The Android Open Source Project
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* This code assumes it is running on a processor that supports all arm v7
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* instructions, that supports neon instructions, and that has a 32 byte
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* cache line.
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*/
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.text
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.fpu neon
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#define CACHE_LINE_SIZE 32
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.globl memcpy
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.type memcpy,%function
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memcpy:
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.fnstart
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.save {r0, lr}
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/* start preloading as early as possible */
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pld [r1, #(CACHE_LINE_SIZE * 0)]
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stmfd sp!, {r0, lr}
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pld [r1, #(CACHE_LINE_SIZE * 2)]
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// Check so divider is at least 16 bytes, needed for alignment code.
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cmp r2, #16
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blo 5f
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/* check if buffers are aligned. If so, run arm-only version */
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eor r3, r0, r1
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ands r3, r3, #0x3
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beq 11f
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/* Check the upper size limit for Neon unaligned memory access in memcpy */
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cmp r2, #224
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blo 3f
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/* align destination to 16 bytes for the write-buffer */
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rsb r3, r0, #0
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ands r3, r3, #0xF
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beq 3f
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/* copy up to 15-bytes (count in r3) */
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sub r2, r2, r3
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movs ip, r3, lsl #31
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ldrmib lr, [r1], #1
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strmib lr, [r0], #1
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ldrcsb ip, [r1], #1
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ldrcsb lr, [r1], #1
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strcsb ip, [r0], #1
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strcsb lr, [r0], #1
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movs ip, r3, lsl #29
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bge 1f
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// copies 4 bytes, destination 32-bits aligned
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vld1.32 {d0[0]}, [r1]!
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vst1.32 {d0[0]}, [r0, :32]!
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1: bcc 2f
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// copies 8 bytes, destination 64-bits aligned
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vld1.8 {d0}, [r1]!
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vst1.8 {d0}, [r0, :64]!
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2:
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/* preload immediately the next cache line, which we may need */
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pld [r1, #(CACHE_LINE_SIZE * 0)]
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pld [r1, #(CACHE_LINE_SIZE * 2)]
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3:
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/* make sure we have at least 64 bytes to copy */
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subs r2, r2, #64
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blo 2f
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/* preload all the cache lines we need */
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pld [r1, #(CACHE_LINE_SIZE * 4)]
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pld [r1, #(CACHE_LINE_SIZE * 6)]
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1: /* The main loop copies 64 bytes at a time */
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vld1.8 {d0 - d3}, [r1]!
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vld1.8 {d4 - d7}, [r1]!
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pld [r1, #(CACHE_LINE_SIZE * 6)]
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subs r2, r2, #64
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vst1.8 {d0 - d3}, [r0]!
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vst1.8 {d4 - d7}, [r0]!
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bhs 1b
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2: /* fix-up the remaining count and make sure we have >= 32 bytes left */
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add r2, r2, #64
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subs r2, r2, #32
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blo 4f
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3: /* 32 bytes at a time. These cache lines were already preloaded */
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vld1.8 {d0 - d3}, [r1]!
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subs r2, r2, #32
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vst1.8 {d0 - d3}, [r0]!
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bhs 3b
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4: /* less than 32 left */
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add r2, r2, #32
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tst r2, #0x10
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beq 5f
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// copies 16 bytes, 128-bits aligned
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vld1.8 {d0, d1}, [r1]!
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vst1.8 {d0, d1}, [r0]!
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5: /* copy up to 15-bytes (count in r2) */
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movs ip, r2, lsl #29
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bcc 1f
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vld1.8 {d0}, [r1]!
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vst1.8 {d0}, [r0]!
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1: bge 2f
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vld1.32 {d0[0]}, [r1]!
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vst1.32 {d0[0]}, [r0]!
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2: movs ip, r2, lsl #31
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ldrmib r3, [r1], #1
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ldrcsb ip, [r1], #1
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ldrcsb lr, [r1], #1
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strmib r3, [r0], #1
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strcsb ip, [r0], #1
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strcsb lr, [r0], #1
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ldmfd sp!, {r0, lr}
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bx lr
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11:
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/* Simple arm-only copy loop to handle aligned copy operations */
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stmfd sp!, {r4, r5, r6, r7, r8}
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pld [r1, #(CACHE_LINE_SIZE * 4)]
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/* Check alignment */
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rsb r3, r1, #0
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ands r3, #3
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beq 2f
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/* align source to 32 bits. We need to insert 2 instructions between
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* a ldr[b|h] and str[b|h] because byte and half-word instructions
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* stall 2 cycles.
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*/
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movs r12, r3, lsl #31
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sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */
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ldrmib r3, [r1], #1
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ldrcsb r4, [r1], #1
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ldrcsb r5, [r1], #1
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strmib r3, [r0], #1
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strcsb r4, [r0], #1
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strcsb r5, [r0], #1
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2:
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subs r2, r2, #64
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blt 4f
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3: /* Main copy loop, copying 64 bytes at a time */
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pld [r1, #(CACHE_LINE_SIZE * 8)]
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ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr}
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stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr}
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ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr}
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stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr}
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subs r2, r2, #64
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bge 3b
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4: /* Check if there are > 32 bytes left */
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adds r2, r2, #64
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subs r2, r2, #32
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blt 5f
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/* Copy 32 bytes */
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ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr}
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stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr}
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subs r2, #32
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5: /* Handle any remaining bytes */
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adds r2, #32
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beq 6f
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movs r12, r2, lsl #28
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ldmcsia r1!, {r3, r4, r5, r6} /* 16 bytes */
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ldmmiia r1!, {r7, r8} /* 8 bytes */
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stmcsia r0!, {r3, r4, r5, r6}
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stmmiia r0!, {r7, r8}
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movs r12, r2, lsl #30
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ldrcs r3, [r1], #4 /* 4 bytes */
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ldrmih r4, [r1], #2 /* 2 bytes */
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strcs r3, [r0], #4
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strmih r4, [r0], #2
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tst r2, #0x1
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ldrneb r3, [r1] /* last byte */
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strneb r3, [r0]
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6:
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ldmfd sp!, {r4, r5, r6, r7, r8}
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ldmfd sp!, {r0, pc}
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.fnend
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.size memcpy, .-memcpy
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