2
* Copyright (c) 2008 ARM Ltd
5
* Redistribution and use in source and binary forms, with or without
6
* modification, are permitted provided that the following conditions
8
* 1. Redistributions of source code must retain the above copyright
9
* notice, this list of conditions and the following disclaimer.
10
* 2. Redistributions in binary form must reproduce the above copyright
11
* notice, this list of conditions and the following disclaimer in the
12
* documentation and/or other materials provided with the distribution.
13
* 3. The name of the company may not be used to endorse or promote
14
* products derived from this software without specific prior written
17
* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
18
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22
* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32
#if defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED) || \
33
(defined (__thumb__) && !defined (__thumb2__))
36
strlen (const char* str)
39
#if defined (__thumb__) && !defined (__thumb2__)
43
"ldrb %1, [%2, %0]\n\t"
47
: "=&r" (len), "=&r" (scratch) : "r" (str) : "memory", "cc");
52
"ldrb %1, [%0], #1\n\t"
55
: "=&r" (end), "=&r" (scratch) : "0" (str) : "memory", "cc");
61
size_t __attribute__((naked))
62
strlen (const char* str)
64
asm ("len .req r0\n\t"
69
/* Word-align address */
70
"bic addr, r0, #3\n\t"
71
/* Get adjustment for start ... */
72
"ands len, r0, #3\n\t"
74
/* First word of data */
75
"ldr data, [addr], #4\n\t"
76
/* Ensure bytes preceeding start ... */
78
"mov ip, ip, asl #3\n\t"
80
/* ... are masked out */
88
"orrne data, data, r2\n\t"
92
"orrne data, data, r2, lsl ip\n\t"
94
"orrne data, data, r2, lsr ip\n\t"
97
/* Magic const 0x01010101 */
102
"orr ip, ip, ip, lsl #8\n\t"
104
"orr ip, ip, ip, lsl #16\n"
106
/* This is the main loop. We subtract one from each byte in
107
the word: the sign bit changes iff the byte was zero or
108
0x80 -- we eliminate the latter case by anding the result
109
with the 1-s complement of the data. */
111
/* test (data - 0x01010101) */
112
"sub r2, data, ip\n\t"
114
"bic r2, r2, data\n\t"
115
/* ... & 0x80808080 == 0? */
116
"ands r2, r2, ip, lsl #7\n\t"
118
/* yes, get more data... */
120
"ldreq data, [addr], #4\n\t"
121
/* and 4 more bytes */
122
"addeq len, len, #4\n\t"
123
/* If we have PLD, then unroll the loop a bit. */
125
/* test (data - 0x01010101) */
127
"subeq r2, data, ip\n\t"
129
"biceq r2, r2, data\n\t"
130
/* ... & 0x80808080 == 0? */
131
"andeqs r2, r2, ip, lsl #7\n\t"
134
/* yes, get more data... */
135
"ldreq data, [addr], #4\n\t"
136
/* and 4 more bytes */
137
"addeq len, len, #4\n\t"
140
"tst data, #0xff000000\n\t"
142
"addne len, len, #1\n\t"
143
"tstne data, #0xff0000\n\t"
144
"addne len, len, #1\n\t"
145
"tstne data, #0xff00\n\t"
147
"addne len, len, #1\n\t"
150
/* R2 is the residual sign bits from the above test. All we
151
need to do now is establish the position of the first zero
153
/* Little-endian is harder, we need the number of trailing
162
"rsb r2, r2, #31\n\t"
164
"add len, len, r2, lsr #3\n\t"
165
# else /* No CLZ instruction */
166
"tst data, #0xff\n\t"
168
"addne len, len, #1\n\t"
169
"tstne data, #0xff00\n\t"
170
"addne len, len, #1\n\t"
171
"tstne data, #0xff0000\n\t"
173
"addne len, len, #1\n\t"