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/*********************************************************
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* Copyright (C) 2007 VMware, Inc. All rights reserved.
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation version 2 and no later version.
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*********************************************************/
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* Definitions shared by device emulation and guest drivers for
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#ifndef _VMXNET3_DEFS_H_
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#define _VMXNET3_DEFS_H_
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#define INCLUDE_ALLOW_USERLEVEL
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#define INCLUDE_ALLOW_VMKERNEL
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#define INCLUDE_ALLOW_VMMEXT
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#define INCLUDE_ALLOW_VMCORE
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#define INCLUDE_ALLOW_MODULE
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#include "includeCheck.h"
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#include "upt1_defs.h"
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/* all registers are 32 bit wide */
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#define VMXNET3_REG_VRRS 0x0 /* Vmxnet3 Revision Report Selection */
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#define VMXNET3_REG_UVRS 0x8 /* UPT Version Report Selection */
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#define VMXNET3_REG_DSAL 0x10 /* Driver Shared Address Low */
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#define VMXNET3_REG_DSAH 0x18 /* Driver Shared Address High */
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#define VMXNET3_REG_CMD 0x20 /* Command */
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#define VMXNET3_REG_MACL 0x28 /* MAC Address Low */
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#define VMXNET3_REG_MACH 0x30 /* MAC Address High */
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#define VMXNET3_REG_ICR 0x38 /* Interrupt Cause Register */
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#define VMXNET3_REG_ECR 0x40 /* Event Cause Register */
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#define VMXNET3_REG_IMR 0x0 /* Interrupt Mask Register */
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#define VMXNET3_REG_TXPROD 0x600 /* Tx Producer Index */
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#define VMXNET3_REG_RXPROD 0x800 /* Rx Producer Index for ring 1 */
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#define VMXNET3_REG_RXPROD2 0xA00 /* Rx Producer Index for ring 2 */
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#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
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#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
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#define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
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#define VMXNET3_REG_ALIGN_MASK 0x7
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/* I/O Mapped access to registers */
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#define VMXNET3_IO_TYPE_PT 0
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#define VMXNET3_IO_TYPE_VD 1
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#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
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#define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
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#define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
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VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
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VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
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VMXNET3_CMD_QUIESCE_DEV,
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VMXNET3_CMD_RESET_DEV,
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VMXNET3_CMD_UPDATE_RX_MODE,
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VMXNET3_CMD_UPDATE_MAC_FILTERS,
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VMXNET3_CMD_UPDATE_VLAN_FILTERS,
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VMXNET3_CMD_UPDATE_RSSIDT,
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VMXNET3_CMD_UPDATE_IML,
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VMXNET3_CMD_UPDATE_PMCFG,
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VMXNET3_CMD_UPDATE_FEATURE,
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VMXNET3_CMD_FIRST_GET = 0xF00D0000,
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VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
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VMXNET3_CMD_GET_STATS,
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VMXNET3_CMD_GET_PERM_MAC_LO,
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VMXNET3_CMD_GET_PERM_MAC_HI,
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VMXNET3_CMD_GET_DID_LO,
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VMXNET3_CMD_GET_DID_HI,
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VMXNET3_CMD_GET_DEV_EXTRA_INFO,
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VMXNET3_CMD_GET_CONF_INTR
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#include "vmware_pack_begin.h"
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struct Vmxnet3_TxDesc {
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uint32 gen:1; /* generation bit */
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uint32 dtype:1; /* descriptor type */
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uint32 msscof:14; /* MSS, checksum offset, flags */
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uint32 hlen:10; /* header len */
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uint32 om:2; /* offload mode */
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uint32 eop:1; /* End Of Packet */
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uint32 cq:1; /* completion request */
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uint32 ti:1; /* VLAN Tag Insertion */
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uint32 tci:16; /* Tag to Insert */
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#include "vmware_pack_end.h"
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/* TxDesc.OM values */
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#define VMXNET3_OM_NONE 0
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#define VMXNET3_OM_CSUM 2
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#define VMXNET3_OM_TSO 3
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/* fields in TxDesc we access w/o using bit fields */
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#define VMXNET3_TXD_EOP_SHIFT 12
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#define VMXNET3_TXD_CQ_SHIFT 13
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#define VMXNET3_TXD_GEN_SHIFT 14
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#define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
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#define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
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#define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
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#define VMXNET3_HDR_COPY_SIZE 128
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#include "vmware_pack_begin.h"
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struct vmxnet3_TxDataDesc {
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uint8 data[VMXNET3_HDR_COPY_SIZE];
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#include "vmware_pack_end.h"
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#include "vmware_pack_begin.h"
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struct Vmxnet3_TxCompDesc {
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uint32 txdIdx:12; /* Index of the EOP TxDesc */
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uint32 type:7; /* completion type */
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uint32 gen:1; /* generation bit */
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#include "vmware_pack_end.h"
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#include "vmware_pack_begin.h"
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struct Vmxnet3_RxDesc {
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uint32 btype:1; /* Buffer Type */
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uint32 dtype:1; /* Descriptor type */
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uint32 gen:1; /* Generation bit */
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#include "vmware_pack_end.h"
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/* values of RXD.BTYPE */
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#define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
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#define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
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/* fields in RxDesc we access w/o using bit fields */
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#define VMXNET3_RXD_BTYPE_SHIFT 14
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#define VMXNET3_RXD_GEN_SHIFT 31
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#include "vmware_pack_begin.h"
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struct Vmxnet3_RxCompDesc {
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uint32 rxdIdx:12; /* Index of the RxDesc */
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uint32 eop:1; /* End of Packet */
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uint32 sop:1; /* Start of Packet */
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uint32 rqID:10; /* rx queue/ring ID */
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uint32 rssType:4; /* RSS hash type used */
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uint32 cnc:1; /* Checksum Not Calculated */
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uint32 rssHash; /* RSS hash value */
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uint32 len:14; /* data length */
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uint32 err:1; /* Error */
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uint32 ts:1; /* Tag is stripped */
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uint32 tci:16; /* Tag stripped */
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uint32 tuc:1; /* TCP/UDP Checksum Correct */
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uint32 udp:1; /* UDP packet */
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uint32 tcp:1; /* TCP packet */
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uint32 ipc:1; /* IP Checksum Correct */
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uint32 v6:1; /* IPv6 */
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uint32 v4:1; /* IPv4 */
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uint32 frg:1; /* IP Fragment */
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uint32 fcs:1; /* Frame CRC correct */
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uint32 type:7; /* completion type */
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uint32 gen:1; /* generation bit */
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#include "vmware_pack_end.h"
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/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
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#define VMXNET3_RCD_TUC_SHIFT 16
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#define VMXNET3_RCD_IPC_SHIFT 19
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/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
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#define VMXNET3_RCD_TYPE_SHIFT 56
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#define VMXNET3_RCD_GEN_SHIFT 63
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/* csum OK for TCP/UDP pkts over IP */
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#define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | 1 << VMXNET3_RCD_IPC_SHIFT)
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/* value of RxCompDesc.rssType */
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#define VMXNET3_RCD_RSS_TYPE_NONE 0
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#define VMXNET3_RCD_RSS_TYPE_IPV4 1
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#define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2
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#define VMXNET3_RCD_RSS_TYPE_IPV6 3
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#define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4
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/* a union for accessing all cmd/completion descriptors */
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typedef union Vmxnet3_GenericDesc {
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Vmxnet3_TxCompDesc tcd;
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Vmxnet3_RxCompDesc rcd;
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} Vmxnet3_GenericDesc;
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#define VMXNET3_INIT_GEN 1
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/* Max size of a single tx buffer */
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#define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
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/* # of tx desc needed for a tx buffer size */
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#define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / VMXNET3_MAX_TX_BUF_SIZE)
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/* max # of tx descs for a non-tso pkt */
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#define VMXNET3_MAX_TXD_PER_PKT 16
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/* Max size of a single rx buffer */
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#define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
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/* Minimum size of a type 0 buffer */
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#define VMXNET3_MIN_T0_BUF_SIZE 128
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#define VMXNET3_MAX_CSUM_OFFSET 1024
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/* Ring base address alignment */
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#define VMXNET3_RING_BA_ALIGN 512
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#define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
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/* Ring size must be a multiple of 32 */
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#define VMXNET3_RING_SIZE_ALIGN 32
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#define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
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#define VMXNET3_TX_RING_MAX_SIZE 4096
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#define VMXNET3_TC_RING_MAX_SIZE 4096
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#define VMXNET3_RX_RING_MAX_SIZE 4096
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#define VMXNET3_RC_RING_MAX_SIZE 8192
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/* a list of reasons for queue stop */
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#define VMXNET3_ERR_NOEOP 0x80000000 /* cannot find the EOP desc of a pkt */
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#define VMXNET3_ERR_TXD_REUSE 0x80000001 /* reuse a TxDesc before tx completion */
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#define VMXNET3_ERR_BIG_PKT 0x80000002 /* too many TxDesc for a pkt */
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#define VMXNET3_ERR_DESC_NOT_SPT 0x80000003 /* descriptor type not supported */
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#define VMXNET3_ERR_SMALL_BUF 0x80000004 /* type 0 buffer too small */
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#define VMXNET3_ERR_STRESS 0x80000005 /* stress option firing in vmkernel */
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#define VMXNET3_ERR_SWITCH 0x80000006 /* mode switch failure */
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#define VMXNET3_ERR_TXD_INVALID 0x80000007 /* invalid TxDesc */
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/* completion descriptor types */
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#define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
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#define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
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#define VMXNET3_GOS_BITS_UNK 0 /* unknown */
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#define VMXNET3_GOS_BITS_32 1
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#define VMXNET3_GOS_BITS_64 2
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#define VMXNET3_GOS_TYPE_UNK 0 /* unknown */
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#define VMXNET3_GOS_TYPE_LINUX 1
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#define VMXNET3_GOS_TYPE_WIN 2
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#define VMXNET3_GOS_TYPE_SOLARIS 3
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#define VMXNET3_GOS_TYPE_FREEBSD 4
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#define VMXNET3_GOS_TYPE_PXE 5
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/* All structures in DriverShared are padded to multiples of 8 bytes */
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#include "vmware_pack_begin.h"
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struct Vmxnet3_GOSInfo {
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uint32 gosBits: 2; /* 32-bit or 64-bit? */
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uint32 gosType: 4; /* which guest */
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uint32 gosVer: 16; /* gos version */
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uint32 gosMisc: 10; /* other info about gos */
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#include "vmware_pack_end.h"
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#include "vmware_pack_begin.h"
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struct Vmxnet3_DriverInfo {
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uint32 version; /* driver version */
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uint32 vmxnet3RevSpt; /* vmxnet3 revision supported */
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uint32 uptVerSpt; /* upt version supported */
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#include "vmware_pack_end.h"
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#define VMXNET3_REV1_MAGIC 0xbabefee1
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* QueueDescPA must be 128 bytes aligned. It points to an array of
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* Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
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* The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
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* Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
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#define VMXNET3_QUEUE_DESC_ALIGN 128
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#include "vmware_pack_begin.h"
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struct Vmxnet3_MiscConf {
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Vmxnet3_DriverInfo driverInfo;
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uint64 ddPA; /* driver data PA */
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uint64 queueDescPA; /* queue descriptor table PA */
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uint32 ddLen; /* driver data len */
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uint32 queueDescLen; /* queue descriptor table len, in bytes */
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#include "vmware_pack_end.h"
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#include "vmware_pack_begin.h"
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struct vmxnet3_TxQueueConf {
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uint64 dataRingBasePA;
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uint64 compRingBasePA;
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uint64 ddPA; /* driver data */
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uint32 txRingSize; /* # of tx desc */
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uint32 dataRingSize; /* # of data desc */
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uint32 compRingSize; /* # of comp desc */
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uint32 ddLen; /* size of driver data */
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#include "vmware_pack_end.h"
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#include "vmware_pack_begin.h"
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struct Vmxnet3_RxQueueConf {
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uint64 rxRingBasePA[2];
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uint64 compRingBasePA;
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uint64 ddPA; /* driver data */
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uint32 rxRingSize[2]; /* # of rx desc */
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uint32 compRingSize; /* # of rx comp desc */
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uint32 ddLen; /* size of driver data */
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#include "vmware_pack_end.h"
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enum vmxnet3_intr_mask_mode {
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VMXNET3_IMM_AUTO = 0,
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VMXNET3_IMM_ACTIVE = 1,
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enum vmxnet3_intr_type {
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#define VMXNET3_MAX_TX_QUEUES 8
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#define VMXNET3_MAX_RX_QUEUES 16
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/* addition 1 for events */
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#define VMXNET3_MAX_INTRS 25
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#include "vmware_pack_begin.h"
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struct Vmxnet3_IntrConf {
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uint8 numIntrs; /* # of interrupts */
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uint8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for each intr */
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#include "vmware_pack_end.h"
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/* one bit per VLAN ID, the size is in the units of uint32 */
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#define VMXNET3_VFT_SIZE (4096 / (sizeof(uint32) * 8))
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#include "vmware_pack_begin.h"
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struct Vmxnet3_QueueStatus {
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#include "vmware_pack_end.h"
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#include "vmware_pack_begin.h"
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struct Vmxnet3_TxQueueCtrl {
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uint32 txNumDeferred;
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#include "vmware_pack_end.h"
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#include "vmware_pack_begin.h"
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struct Vmxnet3_RxQueueCtrl {
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#include "vmware_pack_end.h"
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#define VMXNET3_RXM_UCAST 0x01 /* unicast only */
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#define VMXNET3_RXM_MCAST 0x02 /* multicast passing the filters */
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#define VMXNET3_RXM_BCAST 0x04 /* broadcast only */
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#define VMXNET3_RXM_ALL_MULTI 0x08 /* all multicast */
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#define VMXNET3_RXM_PROMISC 0x10 /* promiscuous */
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#include "vmware_pack_begin.h"
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struct Vmxnet3_RxFilterConf {
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uint32 rxMode; /* VMXNET3_RXM_xxx */
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uint16 mfTableLen; /* size of the multicast filter table */
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uint64 mfTablePA; /* PA of the multicast filters table */
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uint32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
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#include "vmware_pack_end.h"
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Vmxnet3_RxFilterConf;
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#define VMXNET3_PM_MAX_FILTERS 6
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#define VMXNET3_PM_MAX_PATTERN_SIZE 128
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#define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
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#define VMXNET3_PM_WAKEUP_MAGIC 0x01 /* wake up on magic pkts */
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#define VMXNET3_PM_WAKEUP_FILTER 0x02 /* wake up on pkts matching filters */
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#include "vmware_pack_begin.h"
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struct Vmxnet3_PM_PktFilter {
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uint8 mask[VMXNET3_PM_MAX_MASK_SIZE];
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uint8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
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#include "vmware_pack_end.h"
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Vmxnet3_PM_PktFilter;
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#include "vmware_pack_begin.h"
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struct Vmxnet3_PMConf {
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uint16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */
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Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
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#include "vmware_pack_end.h"
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#include "vmware_pack_begin.h"
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struct Vmxnet3_VariableLenConfDesc {
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#include "vmware_pack_end.h"
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Vmxnet3_VariableLenConfDesc;
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#include "vmware_pack_begin.h"
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struct Vmxnet3_DSDevRead {
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/* read-only region for device, read by dev in response to a SET cmd */
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Vmxnet3_MiscConf misc;
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Vmxnet3_IntrConf intrConf;
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Vmxnet3_RxFilterConf rxFilterConf;
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Vmxnet3_VariableLenConfDesc rssConfDesc;
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Vmxnet3_VariableLenConfDesc pmConfDesc;
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#include "vmware_pack_end.h"
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#include "vmware_pack_begin.h"
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struct Vmxnet3_TxQueueDesc {
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Vmxnet3_TxQueueCtrl ctrl;
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Vmxnet3_TxQueueConf conf;
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/* Driver read after a GET command */
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Vmxnet3_QueueStatus status;
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uint8 _pad[88]; /* 128 aligned */
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#include "vmware_pack_end.h"
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#include "vmware_pack_begin.h"
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struct Vmxnet3_RxQueueDesc {
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Vmxnet3_RxQueueCtrl ctrl;
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Vmxnet3_RxQueueConf conf;
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/* Driver read after a GET command */
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Vmxnet3_QueueStatus status;
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uint8 _pad[88]; /* 128 aligned */
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#include "vmware_pack_end.h"
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#include "vmware_pack_begin.h"
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struct Vmxnet3_DriverShared {
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uint32 pad; /* make devRead start at 64-bit boundaries */
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Vmxnet3_DSDevRead devRead;
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#include "vmware_pack_end.h"
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Vmxnet3_DriverShared;
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#define VMXNET3_ECR_RQERR (1 << 0)
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#define VMXNET3_ECR_TQERR (1 << 1)
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#define VMXNET3_ECR_LINK (1 << 2)
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#define VMXNET3_ECR_DIC (1 << 3)
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#define VMXNET3_ECR_DEBUG (1 << 4)
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/* flip the gen bit of a ring */
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#define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
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/* only use this if moving the idx won't affect the gen bit */
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#define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
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if (UNLIKELY((idx) == (ring_size))) {\
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#define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
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vfTable[vid >> 5] |= (1 << (vid & 31))
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#define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
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vfTable[vid >> 5] &= ~(1 << (vid & 31))
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#define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
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((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
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#define VMXNET3_MAX_MTU 9000
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#define VMXNET3_MIN_MTU 60
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#define VMXNET3_LINK_UP (10000 << 16 | 1) // 10 Gbps, up
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#define VMXNET3_LINK_DOWN 0
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#endif /* _VMXNET3_DEFS_H_ */
added
removed
modules/linux/vmxnet3/vmxnet3_defs.h
