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#define INCLUDE_ALLOW_VMMEXT
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#define INCLUDE_ALLOW_VMKERNEL
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#define INCLUDE_ALLOW_MODULE
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#define INCLUDE_ALLOW_VMNIXMOD
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#define INCLUDE_ALLOW_DISTRIBUTE
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#define INCLUDE_ALLOW_VMK_MODULE
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45
#define INCLUDE_ALLOW_VMCORE
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FLAGDEF( 6, EAX, INTEL, 0, 1, THERMAL_SENSOR, NA, FALSE) \
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FLAGDEF( 6, EAX, INTEL, 1, 1, TURBO_MODE, NA, FALSE) \
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FIELDDEF( 6, EBX, INTEL, 0, 4, NUM_INTR_THRESHOLDS, NA, FALSE) \
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FLAGDEF( 6, ECX, INTEL, 0, 1, HW_COORD_FEEDBACK, NA, FALSE)
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FLAGDEF( 6, ECX, INTEL, 0, 1, HW_COORD_FEEDBACK, NA, FALSE) \
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FLAGDEF( 6, ECX, INTEL, 3, 1, ENERGY_PERF_BIAS, NA, FALSE)
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/* LEVEL, REG, VENDOR, POS, SIZE, NAME, MON SUPP, CPL3, [FUNC] */
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#define CPUID_FIELD_DATA_LEVEL_A \
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FLAGDEF( 8A, EDX, AMD, 1, 1, SVM_LBR, NO, FALSE) \
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FLAGDEF( 8A, EDX, AMD, 2, 1, SVM_LOCK, NO, FALSE) \
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FLAGDEF( 8A, EDX, AMD, 3, 1, SVM_NRIP, NO, FALSE) \
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FIELDDEF( 8A, EDX, AMD, 4, 28, SVMEDX_RSVD, NO, FALSE)
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FLAGDEF( 8A, EDX, AMD, 10, 1, SVM_PAUSE_FILTER, NO, FALSE)
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#define CPUID_FIELD_DATA_LEVEL_8A_BD \
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FIELDDEF( 8A, EDX, AMD, 4, 6, SVMEDX_RSVD0, NO, FALSE) \
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FIELDDEF( 8A, EDX, AMD, 11, 21, SVMEDX_RSVD1, NO, FALSE)
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#define CPUID_FIELD_DATA \
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CPUID_FIELD_DATA_LEVEL_B \
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CPUID_FIELD_DATA_LEVEL_80 \
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CPUID_FIELD_DATA_LEVEL_81 \
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CPUID_FIELD_DATA_LEVEL_8x
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CPUID_FIELD_DATA_LEVEL_8x \
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CPUID_FIELD_DATA_LEVEL_8A_BD