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* VC1 NEON optimisations
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* Copyright (c) 2010 Rob Clark <rob@ti.com>
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* Copyright (c) 2011 Mans Rullgard <mans@mansr.com>
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* This file is part of FFmpeg.
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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#include "libavutil/arm/asm.S"
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@ Transpose rows into columns of a matrix of 16-bit elements. For 4x4, pass
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@ double-word registers, for 8x4, pass quad-word registers.
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.macro transpose16 r0, r1, r2, r3
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vtrn.16 \r0, \r1 @ first and second row
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vtrn.16 \r2, \r3 @ third and fourth row
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vtrn.32 \r0, \r2 @ first and third row
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vtrn.32 \r1, \r3 @ second and fourth row
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@ At this point, if registers are quad-word:
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@ At this point, if registers are double-word:
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@ ff_vc1_inv_trans_{4,8}x{4,8}_neon and overflow: The input values in the file
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@ are supposed to be in a specific range as to allow for 16-bit math without
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@ causing overflows, but sometimes the input values are just big enough to
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@ barely cause overflow in vadd instructions like:
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@ vadd.i16 q0, q8, q10
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@ vshr.s16 q0, q0, #\rshift
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@ To prevent these borderline cases from overflowing, we just need one more
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@ bit of precision, which is accomplished by replacing the sequence above with:
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@ vhadd.s16 q0, q8, q10
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@ vshr.s16 q0, q0, #(\rshift -1)
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@ This works because vhadd is a single instruction that adds, then shifts to
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@ the right once, all before writing the result to the destination register.
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@ Even with this workaround, there were still some files that caused overflows
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@ in ff_vc1_inv_trans_8x8_neon. See the comments in ff_vc1_inv_trans_8x8_neon
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@ for the additional workaround.
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@ Takes 4 columns of 8 values each and operates on it. Modeled after the first
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@ for loop in vc1_inv_trans_4x8_c.
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@ Input columns: q0 q1 q2 q3
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@ Output columns: q0 q1 q2 q3
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@ Trashes: r12 q8 q9 q10 q11 q12 q13
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.macro vc1_inv_trans_4x8_helper add rshift
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@ Compute temp1, temp2 and setup scalar #17, #22, #10
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vadd.i16 q12, q0, q2 @ temp1 = src[0] + src[2]
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vsub.i16 q13, q0, q2 @ temp2 = src[0] - src[2]
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vmov.i16 q8, #\add @ t1 will accumulate here
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vmov.i16 q9, #\add @ t2 will accumulate here
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vmul.i16 q10, q1, d0[1] @ t3 = 22 * (src[1])
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vmul.i16 q11, q3, d0[1] @ t4 = 22 * (src[3])
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vmla.i16 q8, q12, d0[0] @ t1 = 17 * (temp1) + 4
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vmla.i16 q9, q13, d0[0] @ t2 = 17 * (temp2) + 4
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vmla.i16 q10, q3, d1[0] @ t3 += 10 * src[3]
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vmls.i16 q11, q1, d1[0] @ t4 -= 10 * src[1]
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vhadd.s16 q0, q8, q10 @ dst[0] = (t1 + t3) >> 1
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vhsub.s16 q3, q8, q10 @ dst[3] = (t1 - t3) >> 1
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vhsub.s16 q1, q9, q11 @ dst[1] = (t2 - t4) >> 1
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vhadd.s16 q2, q9, q11 @ dst[2] = (t2 + t4) >> 1
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@ Halving add/sub above already did one shift
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vshr.s16 q0, q0, #(\rshift - 1) @ dst[0] >>= (rshift - 1)
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vshr.s16 q3, q3, #(\rshift - 1) @ dst[3] >>= (rshift - 1)
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vshr.s16 q1, q1, #(\rshift - 1) @ dst[1] >>= (rshift - 1)
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vshr.s16 q2, q2, #(\rshift - 1) @ dst[2] >>= (rshift - 1)
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@ Takes 8 columns of 4 values each and operates on it. Modeled after the second
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@ for loop in vc1_inv_trans_4x8_c.
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@ Input columns: d0 d2 d4 d6 d1 d3 d5 d7
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@ Output columns: d16 d17 d18 d19 d21 d20 d23 d22
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@ Trashes all NEON registers (and r12) except for: q4 q5 q6 q7
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.macro vc1_inv_trans_8x4_helper add add1beforeshift rshift
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@ src[0] d0 overwritten later
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@ src[16] d4 overwritten later
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@ src[32] d1 overwritten later
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@ src[48] d5 overwritten later
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vmov.i16 q14, #\add @ t1|t2 will accumulate here
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vadd.i16 d20, d0, d1 @ temp1 = src[0] + src[32]
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vsub.i16 d21, d0, d1 @ temp2 = src[0] - src[32]
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vmov.i32 d0[0], r12 @ 16-bit: d0[0] = #12, d0[1] = #6
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vshl.i16 q15, q2, #4 @ t3|t4 = 16 * (src[16]|src[48])
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vswp d4, d5 @ q2 = src[48]|src[16]
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vmla.i16 q14, q10, d0[0] @ t1|t2 = 12 * (temp1|temp2) + 64
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vmov.i32 d0[1], r12 @ 16-bit: d0[2] = #15, d0[3] = #9
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vneg.s16 d31, d31 @ t4 = -t4
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vmla.i16 q15, q2, d0[1] @ t3|t4 += 6 * (src[48]|src[16])
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vshl.i16 q8, q1, #4 @ t1|t2 = 16 * (src[8]|src[40])
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vswp d2, d3 @ q1 = src[40]|src[8]
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vshl.i16 q12, q3, #4 @ temp3a|temp4a = 16 * src[24]|src[56]
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vswp d6, d7 @ q3 = src[56]|src[24]
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vshl.i16 q13, q1, #2 @ temp3b|temp4b = 4 * (src[40]|src[8])
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vshl.i16 q2, q3, #2 @ temp1|temp2 = 4 * (src[56]|src[24])
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vswp d3, d6 @ q1 = src[40]|src[56], q3 = src[8]|src[24]
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vsub.i16 q9, q13, q12 @ t3|t4 = - (temp3a|temp4a) + (temp3b|temp4b)
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vadd.i16 q8, q8, q2 @ t1|t2 += temp1|temp2
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vmul.i16 q12, q3, d0[3] @ temp3|temp4 = 9 * src[8]|src[24]
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vmla.i16 q8, q1, d0[3] @ t1|t2 += 9 * (src[40]|src[56])
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vswp d6, d7 @ q3 = src[24]|src[8]
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vswp d2, d3 @ q1 = src[56]|src[40]
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vsub.i16 q11, q14, q15 @ t8|t7 = old t1|t2 - old t3|t4
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vadd.i16 q10, q14, q15 @ t5|t6 = old t1|t2 + old t3|t4
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vadd.i16 d18, d18, d24 @ t3 += temp3
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vsub.i16 d19, d19, d25 @ t4 -= temp4
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vswp d22, d23 @ q11 = t7|t8
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vneg.s16 d17, d17 @ t2 = -t2
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vmla.i16 q9, q1, d0[2] @ t3|t4 += 15 * src[56]|src[40]
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vmla.i16 q8, q3, d0[2] @ t1|t2 += 15 * src[24]|src[8]
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vadd.i16 q3, q15, q10 @ line[7,6] = t5|t6 + 1
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vadd.i16 q2, q15, q11 @ line[5,4] = t7|t8 + 1
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@ Sometimes this overflows, so to get one additional bit of precision, use
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@ a single instruction that both adds and shifts right (halving).
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vhadd.s16 q1, q9, q11 @ line[2,3] = (t3|t4 + t7|t8) >> 1
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vhadd.s16 q0, q8, q10 @ line[0,1] = (t1|t2 + t5|t6) >> 1
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vhsub.s16 q2, q2, q9 @ line[5,4] = (t7|t8 - t3|t4 + 1) >> 1
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vhsub.s16 q3, q3, q8 @ line[7,6] = (t5|t6 - t1|t2 + 1) >> 1
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vhsub.s16 q2, q11, q9 @ line[5,4] = (t7|t8 - t3|t4) >> 1
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vhsub.s16 q3, q10, q8 @ line[7,6] = (t5|t6 - t1|t2) >> 1
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vshr.s16 q9, q1, #(\rshift - 1) @ one shift is already done by vhadd/vhsub above
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vshr.s16 q8, q0, #(\rshift - 1)
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vshr.s16 q10, q2, #(\rshift - 1)
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vshr.s16 q11, q3, #(\rshift - 1)
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@ This is modeled after the first and second for loop in vc1_inv_trans_8x8_c.
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@ Input columns: q8, q9, q10, q11, q12, q13, q14, q15
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@ Output columns: q8, q9, q10, q11, q12, q13, q14, q15
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@ Trashes all NEON registers (and r12) except for: q4 q5 q6 q7
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.macro vc1_inv_trans_8x8_helper add add1beforeshift rshift
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@ This actually computes half of t1, t2, t3, t4, as explained below
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vmov.i16 q0, #(6 / 2) @ q0 = #6/2
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vshl.i16 q1, q10, #3 @ t3 = 16/2 * src[16]
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vshl.i16 q3, q14, #3 @ temp4 = 16/2 * src[48]
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vmul.i16 q2, q10, q0 @ t4 = 6/2 * src[16]
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vmla.i16 q1, q14, q0 @ t3 += 6/2 * src[48]
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@ unused: q0, q10, q14
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vmov.i16 q0, #(12 / 2) @ q0 = #12/2
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vadd.i16 q10, q8, q12 @ temp1 = src[0] + src[32]
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vsub.i16 q14, q8, q12 @ temp2 = src[0] - src[32]
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vmov.i16 q8, #(\add / 2) @ t1 will accumulate here
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vmov.i16 q12, #(\add / 2) @ t2 will accumulate here
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vsub.i16 q2, q2, q3 @ t4 = 6/2 * src[16] - 16/2 * src[48]
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vmla.i16 q8, q10, q0 @ t1 = 12/2 * temp1 + add
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vmla.i16 q12, q14, q0 @ t2 = 12/2 * temp2 + add
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@ unused: q3, q10, q14
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@ unused: q3, q10, q14
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vshl.i16 q3, q9, #4 @ t1 = 16 * src[8]
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vshl.i16 q10, q9, #2 @ t4 = 4 * src[8]
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vmul.i16 q14, q9, d0[0] @ t2 = 15 * src[8]
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vmul.i16 q9, q9, d0[1] @ t3 = 9 * src[8]
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vmla.i16 q3, q11, d0[0] @ t1 += 15 * src[24]
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vmls.i16 q10, q11, d0[1] @ t4 -= 9 * src[24]
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vmls.i16 q14, q11, d1[1] @ t2 -= 4 * src[24]
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vmls.i16 q9, q11, d1[0] @ t3 -= 16 * src[24]
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vmla.i16 q3, q13, d0[1] @ t1 += 9 * src[40]
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vmla.i16 q10, q13, d0[0] @ t4 += 15 * src[40]
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vmls.i16 q14, q13, d1[0] @ t2 -= 16 * src[40]
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vmla.i16 q9, q13, d1[1] @ t3 += 4 * src[40]
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@ Compute t5, t6, t7, t8 from old t1, t2, t3, t4. Actually, it computes
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@ half of t5, t6, t7, t8 since t1, t2, t3, t4 are halved.
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vadd.i16 q11, q8, q1 @ t5 = t1 + t3
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vsub.i16 q1, q8, q1 @ t8 = t1 - t3
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vadd.i16 q13, q12, q2 @ t6 = t2 + t4
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vsub.i16 q2, q12, q2 @ t7 = t2 - t4
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vmla.i16 q3, q15, d1[1] @ t1 += 4 * src[56]
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vmls.i16 q14, q15, d0[1] @ t2 -= 9 * src[56]
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vmla.i16 q9, q15, d0[0] @ t3 += 15 * src[56]
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vmls.i16 q10, q15, d1[0] @ t4 -= 16 * src[56]
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@ unused: q0, q8, q15
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@ tNhalf is half of the value of tN (as described in vc1_inv_trans_8x8_c).
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@ This is done because sometimes files have input that causes tN + tM to
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@ overflow. To avoid this overflow, we compute tNhalf, then compute
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@ tNhalf + tM (which doesn't overflow), and then we use vhadd to compute
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@ (tNhalf + (tNhalf + tM)) >> 1 which does not overflow because it is
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@ For each pair of tN and tM, do:
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@ lineA = t5half + t1
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@ if add1beforeshift: t1 -= 1
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@ lineA = (t5half + lineA) >> 1
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@ lineB = t5half - t1
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@ lineB = (t5half + lineB) >> 1
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@ lineA >>= rshift - 1
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@ lineB >>= rshift - 1
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vadd.i16 q8, q11, q3 @ q8 = t5half + t1
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vsub.i16 q3, q3, q12 @ q3 = t1 - 1
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vadd.i16 q0, q13, q14 @ q0 = t6half + t2
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vsub.i16 q14, q14, q12 @ q14 = t2 - 1
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vadd.i16 q15, q2, q9 @ q15 = t7half + t3
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vsub.i16 q9, q9, q12 @ q9 = t3 - 1
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vhadd.s16 q8, q11, q8 @ q8 = (t5half + t5half + t1) >> 1
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vsub.i16 q3, q11, q3 @ q3 = t5half - t1 + 1
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vhadd.s16 q0, q13, q0 @ q0 = (t6half + t6half + t2) >> 1
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vsub.i16 q14, q13, q14 @ q14 = t6half - t2 + 1
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vhadd.s16 q15, q2, q15 @ q15 = (t7half + t7half + t3) >> 1
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vsub.i16 q9, q2, q9 @ q9 = t7half - t3 + 1
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vhadd.s16 q3, q11, q3 @ q3 = (t5half + t5half - t1 + 1) >> 1
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vadd.i16 q11, q1, q10 @ q11 = t8half + t4
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vsub.i16 q10, q10, q12 @ q10 = t4 - 1
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vhadd.s16 q14, q13, q14 @ q14 = (t6half + t6half - t2 + 1) >> 1
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vhadd.s16 q13, q2, q9 @ q9 = (t7half + t7half - t3 + 1) >> 1
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@ unused: q12, q2, q9
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vsub.i16 q10, q1, q10 @ q10 = t8half - t4 + 1
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vhadd.s16 q11, q1, q11 @ q11 = (t8half + t8half + t4) >> 1
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vshr.s16 q8, q8, #(\rshift - 1) @ q8 = line[0]
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vhadd.s16 q12, q1, q10 @ q12 = (t8half + t8half - t4 + 1) >> 1
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vshr.s16 q9, q0, #(\rshift - 1) @ q9 = line[1]
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vshr.s16 q10, q15, #(\rshift - 1) @ q10 = line[2]
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vshr.s16 q11, q11, #(\rshift - 1) @ q11 = line[3]
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vshr.s16 q12, q12, #(\rshift - 1) @ q12 = line[4]
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vshr.s16 q13, q13, #(\rshift - 1) @ q13 = line[5]
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vshr.s16 q14, q14, #(\rshift - 1) @ q14 = line[6]
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vshr.s16 q15, q3, #(\rshift - 1) @ q15 = line[7]
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@ (int16_t *block [r0])
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function ff_vc1_inv_trans_8x8_neon, export=1
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vld1.64 {q8-q9}, [r0,:128]!
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vld1.64 {q10-q11}, [r0,:128]!
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vld1.64 {q12-q13}, [r0,:128]!
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vld1.64 {q14-q15}, [r0,:128]
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sub r0, r0, #(16 * 2 * 3) @ restore r0
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vc1_inv_trans_8x8_helper add=4 add1beforeshift=0 rshift=3
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@ Transpose result matrix of 8x8
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swap4 d17, d19, d21, d23, d24, d26, d28, d30
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transpose16_4x4 q8, q9, q10, q11, q12, q13, q14, q15
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vc1_inv_trans_8x8_helper add=64 add1beforeshift=1 rshift=7
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vst1.64 {q8-q9}, [r0,:128]!
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vst1.64 {q10-q11}, [r0,:128]!
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vst1.64 {q12-q13}, [r0,:128]!
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vst1.64 {q14-q15}, [r0,:128]
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@ (uint8_t *dest [r0], int linesize [r1], int16_t *block [r2])
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function ff_vc1_inv_trans_8x4_neon, export=1
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vld1.64 {q0-q1}, [r2,:128]! @ load 8 * 4 * 2 = 64 bytes / 16 bytes per quad = 4 quad registers
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vld1.64 {q2-q3}, [r2,:128]
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transpose16 q0 q1 q2 q3 @ transpose rows to columns
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vc1_inv_trans_8x4_helper add=4 add1beforeshift=0 rshift=3
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@ Move output to more standardized registers
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transpose16 q0 q1 q2 q3 @ turn columns into rows
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vc1_inv_trans_4x8_helper add=64 rshift=7
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@ unused registers: q12, q13, q14, q15
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vld1.64 {d28}, [r0,:64], r1 @ read dest
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vld1.64 {d29}, [r0,:64], r1
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vld1.64 {d30}, [r0,:64], r1
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vld1.64 {d31}, [r0,:64], r1
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sub r0, r0, r1, lsl #2 @ restore original r0 value
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vaddw.u8 q0, q0, d28 @ line[0] += dest[0]
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vaddw.u8 q1, q1, d29 @ line[1] += dest[1]
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vaddw.u8 q2, q2, d30 @ line[2] += dest[2]
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vaddw.u8 q3, q3, d31 @ line[3] += dest[3]
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vqmovun.s16 d0, q0 @ line[0]
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vqmovun.s16 d1, q1 @ line[1]
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vqmovun.s16 d2, q2 @ line[2]
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vqmovun.s16 d3, q3 @ line[3]
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vst1.64 {d0}, [r0,:64], r1 @ write dest
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vst1.64 {d1}, [r0,:64], r1
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vst1.64 {d2}, [r0,:64], r1
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vst1.64 {d3}, [r0,:64]
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@ (uint8_t *dest [r0], int linesize [r1], int16_t *block [r2])
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function ff_vc1_inv_trans_4x8_neon, export=1
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mov r12, #(8 * 2) @ 8 elements per line, each element 2 bytes
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vld4.16 {d0[], d2[], d4[], d6[]}, [r2,:64], r12 @ read each column into a q register
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vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r2,:64], r12
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vld4.16 {d0[2], d2[2], d4[2], d6[2]}, [r2,:64], r12
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vld4.16 {d0[3], d2[3], d4[3], d6[3]}, [r2,:64], r12
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vld4.16 {d1[], d3[], d5[], d7[]}, [r2,:64], r12
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vld4.16 {d1[1], d3[1], d5[1], d7[1]}, [r2,:64], r12
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vld4.16 {d1[2], d3[2], d5[2], d7[2]}, [r2,:64], r12
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vld4.16 {d1[3], d3[3], d5[3], d7[3]}, [r2,:64]
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vc1_inv_trans_4x8_helper add=4 rshift=3
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transpose16 q0 q1 q2 q3 @ Transpose rows (registers) into columns
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vc1_inv_trans_8x4_helper add=64 add1beforeshift=1 rshift=7
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vld1.32 {d28[]}, [r0,:32], r1 @ read dest
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vld1.32 {d28[1]}, [r0,:32], r1
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vld1.32 {d29[]}, [r0,:32], r1
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vld1.32 {d29[1]}, [r0,:32], r1
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vld1.32 {d30[]}, [r0,:32], r1
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vld1.32 {d30[0]}, [r0,:32], r1
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vld1.32 {d31[]}, [r0,:32], r1
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vld1.32 {d31[0]}, [r0,:32], r1
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sub r0, r0, r1, lsl #3 @ restore original r0 value
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vaddw.u8 q8, q8, d28 @ line[0,1] += dest[0,1]
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vaddw.u8 q9, q9, d29 @ line[2,3] += dest[2,3]
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vaddw.u8 q10, q10, d30 @ line[5,4] += dest[5,4]
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vaddw.u8 q11, q11, d31 @ line[7,6] += dest[7,6]
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vqmovun.s16 d16, q8 @ clip(line[0,1])
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vqmovun.s16 d18, q9 @ clip(line[2,3])
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vqmovun.s16 d20, q10 @ clip(line[5,4])
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vqmovun.s16 d22, q11 @ clip(line[7,6])
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vst1.32 {d16[0]}, [r0,:32], r1 @ write dest
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vst1.32 {d16[1]}, [r0,:32], r1
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vst1.32 {d18[0]}, [r0,:32], r1
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vst1.32 {d18[1]}, [r0,:32], r1
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vst1.32 {d20[1]}, [r0,:32], r1
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vst1.32 {d20[0]}, [r0,:32], r1
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vst1.32 {d22[1]}, [r0,:32], r1
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vst1.32 {d22[0]}, [r0,:32]
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@ Setup constants in registers which are used by vc1_inv_trans_4x4_helper
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.macro vc1_inv_trans_4x4_helper_setup
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vmov.i16 d30, #10 @ only need double-word, not quad-word
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@ This is modeled after the first for loop in vc1_inv_trans_4x4_c.
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.macro vc1_inv_trans_4x4_helper add rshift
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vmov.i16 q2, #\add @ t1|t2 will accumulate here
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vadd.i16 d16, d0, d1 @ temp1 = src[0] + src[2]
582
vsub.i16 d17, d0, d1 @ temp2 = src[0] - src[2]
583
vmul.i16 q3, q14, q1 @ t3|t4 = 22 * (src[1]|src[3])
584
vmla.i16 q2, q13, q8 @ t1|t2 = 17 * (temp1|temp2) + add
585
vmla.i16 d6, d30, d3 @ t3 += 10 * src[3]
586
vmls.i16 d7, d30, d2 @ t4 -= 10 * src[1]
588
vadd.i16 q0, q2, q3 @ dst[0,2] = (t1|t2 + t3|t4)
589
vsub.i16 q1, q2, q3 @ dst[3,1] = (t1|t2 - t3|t4)
590
vshr.s16 q0, q0, #\rshift @ dst[0,2] >>= rshift
591
vshr.s16 q1, q1, #\rshift @ dst[3,1] >>= rshift
594
@ (uint8_t *dest [r0], int linesize [r1], int16_t *block [r2])
595
function ff_vc1_inv_trans_4x4_neon, export=1
596
mov r12, #(8 * 2) @ 8 elements per line, each element 2 bytes
597
vld4.16 {d0[], d1[], d2[], d3[]}, [r2,:64], r12 @ read each column into a register
598
vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r2,:64], r12
599
vld4.16 {d0[2], d1[2], d2[2], d3[2]}, [r2,:64], r12
600
vld4.16 {d0[3], d1[3], d2[3], d3[3]}, [r2,:64]
602
vswp d1, d2 @ so that we can later access column 1 and column 3 as a single q1 register
604
vc1_inv_trans_4x4_helper_setup
612
vc1_inv_trans_4x4_helper add=4 rshift=3 @ compute t1, t2, t3, t4 and combine them into dst[0-3]
620
transpose16 d0 d3 d1 d2 @ Transpose rows (registers) into columns
628
vswp d2, d3 @ so that we can later access column 1 and column 3 in order as a single q1 register
636
vc1_inv_trans_4x4_helper add=64 rshift=7 @ compute t1, t2, t3, t4 and combine them into dst[0-3]
644
vld1.32 {d18[]}, [r0,:32], r1 @ read dest
645
vld1.32 {d19[]}, [r0,:32], r1
646
vld1.32 {d18[1]}, [r0,:32], r1
647
vld1.32 {d19[0]}, [r0,:32], r1
648
sub r0, r0, r1, lsl #2 @ restore original r0 value
650
vaddw.u8 q0, q0, d18 @ line[0,2] += dest[0,2]
651
vaddw.u8 q1, q1, d19 @ line[3,1] += dest[3,1]
653
vqmovun.s16 d0, q0 @ clip(line[0,2])
654
vqmovun.s16 d1, q1 @ clip(line[3,1])
656
vst1.32 {d0[0]}, [r0,:32], r1 @ write dest
657
vst1.32 {d1[1]}, [r0,:32], r1
658
vst1.32 {d0[1]}, [r0,:32], r1
659
vst1.32 {d1[0]}, [r0,:32]
664
@ The absolute value of multiplication constants from vc1_mspel_filter and vc1_mspel_{ver,hor}_filter_16bits.
665
@ The sign is embedded in the code below that carries out the multiplication (mspel_filter{,.16}).
666
#define MSPEL_MODE_1_MUL_CONSTANTS 4 53 18 3
667
#define MSPEL_MODE_2_MUL_CONSTANTS 1 9 9 1
668
#define MSPEL_MODE_3_MUL_CONSTANTS 3 18 53 4
670
@ These constants are from reading the source code of vc1_mspel_mc and determining the value that
671
@ is added to `rnd` to result in the variable `r`, and the value of the variable `shift`.
672
#define MSPEL_MODES_11_ADDSHIFT_CONSTANTS 15 5
673
#define MSPEL_MODES_12_ADDSHIFT_CONSTANTS 3 3
674
#define MSPEL_MODES_13_ADDSHIFT_CONSTANTS 15 5
675
#define MSPEL_MODES_21_ADDSHIFT_CONSTANTS MSPEL_MODES_12_ADDSHIFT_CONSTANTS
676
#define MSPEL_MODES_22_ADDSHIFT_CONSTANTS 0 1
677
#define MSPEL_MODES_23_ADDSHIFT_CONSTANTS 3 3
678
#define MSPEL_MODES_31_ADDSHIFT_CONSTANTS MSPEL_MODES_13_ADDSHIFT_CONSTANTS
679
#define MSPEL_MODES_32_ADDSHIFT_CONSTANTS MSPEL_MODES_23_ADDSHIFT_CONSTANTS
680
#define MSPEL_MODES_33_ADDSHIFT_CONSTANTS 15 5
682
@ The addition and shift constants from vc1_mspel_filter.
683
#define MSPEL_MODE_1_ADDSHIFT_CONSTANTS 32 6
684
#define MSPEL_MODE_2_ADDSHIFT_CONSTANTS 8 4
685
#define MSPEL_MODE_3_ADDSHIFT_CONSTANTS 32 6
687
@ Setup constants in registers for a subsequent use of mspel_filter{,.16}.
688
.macro mspel_constants typesize reg_a reg_b reg_c reg_d filter_a filter_b filter_c filter_d reg_add filter_add_register
689
@ Define double-word register aliases. Typesize should be i8 or i16.
690
ra .dn \reg_a\().\typesize
691
rb .dn \reg_b\().\typesize
692
rc .dn \reg_c\().\typesize
693
rd .dn \reg_d\().\typesize
695
@ Only set the register if the value is not 1 and unique
697
vmov ra, #\filter_a @ ra = filter_a
699
vmov rb, #\filter_b @ rb = filter_b
700
.if \filter_b != \filter_c
701
vmov rc, #\filter_c @ rc = filter_c
704
vmov rd, #\filter_d @ rd = filter_d
706
@ vdup to double the size of typesize
708
vdup.16 \reg_add, \filter_add_register @ reg_add = filter_add_register
710
vdup.32 \reg_add, \filter_add_register @ reg_add = filter_add_register
719
@ After mspel_constants has been used, do the filtering.
720
.macro mspel_filter acc dest src0 src1 src2 src3 filter_a filter_b filter_c filter_d reg_a reg_b reg_c reg_d reg_add filter_shift narrow=1
722
@ If filter_a != 1, then we need a move and subtract instruction
723
vmov \acc, \reg_add @ acc = reg_add
724
vmlsl.u8 \acc, \reg_a, \src0 @ acc -= filter_a * src[-stride]
726
@ If filter_a is 1, then just subtract without an extra move
727
vsubw.u8 \acc, \reg_add, \src0 @ acc = reg_add - src[-stride] @ since filter_a == 1
729
vmlal.u8 \acc, \reg_b, \src1 @ acc += filter_b * src[0]
730
.if \filter_b != \filter_c
731
vmlal.u8 \acc, \reg_c, \src2 @ acc += filter_c * src[stride]
733
@ If filter_b is the same as filter_c, use the same reg_b register
734
vmlal.u8 \acc, \reg_b, \src2 @ acc += filter_c * src[stride] @ where filter_c == filter_b
737
@ If filter_d != 1, then do a multiply accumulate
738
vmlsl.u8 \acc, \reg_d, \src3 @ acc -= filter_d * src[stride * 2]
740
@ If filter_d is 1, then just do a subtract
741
vsubw.u8 \acc, \acc, \src3 @ acc -= src[stride * 2] @ since filter_d == 1
744
vqshrun.s16 \dest, \acc, #\filter_shift @ dest = clip_uint8(acc >> filter_shift)
746
vshr.s16 \dest, \acc, #\filter_shift @ dest = acc >> filter_shift
750
@ This is similar to mspel_filter, but the input is 16-bit instead of 8-bit and narrow=0 is not supported.
751
.macro mspel_filter.16 acc0 acc1 acc0_0 acc0_1 dest src0 src1 src2 src3 src4 src5 src6 src7 filter_a filter_b filter_c filter_d reg_a reg_b reg_c reg_d reg_add filter_shift
755
vmlsl.s16 \acc0, \reg_a, \src0
756
vmlsl.s16 \acc1, \reg_a, \src1
758
vsubw.s16 \acc0, \reg_add, \src0
759
vsubw.s16 \acc1, \reg_add, \src1
761
vmlal.s16 \acc0, \reg_b, \src2
762
vmlal.s16 \acc1, \reg_b, \src3
763
.if \filter_b != \filter_c
764
vmlal.s16 \acc0, \reg_c, \src4
765
vmlal.s16 \acc1, \reg_c, \src5
767
vmlal.s16 \acc0, \reg_b, \src4
768
vmlal.s16 \acc1, \reg_b, \src5
771
vmlsl.s16 \acc0, \reg_d, \src6
772
vmlsl.s16 \acc1, \reg_d, \src7
774
vsubw.s16 \acc0, \acc0, \src6
775
vsubw.s16 \acc1, \acc1, \src7
777
@ Use acc0_0 and acc0_1 as temp space
778
vqshrun.s32 \acc0_0, \acc0, #\filter_shift @ Shift and narrow with saturation from s32 to u16
779
vqshrun.s32 \acc0_1, \acc1, #\filter_shift
780
vqmovn.u16 \dest, \acc0 @ Narrow with saturation from u16 to u8
783
@ Register usage for put_vc1_mspel_mc functions. Registers marked 'hv' are only used in put_vc1_mspel_mc_hv.
796
@ q0 [hv] src[-stride]
798
@ q2 [hv] src[stride]
799
@ q3 [hv] src[stride * 2]
800
@ d21 often result from mspel_filter
802
@ q12 [hv] accumulator 1
803
@ q13 accumulator initial value
809
@ (uint8_t *dst [r0], const uint8_t *src [r1], ptrdiff_t stride [r2], int rnd [r3])
810
.macro put_vc1_mspel_mc_hv hmode vmode filter_h_a filter_h_b filter_h_c filter_h_d filter_v_a filter_v_b filter_v_c filter_v_d filter_add filter_shift
811
function ff_put_vc1_mspel_mc\hmode\()\vmode\()_neon, export=1
813
mov r11, sp @ r11 = stack pointer before realignmnet
814
A bic sp, sp, #15 @ sp = round down to multiple of 16 bytes
817
sub sp, sp, #(8*2*16) @ make space for 8 rows * 2 byte per element * 16 elements per row (to fit 11 actual elements per row)
818
mov r4, sp @ r4 = int16_t tmp[8 * 16]
820
sub r1, r1, #1 @ src -= 1
822
add r3, r3, #\filter_add @ r3 = filter_add + rnd
824
mov r12, #8 @ loop counter
825
sub r1, r1, r2 @ r1 = &src[-stride] @ slide back
827
@ Do vertical filtering from src into tmp
828
mspel_constants i8 d28 d29 d30 d31 \filter_v_a \filter_v_b \filter_v_c \filter_v_d q13 r3
830
vld1.64 {d0,d1}, [r1], r2
831
vld1.64 {d2,d3}, [r1], r2
832
vld1.64 {d4,d5}, [r1], r2
837
vld1.64 {d6,d7}, [r1], r2
838
mspel_filter q11 q11 d0 d2 d4 d6 \filter_v_a \filter_v_b \filter_v_c \filter_v_d d28 d29 d30 d31 q13 \filter_shift narrow=0
839
mspel_filter q12 q12 d1 d3 d5 d7 \filter_v_a \filter_v_b \filter_v_c \filter_v_d d28 d29 d30 d31 q13 \filter_shift narrow=0
840
vst1.64 {q11,q12}, [r4,:128]! @ store and increment
842
vld1.64 {d0,d1}, [r1], r2
843
mspel_filter q11 q11 d2 d4 d6 d0 \filter_v_a \filter_v_b \filter_v_c \filter_v_d d28 d29 d30 d31 q13 \filter_shift narrow=0
844
mspel_filter q12 q12 d3 d5 d7 d1 \filter_v_a \filter_v_b \filter_v_c \filter_v_d d28 d29 d30 d31 q13 \filter_shift narrow=0
845
vst1.64 {q11,q12}, [r4,:128]! @ store and increment
847
vld1.64 {d2,d3}, [r1], r2
848
mspel_filter q11 q11 d4 d6 d0 d2 \filter_v_a \filter_v_b \filter_v_c \filter_v_d d28 d29 d30 d31 q13 \filter_shift narrow=0
849
mspel_filter q12 q12 d5 d7 d1 d3 \filter_v_a \filter_v_b \filter_v_c \filter_v_d d28 d29 d30 d31 q13 \filter_shift narrow=0
850
vst1.64 {q11,q12}, [r4,:128]! @ store and increment
852
vld1.64 {d4,d5}, [r1], r2
853
mspel_filter q11 q11 d6 d0 d2 d4 \filter_v_a \filter_v_b \filter_v_c \filter_v_d d28 d29 d30 d31 q13 \filter_shift narrow=0
854
mspel_filter q12 q12 d7 d1 d3 d5 \filter_v_a \filter_v_b \filter_v_c \filter_v_d d28 d29 d30 d31 q13 \filter_shift narrow=0
855
vst1.64 {q11,q12}, [r4,:128]! @ store and increment
859
rsb r3, r3, #(64 + \filter_add) @ r3 = (64 + filter_add) - r3
860
mov r12, #8 @ loop counter
861
mov r4, sp @ r4 = tmp
863
@ Do horizontal filtering from temp to dst
864
mspel_constants i16 d28 d29 d30 d31 \filter_h_a \filter_h_b \filter_h_c \filter_h_d q13 r3
869
vld1.64 {q0,q1}, [r4,:128]! @ read one line of tmp
870
vext.16 q2, q0, q1, #2
871
vext.16 q3, q0, q1, #3
872
vext.16 q1, q0, q1, #1 @ do last because it writes to q1 which is read by the other vext instructions
874
mspel_filter.16 q11 q12 d22 d23 d21 d0 d1 d2 d3 d4 d5 d6 d7 \filter_h_a \filter_h_b \filter_h_c \filter_h_d d28 d29 d30 d31 q13 7
876
vst1.64 {d21}, [r0,:64], r2 @ store and increment dst
885
@ Use C preprocessor and assembler macros to expand to functions for horizontal and vertical filtering.
886
#define PUT_VC1_MSPEL_MC_HV(hmode, vmode) \
887
put_vc1_mspel_mc_hv hmode vmode \
888
MSPEL_MODE_ ## hmode ## _MUL_CONSTANTS \
889
MSPEL_MODE_ ## vmode ## _MUL_CONSTANTS \
890
MSPEL_MODES_ ## hmode ## vmode ## _ADDSHIFT_CONSTANTS
892
PUT_VC1_MSPEL_MC_HV(1, 1)
893
PUT_VC1_MSPEL_MC_HV(1, 2)
894
PUT_VC1_MSPEL_MC_HV(1, 3)
895
PUT_VC1_MSPEL_MC_HV(2, 1)
896
PUT_VC1_MSPEL_MC_HV(2, 2)
897
PUT_VC1_MSPEL_MC_HV(2, 3)
898
PUT_VC1_MSPEL_MC_HV(3, 1)
899
PUT_VC1_MSPEL_MC_HV(3, 2)
900
PUT_VC1_MSPEL_MC_HV(3, 3)
902
#undef PUT_VC1_MSPEL_MC_HV
904
.macro put_vc1_mspel_mc_h_only hmode filter_a filter_b filter_c filter_d filter_add filter_shift
905
function ff_put_vc1_mspel_mc\hmode\()0_neon, export=1
906
rsb r3, r3, #\filter_add @ r3 = filter_add - r = filter_add - rnd
907
mov r12, #8 @ loop counter
908
sub r1, r1, #1 @ slide back, using immediate
910
mspel_constants i8 d28 d29 d30 d31 \filter_a \filter_b \filter_c \filter_d q13 r3
915
vld1.64 {d0,d1}, [r1], r2 @ read 16 bytes even though we only need 11, also src += stride
916
vext.8 d2, d0, d1, #2
917
vext.8 d3, d0, d1, #3
918
vext.8 d1, d0, d1, #1 @ do last because it writes to d1 which is read by the other vext instructions
920
mspel_filter q11 d21 d0 d1 d2 d3 \filter_a \filter_b \filter_c \filter_d d28 d29 d30 d31 q13 \filter_shift
922
vst1.64 {d21}, [r0,:64], r2 @ store and increment dst
930
@ Use C preprocessor and assembler macros to expand to functions for horizontal only filtering.
931
#define PUT_VC1_MSPEL_MC_H_ONLY(hmode) \
932
put_vc1_mspel_mc_h_only hmode MSPEL_MODE_ ## hmode ## _MUL_CONSTANTS MSPEL_MODE_ ## hmode ## _ADDSHIFT_CONSTANTS
934
PUT_VC1_MSPEL_MC_H_ONLY(1)
935
PUT_VC1_MSPEL_MC_H_ONLY(2)
936
PUT_VC1_MSPEL_MC_H_ONLY(3)
938
#undef PUT_VC1_MSPEL_MC_H_ONLY
940
@ (uint8_t *dst [r0], const uint8_t *src [r1], ptrdiff_t stride [r2], int rnd [r3])
941
.macro put_vc1_mspel_mc_v_only vmode filter_a filter_b filter_c filter_d filter_add filter_shift
942
function ff_put_vc1_mspel_mc0\vmode\()_neon, export=1
943
add r3, r3, #\filter_add - 1 @ r3 = filter_add - r = filter_add - (1 - rnd) = filter_add - 1 + rnd
944
mov r12, #8 @ loop counter
945
sub r1, r1, r2 @ r1 = &src[-stride] @ slide back
947
mspel_constants i8 d28 d29 d30 d31 \filter_a \filter_b \filter_c \filter_d q13 r3
949
vld1.64 {d0}, [r1], r2 @ d0 = src[-stride]
950
vld1.64 {d1}, [r1], r2 @ d1 = src[0]
951
vld1.64 {d2}, [r1], r2 @ d2 = src[stride]
956
vld1.64 {d3}, [r1], r2 @ d3 = src[stride * 2]
957
mspel_filter q11 d21 d0 d1 d2 d3 \filter_a \filter_b \filter_c \filter_d d28 d29 d30 d31 q13 \filter_shift
958
vst1.64 {d21}, [r0,:64], r2 @ store and increment dst
960
vld1.64 {d0}, [r1], r2 @ d0 = next line
961
mspel_filter q11 d21 d1 d2 d3 d0 \filter_a \filter_b \filter_c \filter_d d28 d29 d30 d31 q13 \filter_shift
962
vst1.64 {d21}, [r0,:64], r2 @ store and increment dst
964
vld1.64 {d1}, [r1], r2 @ d1 = next line
965
mspel_filter q11 d21 d2 d3 d0 d1 \filter_a \filter_b \filter_c \filter_d d28 d29 d30 d31 q13 \filter_shift
966
vst1.64 {d21}, [r0,:64], r2 @ store and increment dst
968
vld1.64 {d2}, [r1], r2 @ d2 = next line
969
mspel_filter q11 d21 d3 d0 d1 d2 \filter_a \filter_b \filter_c \filter_d d28 d29 d30 d31 q13 \filter_shift
970
vst1.64 {d21}, [r0,:64], r2 @ store and increment dst
978
@ Use C preprocessor and assembler macros to expand to functions for vertical only filtering.
979
#define PUT_VC1_MSPEL_MC_V_ONLY(vmode) \
980
put_vc1_mspel_mc_v_only vmode MSPEL_MODE_ ## vmode ## _MUL_CONSTANTS MSPEL_MODE_ ## vmode ## _ADDSHIFT_CONSTANTS
982
PUT_VC1_MSPEL_MC_V_ONLY(1)
983
PUT_VC1_MSPEL_MC_V_ONLY(2)
984
PUT_VC1_MSPEL_MC_V_ONLY(3)
986
#undef PUT_VC1_MSPEL_MC_V_ONLY
988
function ff_put_pixels8x8_neon, export=1
989
vld1.64 {d0}, [r1], r2
990
vld1.64 {d1}, [r1], r2
991
vld1.64 {d2}, [r1], r2
992
vld1.64 {d3}, [r1], r2
993
vld1.64 {d4}, [r1], r2
994
vld1.64 {d5}, [r1], r2
995
vld1.64 {d6}, [r1], r2
997
vst1.64 {d0}, [r0,:64], r2
998
vst1.64 {d1}, [r0,:64], r2
999
vst1.64 {d2}, [r0,:64], r2
1000
vst1.64 {d3}, [r0,:64], r2
1001
vst1.64 {d4}, [r0,:64], r2
1002
vst1.64 {d5}, [r0,:64], r2
1003
vst1.64 {d6}, [r0,:64], r2
1004
vst1.64 {d7}, [r0,:64]
1008
function ff_vc1_inv_trans_8x8_dc_neon, export=1
1009
ldrsh r2, [r2] @ int dc = block[0];
1011
vld1.64 {d0}, [r0,:64], r1
1012
vld1.64 {d1}, [r0,:64], r1
1013
vld1.64 {d4}, [r0,:64], r1
1014
vld1.64 {d5}, [r0,:64], r1
1016
add r2, r2, r2, lsl #1 @ dc = (3 * dc + 1) >> 1;
1017
vld1.64 {d6}, [r0,:64], r1
1019
vld1.64 {d7}, [r0,:64], r1
1020
vld1.64 {d16}, [r0,:64], r1
1021
vld1.64 {d17}, [r0,:64], r1
1024
sub r0, r0, r1, lsl #3 @ restore r0 to original value
1026
add r2, r2, r2, lsl #1 @ dc = (3 * dc + 16) >> 5;
1033
vaddw.u8 q10, q1, d1
1034
vaddw.u8 q11, q1, d4
1035
vaddw.u8 q12, q1, d5
1039
vst1.64 {d0}, [r0,:64], r1
1041
vst1.64 {d1}, [r0,:64], r1
1042
vaddw.u8 q13, q1, d6
1043
vst1.64 {d4}, [r0,:64], r1
1044
vaddw.u8 q14, q1, d7
1045
vst1.64 {d5}, [r0,:64], r1
1046
vaddw.u8 q15, q1, d16
1047
vaddw.u8 q1, q1, d17 @ this destroys q1
1050
vqmovun.s16 d16, q15
1052
vst1.64 {d6}, [r0,:64], r1
1053
vst1.64 {d7}, [r0,:64], r1
1054
vst1.64 {d16}, [r0,:64], r1
1055
vst1.64 {d17}, [r0,:64]
1059
function ff_vc1_inv_trans_8x4_dc_neon, export=1
1060
ldrsh r2, [r2] @ int dc = block[0];
1062
vld1.64 {d0}, [r0,:64], r1
1063
vld1.64 {d1}, [r0,:64], r1
1064
vld1.64 {d4}, [r0,:64], r1
1065
vld1.64 {d5}, [r0,:64], r1
1067
add r2, r2, r2, lsl #1 @ dc = ( 3 * dc + 1) >> 1;
1069
sub r0, r0, r1, lsl #2 @ restore r0 to original value
1074
add r2, r2, r2, lsl #4 @ dc = (17 * dc + 64) >> 7;
1083
vaddw.u8 q10, q1, d5
1087
vst1.64 {d0}, [r0,:64], r1
1089
vst1.64 {d1}, [r0,:64], r1
1090
vst1.64 {d4}, [r0,:64], r1
1091
vst1.64 {d5}, [r0,:64]
1095
function ff_vc1_inv_trans_4x8_dc_neon, export=1
1096
ldrsh r2, [r2] @ int dc = block[0];
1098
vld1.32 {d0[]}, [r0,:32], r1
1099
vld1.32 {d1[]}, [r0,:32], r1
1100
vld1.32 {d0[1]}, [r0,:32], r1
1101
vld1.32 {d1[1]}, [r0,:32], r1
1103
add r2, r2, r2, lsl #4 @ dc = (17 * dc + 4) >> 3;
1104
vld1.32 {d4[]}, [r0,:32], r1
1106
vld1.32 {d5[]}, [r0,:32], r1
1107
vld1.32 {d4[1]}, [r0,:32], r1
1109
vld1.32 {d5[1]}, [r0,:32], r1
1111
add r2, r2, r2, lsl #1 @ dc = (12 * dc + 64) >> 7;
1113
sub r0, r0, r1, lsl #3 @ restore r0 to original value
1124
vaddw.u8 q10, q1, d5
1126
vst1.32 {d0[0]}, [r0,:32], r1
1128
vst1.32 {d1[0]}, [r0,:32], r1
1130
vst1.32 {d0[1]}, [r0,:32], r1
1132
vst1.32 {d1[1]}, [r0,:32], r1
1133
vst1.32 {d4[0]}, [r0,:32], r1
1134
vst1.32 {d5[0]}, [r0,:32], r1
1135
vst1.32 {d4[1]}, [r0,:32], r1
1136
vst1.32 {d5[1]}, [r0,:32]
1140
function ff_vc1_inv_trans_4x4_dc_neon, export=1
1141
ldrsh r2, [r2] @ int dc = block[0];
1143
vld1.32 {d0[]}, [r0,:32], r1
1144
vld1.32 {d1[]}, [r0,:32], r1
1145
vld1.32 {d0[1]}, [r0,:32], r1
1146
vld1.32 {d1[1]}, [r0,:32], r1
1148
add r2, r2, r2, lsl #4 @ dc = (17 * dc + 4) >> 3;
1150
sub r0, r0, r1, lsl #2 @ restore r0 to original value
1155
add r2, r2, r2, lsl #4 @ dc = (17 * dc + 64) >> 7;
1164
vst1.32 {d0[0]}, [r0,:32], r1
1166
vst1.32 {d1[0]}, [r0,:32], r1
1167
vst1.32 {d0[1]}, [r0,:32], r1
1168
vst1.32 {d1[1]}, [r0,:32]
added
removed
libavcodec/arm/vc1dsp_neon.S
